1 /* $NetBSD: qcom,gcc-msm8660.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H 17 #define _DT_BINDINGS_CLK_MSM_GCC_8660_H 18 19 #define AFAB_CLK_SRC 0 20 #define AFAB_CORE_CLK 1 21 #define SCSS_A_CLK 2 22 #define SCSS_H_CLK 3 23 #define SCSS_XO_SRC_CLK 4 24 #define AFAB_EBI1_CH0_A_CLK 5 25 #define AFAB_EBI1_CH1_A_CLK 6 26 #define AFAB_AXI_S0_FCLK 7 27 #define AFAB_AXI_S1_FCLK 8 28 #define AFAB_AXI_S2_FCLK 9 29 #define AFAB_AXI_S3_FCLK 10 30 #define AFAB_AXI_S4_FCLK 11 31 #define SFAB_CORE_CLK 12 32 #define SFAB_AXI_S0_FCLK 13 33 #define SFAB_AXI_S1_FCLK 14 34 #define SFAB_AXI_S2_FCLK 15 35 #define SFAB_AXI_S3_FCLK 16 36 #define SFAB_AXI_S4_FCLK 17 37 #define SFAB_AHB_S0_FCLK 18 38 #define SFAB_AHB_S1_FCLK 19 39 #define SFAB_AHB_S2_FCLK 20 40 #define SFAB_AHB_S3_FCLK 21 41 #define SFAB_AHB_S4_FCLK 22 42 #define SFAB_AHB_S5_FCLK 23 43 #define SFAB_AHB_S6_FCLK 24 44 #define SFAB_ADM0_M0_A_CLK 25 45 #define SFAB_ADM0_M1_A_CLK 26 46 #define SFAB_ADM0_M2_A_CLK 27 47 #define ADM0_CLK 28 48 #define ADM0_PBUS_CLK 29 49 #define SFAB_ADM1_M0_A_CLK 30 50 #define SFAB_ADM1_M1_A_CLK 31 51 #define SFAB_ADM1_M2_A_CLK 32 52 #define MMFAB_ADM1_M3_A_CLK 33 53 #define ADM1_CLK 34 54 #define ADM1_PBUS_CLK 35 55 #define IMEM0_A_CLK 36 56 #define MAHB0_CLK 37 57 #define SFAB_LPASS_Q6_A_CLK 38 58 #define SFAB_AFAB_M_A_CLK 39 59 #define AFAB_SFAB_M0_A_CLK 40 60 #define AFAB_SFAB_M1_A_CLK 41 61 #define DFAB_CLK_SRC 42 62 #define DFAB_CLK 43 63 #define DFAB_CORE_CLK 44 64 #define SFAB_DFAB_M_A_CLK 45 65 #define DFAB_SFAB_M_A_CLK 46 66 #define DFAB_SWAY0_H_CLK 47 67 #define DFAB_SWAY1_H_CLK 48 68 #define DFAB_ARB0_H_CLK 49 69 #define DFAB_ARB1_H_CLK 50 70 #define PPSS_H_CLK 51 71 #define PPSS_PROC_CLK 52 72 #define PPSS_TIMER0_CLK 53 73 #define PPSS_TIMER1_CLK 54 74 #define PMEM_A_CLK 55 75 #define DMA_BAM_H_CLK 56 76 #define SIC_H_CLK 57 77 #define SPS_TIC_H_CLK 58 78 #define SLIMBUS_H_CLK 59 79 #define SLIMBUS_XO_SRC_CLK 60 80 #define CFPB_2X_CLK_SRC 61 81 #define CFPB_CLK 62 82 #define CFPB0_H_CLK 63 83 #define CFPB1_H_CLK 64 84 #define CFPB2_H_CLK 65 85 #define EBI2_2X_CLK 66 86 #define EBI2_CLK 67 87 #define SFAB_CFPB_M_H_CLK 68 88 #define CFPB_MASTER_H_CLK 69 89 #define SFAB_CFPB_S_HCLK 70 90 #define CFPB_SPLITTER_H_CLK 71 91 #define TSIF_H_CLK 72 92 #define TSIF_INACTIVITY_TIMERS_CLK 73 93 #define TSIF_REF_SRC 74 94 #define TSIF_REF_CLK 75 95 #define CE1_H_CLK 76 96 #define CE2_H_CLK 77 97 #define SFPB_H_CLK_SRC 78 98 #define SFPB_H_CLK 79 99 #define SFAB_SFPB_M_H_CLK 80 100 #define SFAB_SFPB_S_H_CLK 81 101 #define RPM_PROC_CLK 82 102 #define RPM_BUS_H_CLK 83 103 #define RPM_SLEEP_CLK 84 104 #define RPM_TIMER_CLK 85 105 #define MODEM_AHB1_H_CLK 86 106 #define MODEM_AHB2_H_CLK 87 107 #define RPM_MSG_RAM_H_CLK 88 108 #define SC_H_CLK 89 109 #define SC_A_CLK 90 110 #define PMIC_ARB0_H_CLK 91 111 #define PMIC_ARB1_H_CLK 92 112 #define PMIC_SSBI2_SRC 93 113 #define PMIC_SSBI2_CLK 94 114 #define SDC1_H_CLK 95 115 #define SDC2_H_CLK 96 116 #define SDC3_H_CLK 97 117 #define SDC4_H_CLK 98 118 #define SDC5_H_CLK 99 119 #define SDC1_SRC 100 120 #define SDC2_SRC 101 121 #define SDC3_SRC 102 122 #define SDC4_SRC 103 123 #define SDC5_SRC 104 124 #define SDC1_CLK 105 125 #define SDC2_CLK 106 126 #define SDC3_CLK 107 127 #define SDC4_CLK 108 128 #define SDC5_CLK 109 129 #define USB_HS1_H_CLK 110 130 #define USB_HS1_XCVR_SRC 111 131 #define USB_HS1_XCVR_CLK 112 132 #define USB_HS2_H_CLK 113 133 #define USB_HS2_XCVR_SRC 114 134 #define USB_HS2_XCVR_CLK 115 135 #define USB_FS1_H_CLK 116 136 #define USB_FS1_XCVR_FS_SRC 117 137 #define USB_FS1_XCVR_FS_CLK 118 138 #define USB_FS1_SYSTEM_CLK 119 139 #define USB_FS2_H_CLK 120 140 #define USB_FS2_XCVR_FS_SRC 121 141 #define USB_FS2_XCVR_FS_CLK 122 142 #define USB_FS2_SYSTEM_CLK 123 143 #define GSBI_COMMON_SIM_SRC 124 144 #define GSBI1_H_CLK 125 145 #define GSBI2_H_CLK 126 146 #define GSBI3_H_CLK 127 147 #define GSBI4_H_CLK 128 148 #define GSBI5_H_CLK 129 149 #define GSBI6_H_CLK 130 150 #define GSBI7_H_CLK 131 151 #define GSBI8_H_CLK 132 152 #define GSBI9_H_CLK 133 153 #define GSBI10_H_CLK 134 154 #define GSBI11_H_CLK 135 155 #define GSBI12_H_CLK 136 156 #define GSBI1_UART_SRC 137 157 #define GSBI1_UART_CLK 138 158 #define GSBI2_UART_SRC 139 159 #define GSBI2_UART_CLK 140 160 #define GSBI3_UART_SRC 141 161 #define GSBI3_UART_CLK 142 162 #define GSBI4_UART_SRC 143 163 #define GSBI4_UART_CLK 144 164 #define GSBI5_UART_SRC 145 165 #define GSBI5_UART_CLK 146 166 #define GSBI6_UART_SRC 147 167 #define GSBI6_UART_CLK 148 168 #define GSBI7_UART_SRC 149 169 #define GSBI7_UART_CLK 150 170 #define GSBI8_UART_SRC 151 171 #define GSBI8_UART_CLK 152 172 #define GSBI9_UART_SRC 153 173 #define GSBI9_UART_CLK 154 174 #define GSBI10_UART_SRC 155 175 #define GSBI10_UART_CLK 156 176 #define GSBI11_UART_SRC 157 177 #define GSBI11_UART_CLK 158 178 #define GSBI12_UART_SRC 159 179 #define GSBI12_UART_CLK 160 180 #define GSBI1_QUP_SRC 161 181 #define GSBI1_QUP_CLK 162 182 #define GSBI2_QUP_SRC 163 183 #define GSBI2_QUP_CLK 164 184 #define GSBI3_QUP_SRC 165 185 #define GSBI3_QUP_CLK 166 186 #define GSBI4_QUP_SRC 167 187 #define GSBI4_QUP_CLK 168 188 #define GSBI5_QUP_SRC 169 189 #define GSBI5_QUP_CLK 170 190 #define GSBI6_QUP_SRC 171 191 #define GSBI6_QUP_CLK 172 192 #define GSBI7_QUP_SRC 173 193 #define GSBI7_QUP_CLK 174 194 #define GSBI8_QUP_SRC 175 195 #define GSBI8_QUP_CLK 176 196 #define GSBI9_QUP_SRC 177 197 #define GSBI9_QUP_CLK 178 198 #define GSBI10_QUP_SRC 179 199 #define GSBI10_QUP_CLK 180 200 #define GSBI11_QUP_SRC 181 201 #define GSBI11_QUP_CLK 182 202 #define GSBI12_QUP_SRC 183 203 #define GSBI12_QUP_CLK 184 204 #define GSBI1_SIM_CLK 185 205 #define GSBI2_SIM_CLK 186 206 #define GSBI3_SIM_CLK 187 207 #define GSBI4_SIM_CLK 188 208 #define GSBI5_SIM_CLK 189 209 #define GSBI6_SIM_CLK 190 210 #define GSBI7_SIM_CLK 191 211 #define GSBI8_SIM_CLK 192 212 #define GSBI9_SIM_CLK 193 213 #define GSBI10_SIM_CLK 194 214 #define GSBI11_SIM_CLK 195 215 #define GSBI12_SIM_CLK 196 216 #define SPDM_CFG_H_CLK 197 217 #define SPDM_MSTR_H_CLK 198 218 #define SPDM_FF_CLK_SRC 199 219 #define SPDM_FF_CLK 200 220 #define SEC_CTRL_CLK 201 221 #define SEC_CTRL_ACC_CLK_SRC 202 222 #define SEC_CTRL_ACC_CLK 203 223 #define TLMM_H_CLK 204 224 #define TLMM_CLK 205 225 #define MARM_CLK_SRC 206 226 #define MARM_CLK 207 227 #define MAHB1_SRC 208 228 #define MAHB1_CLK 209 229 #define SFAB_MSS_S_H_CLK 210 230 #define MAHB2_SRC 211 231 #define MAHB2_CLK 212 232 #define MSS_MODEM_CLK_SRC 213 233 #define MSS_MODEM_CXO_CLK 214 234 #define MSS_SLP_CLK 215 235 #define MSS_SYS_REF_CLK 216 236 #define TSSC_CLK_SRC 217 237 #define TSSC_CLK 218 238 #define PDM_SRC 219 239 #define PDM_CLK 220 240 #define GP0_SRC 221 241 #define GP0_CLK 222 242 #define GP1_SRC 223 243 #define GP1_CLK 224 244 #define GP2_SRC 225 245 #define GP2_CLK 226 246 #define PMEM_CLK 227 247 #define MPM_CLK 228 248 #define EBI1_ASFAB_SRC 229 249 #define EBI1_CLK_SRC 230 250 #define EBI1_CH0_CLK 231 251 #define EBI1_CH1_CLK 232 252 #define SFAB_SMPSS_S_H_CLK 233 253 #define PRNG_SRC 234 254 #define PRNG_CLK 235 255 #define PXO_SRC 236 256 #define LPASS_CXO_CLK 237 257 #define LPASS_PXO_CLK 238 258 #define SPDM_CY_PORT0_CLK 239 259 #define SPDM_CY_PORT1_CLK 240 260 #define SPDM_CY_PORT2_CLK 241 261 #define SPDM_CY_PORT3_CLK 242 262 #define SPDM_CY_PORT4_CLK 243 263 #define SPDM_CY_PORT5_CLK 244 264 #define SPDM_CY_PORT6_CLK 245 265 #define SPDM_CY_PORT7_CLK 246 266 #define PLL0 247 267 #define PLL0_VOTE 248 268 #define PLL5 249 269 #define PLL6 250 270 #define PLL6_VOTE 251 271 #define PLL8 252 272 #define PLL8_VOTE 253 273 #define PLL9 254 274 #define PLL10 255 275 #define PLL11 256 276 #define PLL12 257 277 278 #endif 279