1 /* $NetBSD: pistachio-clk.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (C) 2014 Google, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H 12 #define _DT_BINDINGS_CLOCK_PISTACHIO_H 13 14 /* PLLs */ 15 #define CLK_MIPS_PLL 0 16 #define CLK_AUDIO_PLL 1 17 #define CLK_RPU_V_PLL 2 18 #define CLK_RPU_L_PLL 3 19 #define CLK_SYS_PLL 4 20 #define CLK_WIFI_PLL 5 21 #define CLK_BT_PLL 6 22 23 /* Fixed-factor clocks */ 24 #define CLK_WIFI_DIV4 16 25 #define CLK_WIFI_DIV8 17 26 27 /* Gate clocks */ 28 #define CLK_MIPS 32 29 #define CLK_AUDIO_IN 33 30 #define CLK_AUDIO 34 31 #define CLK_I2S 35 32 #define CLK_SPDIF 36 33 #define CLK_AUDIO_DAC 37 34 #define CLK_RPU_V 38 35 #define CLK_RPU_L 39 36 #define CLK_RPU_SLEEP 40 37 #define CLK_WIFI_PLL_GATE 41 38 #define CLK_RPU_CORE 42 39 #define CLK_WIFI_ADC 43 40 #define CLK_WIFI_DAC 44 41 #define CLK_USB_PHY 45 42 #define CLK_ENET_IN 46 43 #define CLK_ENET 47 44 #define CLK_UART0 48 45 #define CLK_UART1 49 46 #define CLK_PERIPH_SYS 50 47 #define CLK_SPI0 51 48 #define CLK_SPI1 52 49 #define CLK_EVENT_TIMER 53 50 #define CLK_AUX_ADC_INTERNAL 54 51 #define CLK_AUX_ADC 55 52 #define CLK_SD_HOST 56 53 #define CLK_BT 57 54 #define CLK_BT_DIV4 58 55 #define CLK_BT_DIV8 59 56 #define CLK_BT_1MHZ 60 57 58 /* Divider clocks */ 59 #define CLK_MIPS_INTERNAL_DIV 64 60 #define CLK_MIPS_DIV 65 61 #define CLK_AUDIO_DIV 66 62 #define CLK_I2S_DIV 67 63 #define CLK_SPDIF_DIV 68 64 #define CLK_AUDIO_DAC_DIV 69 65 #define CLK_RPU_V_DIV 70 66 #define CLK_RPU_L_DIV 71 67 #define CLK_RPU_SLEEP_DIV 72 68 #define CLK_RPU_CORE_DIV 73 69 #define CLK_USB_PHY_DIV 74 70 #define CLK_ENET_DIV 75 71 #define CLK_UART0_INTERNAL_DIV 76 72 #define CLK_UART0_DIV 77 73 #define CLK_UART1_INTERNAL_DIV 78 74 #define CLK_UART1_DIV 79 75 #define CLK_SYS_INTERNAL_DIV 80 76 #define CLK_SPI0_INTERNAL_DIV 81 77 #define CLK_SPI0_DIV 82 78 #define CLK_SPI1_INTERNAL_DIV 83 79 #define CLK_SPI1_DIV 84 80 #define CLK_EVENT_TIMER_INTERNAL_DIV 85 81 #define CLK_EVENT_TIMER_DIV 86 82 #define CLK_AUX_ADC_INTERNAL_DIV 87 83 #define CLK_AUX_ADC_DIV 88 84 #define CLK_SD_HOST_DIV 89 85 #define CLK_BT_DIV 90 86 #define CLK_BT_DIV4_DIV 91 87 #define CLK_BT_DIV8_DIV 92 88 #define CLK_BT_1MHZ_INTERNAL_DIV 93 89 #define CLK_BT_1MHZ_DIV 94 90 91 /* Mux clocks */ 92 #define CLK_AUDIO_REF_MUX 96 93 #define CLK_MIPS_PLL_MUX 97 94 #define CLK_AUDIO_PLL_MUX 98 95 #define CLK_AUDIO_MUX 99 96 #define CLK_RPU_V_PLL_MUX 100 97 #define CLK_RPU_L_PLL_MUX 101 98 #define CLK_RPU_L_MUX 102 99 #define CLK_WIFI_PLL_MUX 103 100 #define CLK_WIFI_DIV4_MUX 104 101 #define CLK_WIFI_DIV8_MUX 105 102 #define CLK_RPU_CORE_MUX 106 103 #define CLK_SYS_PLL_MUX 107 104 #define CLK_ENET_MUX 108 105 #define CLK_EVENT_TIMER_MUX 109 106 #define CLK_SD_HOST_MUX 110 107 #define CLK_BT_PLL_MUX 111 108 #define CLK_DEBUG_MUX 112 109 110 #define CLK_NR_CLKS 113 111 112 /* Peripheral gate clocks */ 113 #define PERIPH_CLK_SYS 0 114 #define PERIPH_CLK_SYS_BUS 1 115 #define PERIPH_CLK_DDR 2 116 #define PERIPH_CLK_ROM 3 117 #define PERIPH_CLK_COUNTER_FAST 4 118 #define PERIPH_CLK_COUNTER_SLOW 5 119 #define PERIPH_CLK_IR 6 120 #define PERIPH_CLK_WD 7 121 #define PERIPH_CLK_PDM 8 122 #define PERIPH_CLK_PWM 9 123 #define PERIPH_CLK_I2C0 10 124 #define PERIPH_CLK_I2C1 11 125 #define PERIPH_CLK_I2C2 12 126 #define PERIPH_CLK_I2C3 13 127 128 /* Peripheral divider clocks */ 129 #define PERIPH_CLK_ROM_DIV 32 130 #define PERIPH_CLK_COUNTER_FAST_DIV 33 131 #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34 132 #define PERIPH_CLK_COUNTER_SLOW_DIV 35 133 #define PERIPH_CLK_IR_PRE_DIV 36 134 #define PERIPH_CLK_IR_DIV 37 135 #define PERIPH_CLK_WD_PRE_DIV 38 136 #define PERIPH_CLK_WD_DIV 39 137 #define PERIPH_CLK_PDM_PRE_DIV 40 138 #define PERIPH_CLK_PDM_DIV 41 139 #define PERIPH_CLK_PWM_PRE_DIV 42 140 #define PERIPH_CLK_PWM_DIV 43 141 #define PERIPH_CLK_I2C0_PRE_DIV 44 142 #define PERIPH_CLK_I2C0_DIV 45 143 #define PERIPH_CLK_I2C1_PRE_DIV 46 144 #define PERIPH_CLK_I2C1_DIV 47 145 #define PERIPH_CLK_I2C2_PRE_DIV 48 146 #define PERIPH_CLK_I2C2_DIV 49 147 #define PERIPH_CLK_I2C3_PRE_DIV 50 148 #define PERIPH_CLK_I2C3_DIV 51 149 150 #define PERIPH_CLK_NR_CLKS 52 151 152 /* System gate clocks */ 153 #define SYS_CLK_I2C0 0 154 #define SYS_CLK_I2C1 1 155 #define SYS_CLK_I2C2 2 156 #define SYS_CLK_I2C3 3 157 #define SYS_CLK_I2S_IN 4 158 #define SYS_CLK_PAUD_OUT 5 159 #define SYS_CLK_SPDIF_OUT 6 160 #define SYS_CLK_SPI0_MASTER 7 161 #define SYS_CLK_SPI0_SLAVE 8 162 #define SYS_CLK_PWM 9 163 #define SYS_CLK_UART0 10 164 #define SYS_CLK_UART1 11 165 #define SYS_CLK_SPI1 12 166 #define SYS_CLK_MDC 13 167 #define SYS_CLK_SD_HOST 14 168 #define SYS_CLK_ENET 15 169 #define SYS_CLK_IR 16 170 #define SYS_CLK_WD 17 171 #define SYS_CLK_TIMER 18 172 #define SYS_CLK_I2S_OUT 24 173 #define SYS_CLK_SPDIF_IN 25 174 #define SYS_CLK_EVENT_TIMER 26 175 #define SYS_CLK_HASH 27 176 177 #define SYS_CLK_NR_CLKS 28 178 179 /* Gates for external input clocks */ 180 #define EXT_CLK_AUDIO_IN 0 181 #define EXT_CLK_ENET_IN 1 182 183 #define EXT_CLK_NR_CLKS 2 184 185 #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */ 186