1 /* $NetBSD: omap5.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright 2017 Texas Instruments, Inc. 6 */ 7 #ifndef __DT_BINDINGS_CLK_OMAP5_H 8 #define __DT_BINDINGS_CLK_OMAP5_H 9 10 #define OMAP5_CLKCTRL_OFFSET 0x20 11 #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) 12 13 /* mpu clocks */ 14 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 15 16 /* dsp clocks */ 17 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 18 19 /* abe clocks */ 20 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 21 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 22 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 23 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) 24 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 25 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) 26 #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 27 #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) 28 #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 29 #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) 30 31 /* l3main1 clocks */ 32 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 33 34 /* l3main2 clocks */ 35 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 36 37 /* ipu clocks */ 38 #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 39 40 /* dma clocks */ 41 #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 42 43 /* emif clocks */ 44 #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 45 #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 46 #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 47 48 /* l4cfg clocks */ 49 #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 50 #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 51 #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 52 53 /* l3instr clocks */ 54 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 55 #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 56 57 /* l4per clocks */ 58 #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 59 #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 60 #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 61 #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) 62 #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) 63 #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 64 #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) 65 #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 66 #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) 67 #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 68 #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) 69 #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) 70 #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) 71 #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) 72 #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) 73 #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) 74 #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) 75 #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) 76 #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) 77 #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) 78 #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) 79 #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) 80 #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) 81 #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) 82 #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) 83 #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) 84 #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) 85 #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) 86 #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) 87 #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) 88 #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) 89 #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) 90 91 /* iva clocks */ 92 #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 93 #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 94 95 /* dss clocks */ 96 #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 97 98 /* gpu clocks */ 99 #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 100 101 /* l3init clocks */ 102 #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) 103 #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 104 #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) 105 #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) 106 #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) 107 #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) 108 #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) 109 #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) 110 111 /* wkupaon clocks */ 112 #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) 113 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) 114 #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) 115 #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) 116 #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) 117 #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) 118 119 #endif 120