1 /* $NetBSD: mt8135-clk.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2014 MediaTek Inc. 5 * Author: James Liao <jamesjj.liao@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _DT_BINDINGS_CLK_MT8135_H 18 #define _DT_BINDINGS_CLK_MT8135_H 19 20 /* TOPCKGEN */ 21 22 #define CLK_TOP_DSI0_LNTC_DSICLK 1 23 #define CLK_TOP_HDMITX_CLKDIG_CTS 2 24 #define CLK_TOP_CLKPH_MCK 3 25 #define CLK_TOP_CPUM_TCK_IN 4 26 #define CLK_TOP_MAINPLL_806M 5 27 #define CLK_TOP_MAINPLL_537P3M 6 28 #define CLK_TOP_MAINPLL_322P4M 7 29 #define CLK_TOP_MAINPLL_230P3M 8 30 #define CLK_TOP_UNIVPLL_624M 9 31 #define CLK_TOP_UNIVPLL_416M 10 32 #define CLK_TOP_UNIVPLL_249P6M 11 33 #define CLK_TOP_UNIVPLL_178P3M 12 34 #define CLK_TOP_UNIVPLL_48M 13 35 #define CLK_TOP_MMPLL_D2 14 36 #define CLK_TOP_MMPLL_D3 15 37 #define CLK_TOP_MMPLL_D5 16 38 #define CLK_TOP_MMPLL_D7 17 39 #define CLK_TOP_MMPLL_D4 18 40 #define CLK_TOP_MMPLL_D6 19 41 #define CLK_TOP_SYSPLL_D2 20 42 #define CLK_TOP_SYSPLL_D4 21 43 #define CLK_TOP_SYSPLL_D6 22 44 #define CLK_TOP_SYSPLL_D8 23 45 #define CLK_TOP_SYSPLL_D10 24 46 #define CLK_TOP_SYSPLL_D12 25 47 #define CLK_TOP_SYSPLL_D16 26 48 #define CLK_TOP_SYSPLL_D24 27 49 #define CLK_TOP_SYSPLL_D3 28 50 #define CLK_TOP_SYSPLL_D2P5 29 51 #define CLK_TOP_SYSPLL_D5 30 52 #define CLK_TOP_SYSPLL_D3P5 31 53 #define CLK_TOP_UNIVPLL1_D2 32 54 #define CLK_TOP_UNIVPLL1_D4 33 55 #define CLK_TOP_UNIVPLL1_D6 34 56 #define CLK_TOP_UNIVPLL1_D8 35 57 #define CLK_TOP_UNIVPLL1_D10 36 58 #define CLK_TOP_UNIVPLL2_D2 37 59 #define CLK_TOP_UNIVPLL2_D4 38 60 #define CLK_TOP_UNIVPLL2_D6 39 61 #define CLK_TOP_UNIVPLL2_D8 40 62 #define CLK_TOP_UNIVPLL_D3 41 63 #define CLK_TOP_UNIVPLL_D5 42 64 #define CLK_TOP_UNIVPLL_D7 43 65 #define CLK_TOP_UNIVPLL_D10 44 66 #define CLK_TOP_UNIVPLL_D26 45 67 #define CLK_TOP_APLL 46 68 #define CLK_TOP_APLL_D4 47 69 #define CLK_TOP_APLL_D8 48 70 #define CLK_TOP_APLL_D16 49 71 #define CLK_TOP_APLL_D24 50 72 #define CLK_TOP_LVDSPLL_D2 51 73 #define CLK_TOP_LVDSPLL_D4 52 74 #define CLK_TOP_LVDSPLL_D8 53 75 #define CLK_TOP_LVDSTX_CLKDIG_CT 54 76 #define CLK_TOP_VPLL_DPIX 55 77 #define CLK_TOP_TVHDMI_H 56 78 #define CLK_TOP_HDMITX_CLKDIG_D2 57 79 #define CLK_TOP_HDMITX_CLKDIG_D3 58 80 #define CLK_TOP_TVHDMI_D2 59 81 #define CLK_TOP_TVHDMI_D4 60 82 #define CLK_TOP_MEMPLL_MCK_D4 61 83 #define CLK_TOP_AXI_SEL 62 84 #define CLK_TOP_SMI_SEL 63 85 #define CLK_TOP_MFG_SEL 64 86 #define CLK_TOP_IRDA_SEL 65 87 #define CLK_TOP_CAM_SEL 66 88 #define CLK_TOP_AUD_INTBUS_SEL 67 89 #define CLK_TOP_JPG_SEL 68 90 #define CLK_TOP_DISP_SEL 69 91 #define CLK_TOP_MSDC30_1_SEL 70 92 #define CLK_TOP_MSDC30_2_SEL 71 93 #define CLK_TOP_MSDC30_3_SEL 72 94 #define CLK_TOP_MSDC30_4_SEL 73 95 #define CLK_TOP_USB20_SEL 74 96 #define CLK_TOP_VENC_SEL 75 97 #define CLK_TOP_SPI_SEL 76 98 #define CLK_TOP_UART_SEL 77 99 #define CLK_TOP_MEM_SEL 78 100 #define CLK_TOP_CAMTG_SEL 79 101 #define CLK_TOP_AUDIO_SEL 80 102 #define CLK_TOP_FIX_SEL 81 103 #define CLK_TOP_VDEC_SEL 82 104 #define CLK_TOP_DDRPHYCFG_SEL 83 105 #define CLK_TOP_DPILVDS_SEL 84 106 #define CLK_TOP_PMICSPI_SEL 85 107 #define CLK_TOP_MSDC30_0_SEL 86 108 #define CLK_TOP_SMI_MFG_AS_SEL 87 109 #define CLK_TOP_GCPU_SEL 88 110 #define CLK_TOP_DPI1_SEL 89 111 #define CLK_TOP_CCI_SEL 90 112 #define CLK_TOP_APLL_SEL 91 113 #define CLK_TOP_HDMIPLL_SEL 92 114 #define CLK_TOP_NR_CLK 93 115 116 /* APMIXED_SYS */ 117 118 #define CLK_APMIXED_ARMPLL1 1 119 #define CLK_APMIXED_ARMPLL2 2 120 #define CLK_APMIXED_MAINPLL 3 121 #define CLK_APMIXED_UNIVPLL 4 122 #define CLK_APMIXED_MMPLL 5 123 #define CLK_APMIXED_MSDCPLL 6 124 #define CLK_APMIXED_TVDPLL 7 125 #define CLK_APMIXED_LVDSPLL 8 126 #define CLK_APMIXED_AUDPLL 9 127 #define CLK_APMIXED_VDECPLL 10 128 #define CLK_APMIXED_NR_CLK 11 129 130 /* INFRA_SYS */ 131 132 #define CLK_INFRA_PMIC_WRAP 1 133 #define CLK_INFRA_PMICSPI 2 134 #define CLK_INFRA_CCIF1_AP_CTRL 3 135 #define CLK_INFRA_CCIF0_AP_CTRL 4 136 #define CLK_INFRA_KP 5 137 #define CLK_INFRA_CPUM 6 138 #define CLK_INFRA_M4U 7 139 #define CLK_INFRA_MFGAXI 8 140 #define CLK_INFRA_DEVAPC 9 141 #define CLK_INFRA_AUDIO 10 142 #define CLK_INFRA_MFG_BUS 11 143 #define CLK_INFRA_SMI 12 144 #define CLK_INFRA_DBGCLK 13 145 #define CLK_INFRA_NR_CLK 14 146 147 /* PERI_SYS */ 148 149 #define CLK_PERI_I2C5 1 150 #define CLK_PERI_I2C4 2 151 #define CLK_PERI_I2C3 3 152 #define CLK_PERI_I2C2 4 153 #define CLK_PERI_I2C1 5 154 #define CLK_PERI_I2C0 6 155 #define CLK_PERI_UART3 7 156 #define CLK_PERI_UART2 8 157 #define CLK_PERI_UART1 9 158 #define CLK_PERI_UART0 10 159 #define CLK_PERI_IRDA 11 160 #define CLK_PERI_NLI 12 161 #define CLK_PERI_MD_HIF 13 162 #define CLK_PERI_AP_HIF 14 163 #define CLK_PERI_MSDC30_3 15 164 #define CLK_PERI_MSDC30_2 16 165 #define CLK_PERI_MSDC30_1 17 166 #define CLK_PERI_MSDC20_2 18 167 #define CLK_PERI_MSDC20_1 19 168 #define CLK_PERI_AP_DMA 20 169 #define CLK_PERI_USB1 21 170 #define CLK_PERI_USB0 22 171 #define CLK_PERI_PWM 23 172 #define CLK_PERI_PWM7 24 173 #define CLK_PERI_PWM6 25 174 #define CLK_PERI_PWM5 26 175 #define CLK_PERI_PWM4 27 176 #define CLK_PERI_PWM3 28 177 #define CLK_PERI_PWM2 29 178 #define CLK_PERI_PWM1 30 179 #define CLK_PERI_THERM 31 180 #define CLK_PERI_NFI 32 181 #define CLK_PERI_USBSLV 33 182 #define CLK_PERI_USB1_MCU 34 183 #define CLK_PERI_USB0_MCU 35 184 #define CLK_PERI_GCPU 36 185 #define CLK_PERI_FHCTL 37 186 #define CLK_PERI_SPI1 38 187 #define CLK_PERI_AUXADC 39 188 #define CLK_PERI_PERI_PWRAP 40 189 #define CLK_PERI_I2C6 41 190 #define CLK_PERI_UART0_SEL 42 191 #define CLK_PERI_UART1_SEL 43 192 #define CLK_PERI_UART2_SEL 44 193 #define CLK_PERI_UART3_SEL 45 194 #define CLK_PERI_NR_CLK 46 195 196 #endif /* _DT_BINDINGS_CLK_MT8135_H */ 197