xref: /netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/mt6797-clk.h (revision 796c32c94f6e154afc9de0f63da35c91bb739b45)
1 /*	$NetBSD: mt6797-clk.h,v 1.1.1.1 2017/07/27 18:10:50 jmcneill Exp $	*/
2 
3 /*
4  * Copyright (c) 2017 MediaTek Inc.
5  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #ifndef _DT_BINDINGS_CLK_MT6797_H
18 #define _DT_BINDINGS_CLK_MT6797_H
19 
20 /* TOPCKGEN */
21 #define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE	1
22 #define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX		2
23 #define	CLK_TOP_MUX_AXI				3
24 #define	CLK_TOP_MUX_MEM				4
25 #define	CLK_TOP_MUX_DDRPHYCFG			5
26 #define	CLK_TOP_MUX_MM				6
27 #define	CLK_TOP_MUX_PWM				7
28 #define	CLK_TOP_MUX_VDEC			8
29 #define	CLK_TOP_MUX_VENC			9
30 #define	CLK_TOP_MUX_MFG				10
31 #define	CLK_TOP_MUX_CAMTG			11
32 #define	CLK_TOP_MUX_UART			12
33 #define	CLK_TOP_MUX_SPI				13
34 #define	CLK_TOP_MUX_ULPOSC_SPI_CK_MUX		14
35 #define	CLK_TOP_MUX_USB20			15
36 #define	CLK_TOP_MUX_MSDC50_0_HCLK		16
37 #define	CLK_TOP_MUX_MSDC50_0			17
38 #define	CLK_TOP_MUX_MSDC30_1			18
39 #define	CLK_TOP_MUX_MSDC30_2			19
40 #define	CLK_TOP_MUX_AUDIO			20
41 #define	CLK_TOP_MUX_AUD_INTBUS			21
42 #define	CLK_TOP_MUX_PMICSPI			22
43 #define	CLK_TOP_MUX_SCP				23
44 #define	CLK_TOP_MUX_ATB				24
45 #define	CLK_TOP_MUX_MJC				25
46 #define	CLK_TOP_MUX_DPI0			26
47 #define	CLK_TOP_MUX_AUD_1			27
48 #define	CLK_TOP_MUX_AUD_2			28
49 #define	CLK_TOP_MUX_SSUSB_TOP_SYS		29
50 #define	CLK_TOP_MUX_SPM				30
51 #define	CLK_TOP_MUX_BSI_SPI			31
52 #define	CLK_TOP_MUX_AUDIO_H			32
53 #define	CLK_TOP_MUX_ANC_MD32			33
54 #define	CLK_TOP_MUX_MFG_52M			34
55 #define	CLK_TOP_SYSPLL_CK			35
56 #define	CLK_TOP_SYSPLL_D2			36
57 #define	CLK_TOP_SYSPLL1_D2			37
58 #define	CLK_TOP_SYSPLL1_D4			38
59 #define	CLK_TOP_SYSPLL1_D8			39
60 #define	CLK_TOP_SYSPLL1_D16			40
61 #define	CLK_TOP_SYSPLL_D3			41
62 #define	CLK_TOP_SYSPLL_D3_D3			42
63 #define	CLK_TOP_SYSPLL2_D2			43
64 #define	CLK_TOP_SYSPLL2_D4			44
65 #define	CLK_TOP_SYSPLL2_D8			45
66 #define	CLK_TOP_SYSPLL_D5			46
67 #define	CLK_TOP_SYSPLL3_D2			47
68 #define	CLK_TOP_SYSPLL3_D4			48
69 #define	CLK_TOP_SYSPLL_D7			49
70 #define	CLK_TOP_SYSPLL4_D2			50
71 #define	CLK_TOP_SYSPLL4_D4			51
72 #define	CLK_TOP_UNIVPLL_CK			52
73 #define	CLK_TOP_UNIVPLL_D7			53
74 #define	CLK_TOP_UNIVPLL_D26			54
75 #define	CLK_TOP_SSUSB_PHY_48M_CK		55
76 #define	CLK_TOP_USB_PHY48M_CK			56
77 #define	CLK_TOP_UNIVPLL_D2			57
78 #define	CLK_TOP_UNIVPLL1_D2			58
79 #define	CLK_TOP_UNIVPLL1_D4			59
80 #define	CLK_TOP_UNIVPLL1_D8			60
81 #define	CLK_TOP_UNIVPLL_D3			61
82 #define	CLK_TOP_UNIVPLL2_D2			62
83 #define	CLK_TOP_UNIVPLL2_D4			63
84 #define	CLK_TOP_UNIVPLL2_D8			64
85 #define	CLK_TOP_UNIVPLL_D5			65
86 #define	CLK_TOP_UNIVPLL3_D2			66
87 #define	CLK_TOP_UNIVPLL3_D4			67
88 #define	CLK_TOP_UNIVPLL3_D8			68
89 #define	CLK_TOP_ULPOSC_CK_ORG			69
90 #define	CLK_TOP_ULPOSC_CK			70
91 #define	CLK_TOP_ULPOSC_D2			71
92 #define	CLK_TOP_ULPOSC_D3			72
93 #define	CLK_TOP_ULPOSC_D4			73
94 #define	CLK_TOP_ULPOSC_D8			74
95 #define	CLK_TOP_ULPOSC_D10			75
96 #define	CLK_TOP_APLL1_CK			76
97 #define	CLK_TOP_APLL2_CK			77
98 #define	CLK_TOP_MFGPLL_CK			78
99 #define	CLK_TOP_MFGPLL_D2			79
100 #define	CLK_TOP_IMGPLL_CK			80
101 #define	CLK_TOP_IMGPLL_D2			81
102 #define	CLK_TOP_IMGPLL_D4			82
103 #define	CLK_TOP_CODECPLL_CK			83
104 #define	CLK_TOP_CODECPLL_D2			84
105 #define	CLK_TOP_VDECPLL_CK			85
106 #define	CLK_TOP_TVDPLL_CK			86
107 #define	CLK_TOP_TVDPLL_D2			87
108 #define	CLK_TOP_TVDPLL_D4			88
109 #define	CLK_TOP_TVDPLL_D8			89
110 #define	CLK_TOP_TVDPLL_D16			90
111 #define	CLK_TOP_MSDCPLL_CK			91
112 #define	CLK_TOP_MSDCPLL_D2			92
113 #define	CLK_TOP_MSDCPLL_D4			93
114 #define	CLK_TOP_MSDCPLL_D8			94
115 #define	CLK_TOP_NR				95
116 
117 /* APMIXED_SYS */
118 #define CLK_APMIXED_MAINPLL			1
119 #define CLK_APMIXED_UNIVPLL			2
120 #define CLK_APMIXED_MFGPLL			3
121 #define CLK_APMIXED_MSDCPLL			4
122 #define CLK_APMIXED_IMGPLL			5
123 #define CLK_APMIXED_TVDPLL			6
124 #define CLK_APMIXED_CODECPLL			7
125 #define CLK_APMIXED_VDECPLL			8
126 #define CLK_APMIXED_APLL1			9
127 #define CLK_APMIXED_APLL2			10
128 #define CLK_APMIXED_NR				11
129 
130 /* INFRA_SYS */
131 #define	CLK_INFRA_PMIC_TMR			1
132 #define	CLK_INFRA_PMIC_AP			2
133 #define	CLK_INFRA_PMIC_MD			3
134 #define	CLK_INFRA_PMIC_CONN			4
135 #define	CLK_INFRA_SCP				5
136 #define	CLK_INFRA_SEJ				6
137 #define	CLK_INFRA_APXGPT			7
138 #define	CLK_INFRA_SEJ_13M			8
139 #define	CLK_INFRA_ICUSB				9
140 #define	CLK_INFRA_GCE				10
141 #define	CLK_INFRA_THERM				11
142 #define	CLK_INFRA_I2C0				12
143 #define	CLK_INFRA_I2C1				13
144 #define	CLK_INFRA_I2C2				14
145 #define	CLK_INFRA_I2C3				15
146 #define	CLK_INFRA_PWM_HCLK			16
147 #define	CLK_INFRA_PWM1				17
148 #define	CLK_INFRA_PWM2				18
149 #define	CLK_INFRA_PWM3				19
150 #define	CLK_INFRA_PWM4				20
151 #define	CLK_INFRA_PWM				21
152 #define	CLK_INFRA_UART0				22
153 #define	CLK_INFRA_UART1				23
154 #define	CLK_INFRA_UART2				24
155 #define	CLK_INFRA_UART3				25
156 #define	CLK_INFRA_MD2MD_CCIF_0			26
157 #define	CLK_INFRA_MD2MD_CCIF_1			27
158 #define	CLK_INFRA_MD2MD_CCIF_2			28
159 #define	CLK_INFRA_FHCTL				29
160 #define	CLK_INFRA_BTIF				30
161 #define	CLK_INFRA_MD2MD_CCIF_3			31
162 #define	CLK_INFRA_SPI				32
163 #define	CLK_INFRA_MSDC0				33
164 #define	CLK_INFRA_MD2MD_CCIF_4			34
165 #define	CLK_INFRA_MSDC1				35
166 #define	CLK_INFRA_MSDC2				36
167 #define	CLK_INFRA_MD2MD_CCIF_5			37
168 #define	CLK_INFRA_GCPU				38
169 #define	CLK_INFRA_TRNG				39
170 #define	CLK_INFRA_AUXADC			40
171 #define	CLK_INFRA_CPUM				41
172 #define	CLK_INFRA_AP_C2K_CCIF_0			42
173 #define	CLK_INFRA_AP_C2K_CCIF_1			43
174 #define	CLK_INFRA_CLDMA				44
175 #define	CLK_INFRA_DISP_PWM			45
176 #define	CLK_INFRA_AP_DMA			46
177 #define	CLK_INFRA_DEVICE_APC			47
178 #define	CLK_INFRA_L2C_SRAM			48
179 #define	CLK_INFRA_CCIF_AP			49
180 #define	CLK_INFRA_AUDIO				50
181 #define	CLK_INFRA_CCIF_MD			51
182 #define	CLK_INFRA_DRAMC_F26M			52
183 #define	CLK_INFRA_I2C4				53
184 #define	CLK_INFRA_I2C_APPM			54
185 #define	CLK_INFRA_I2C_GPUPM			55
186 #define	CLK_INFRA_I2C2_IMM			56
187 #define	CLK_INFRA_I2C2_ARB			57
188 #define	CLK_INFRA_I2C3_IMM			58
189 #define	CLK_INFRA_I2C3_ARB			59
190 #define	CLK_INFRA_I2C5				60
191 #define	CLK_INFRA_SYS_CIRQ			61
192 #define	CLK_INFRA_SPI1				62
193 #define	CLK_INFRA_DRAMC_B_F26M			63
194 #define	CLK_INFRA_ANC_MD32			64
195 #define	CLK_INFRA_ANC_MD32_32K			65
196 #define	CLK_INFRA_DVFS_SPM1			66
197 #define	CLK_INFRA_AES_TOP0			67
198 #define	CLK_INFRA_AES_TOP1			68
199 #define	CLK_INFRA_SSUSB_BUS			69
200 #define	CLK_INFRA_SPI2				70
201 #define	CLK_INFRA_SPI3				71
202 #define	CLK_INFRA_SPI4				72
203 #define	CLK_INFRA_SPI5				73
204 #define	CLK_INFRA_IRTX				74
205 #define	CLK_INFRA_SSUSB_SYS			75
206 #define	CLK_INFRA_SSUSB_REF			76
207 #define	CLK_INFRA_AUDIO_26M			77
208 #define	CLK_INFRA_AUDIO_26M_PAD_TOP		78
209 #define	CLK_INFRA_MODEM_TEMP_SHARE		79
210 #define	CLK_INFRA_VAD_WRAP_SOC			80
211 #define	CLK_INFRA_DRAMC_CONF			81
212 #define	CLK_INFRA_DRAMC_B_CONF			82
213 #define	CLK_INFRA_MFG_VCG			83
214 #define	CLK_INFRA_13M				84
215 #define	CLK_INFRA_NR				85
216 
217 /* IMG_SYS */
218 #define	CLK_IMG_FDVT				1
219 #define	CLK_IMG_DPE				2
220 #define	CLK_IMG_DIP				3
221 #define	CLK_IMG_LARB6				4
222 #define	CLK_IMG_NR				5
223 
224 /* MM_SYS */
225 #define	CLK_MM_SMI_COMMON			1
226 #define	CLK_MM_SMI_LARB0			2
227 #define	CLK_MM_SMI_LARB5			3
228 #define	CLK_MM_CAM_MDP				4
229 #define	CLK_MM_MDP_RDMA0			5
230 #define	CLK_MM_MDP_RDMA1			6
231 #define	CLK_MM_MDP_RSZ0				7
232 #define	CLK_MM_MDP_RSZ1				8
233 #define	CLK_MM_MDP_RSZ2				9
234 #define	CLK_MM_MDP_TDSHP			10
235 #define	CLK_MM_MDP_COLOR			11
236 #define	CLK_MM_MDP_WDMA				12
237 #define	CLK_MM_MDP_WROT0			13
238 #define	CLK_MM_MDP_WROT1			14
239 #define	CLK_MM_FAKE_ENG				15
240 #define	CLK_MM_DISP_OVL0			16
241 #define	CLK_MM_DISP_OVL1			17
242 #define	CLK_MM_DISP_OVL0_2L			18
243 #define	CLK_MM_DISP_OVL1_2L			19
244 #define	CLK_MM_DISP_RDMA0			20
245 #define	CLK_MM_DISP_RDMA1			21
246 #define	CLK_MM_DISP_WDMA0			22
247 #define	CLK_MM_DISP_WDMA1			23
248 #define	CLK_MM_DISP_COLOR			24
249 #define	CLK_MM_DISP_CCORR			25
250 #define	CLK_MM_DISP_AAL				26
251 #define	CLK_MM_DISP_GAMMA			27
252 #define	CLK_MM_DISP_OD				28
253 #define	CLK_MM_DISP_DITHER			29
254 #define	CLK_MM_DISP_UFOE			30
255 #define	CLK_MM_DISP_DSC				31
256 #define	CLK_MM_DISP_SPLIT			32
257 #define	CLK_MM_DSI0_MM_CLOCK			33
258 #define	CLK_MM_DSI1_MM_CLOCK			34
259 #define	CLK_MM_DPI_MM_CLOCK			35
260 #define	CLK_MM_DPI_INTERFACE_CLOCK		36
261 #define	CLK_MM_LARB4_AXI_ASIF_MM_CLOCK		37
262 #define	CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK		38
263 #define	CLK_MM_DISP_OVL0_MOUT_CLOCK		39
264 #define	CLK_MM_FAKE_ENG2			40
265 #define	CLK_MM_DSI0_INTERFACE_CLOCK		41
266 #define	CLK_MM_DSI1_INTERFACE_CLOCK		42
267 #define	CLK_MM_NR				43
268 
269 /* VDEC_SYS */
270 #define	CLK_VDEC_CKEN_ENG			1
271 #define	CLK_VDEC_ACTIVE				2
272 #define	CLK_VDEC_CKEN				3
273 #define	CLK_VDEC_LARB1_CKEN			4
274 #define	CLK_VDEC_NR				5
275 
276 /* VENC_SYS */
277 #define	CLK_VENC_0				1
278 #define	CLK_VENC_1				2
279 #define	CLK_VENC_2				3
280 #define	CLK_VENC_3				4
281 #define	CLK_VENC_NR				5
282 
283 #endif /* _DT_BINDINGS_CLK_MT6797_H */
284