1 /* $NetBSD: marvell,mmp2.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 #ifndef __DTS_MARVELL_MMP2_CLOCK_H 4 #define __DTS_MARVELL_MMP2_CLOCK_H 5 6 /* fixed clocks and plls */ 7 #define MMP2_CLK_CLK32 1 8 #define MMP2_CLK_VCTCXO 2 9 #define MMP2_CLK_PLL1 3 10 #define MMP2_CLK_PLL1_2 8 11 #define MMP2_CLK_PLL1_4 9 12 #define MMP2_CLK_PLL1_8 10 13 #define MMP2_CLK_PLL1_16 11 14 #define MMP2_CLK_PLL1_3 12 15 #define MMP2_CLK_PLL1_6 13 16 #define MMP2_CLK_PLL1_12 14 17 #define MMP2_CLK_PLL1_20 15 18 #define MMP2_CLK_PLL2 16 19 #define MMP2_CLK_PLL2_2 17 20 #define MMP2_CLK_PLL2_4 18 21 #define MMP2_CLK_PLL2_8 19 22 #define MMP2_CLK_PLL2_16 20 23 #define MMP2_CLK_PLL2_3 21 24 #define MMP2_CLK_PLL2_6 22 25 #define MMP2_CLK_PLL2_12 23 26 #define MMP2_CLK_VCTCXO_2 24 27 #define MMP2_CLK_VCTCXO_4 25 28 #define MMP2_CLK_UART_PLL 26 29 #define MMP2_CLK_USB_PLL 27 30 31 /* apb periphrals */ 32 #define MMP2_CLK_TWSI0 60 33 #define MMP2_CLK_TWSI1 61 34 #define MMP2_CLK_TWSI2 62 35 #define MMP2_CLK_TWSI3 63 36 #define MMP2_CLK_TWSI4 64 37 #define MMP2_CLK_TWSI5 65 38 #define MMP2_CLK_GPIO 66 39 #define MMP2_CLK_KPC 67 40 #define MMP2_CLK_RTC 68 41 #define MMP2_CLK_PWM0 69 42 #define MMP2_CLK_PWM1 70 43 #define MMP2_CLK_PWM2 71 44 #define MMP2_CLK_PWM3 72 45 #define MMP2_CLK_UART0 73 46 #define MMP2_CLK_UART1 74 47 #define MMP2_CLK_UART2 75 48 #define MMP2_CLK_UART3 76 49 #define MMP2_CLK_SSP0 77 50 #define MMP2_CLK_SSP1 78 51 #define MMP2_CLK_SSP2 79 52 #define MMP2_CLK_SSP3 80 53 #define MMP2_CLK_TIMER 81 54 55 /* axi periphrals */ 56 #define MMP2_CLK_SDH0 101 57 #define MMP2_CLK_SDH1 102 58 #define MMP2_CLK_SDH2 103 59 #define MMP2_CLK_SDH3 104 60 #define MMP2_CLK_USB 105 61 #define MMP2_CLK_DISP0 106 62 #define MMP2_CLK_DISP0_MUX 107 63 #define MMP2_CLK_DISP0_SPHY 108 64 #define MMP2_CLK_DISP1 109 65 #define MMP2_CLK_DISP1_MUX 110 66 #define MMP2_CLK_CCIC_ARBITER 111 67 #define MMP2_CLK_CCIC0 112 68 #define MMP2_CLK_CCIC0_MIX 113 69 #define MMP2_CLK_CCIC0_PHY 114 70 #define MMP2_CLK_CCIC0_SPHY 115 71 #define MMP2_CLK_CCIC1 116 72 #define MMP2_CLK_CCIC1_MIX 117 73 #define MMP2_CLK_CCIC1_PHY 118 74 #define MMP2_CLK_CCIC1_SPHY 119 75 76 #define MMP2_NR_CLKS 200 77 #endif 78