1 /* $NetBSD: imx7d-clock.h,v 1.1.1.5 2018/06/27 16:27:08 jmcneill Exp $ */ 2 3 /* 4 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #ifndef __DT_BINDINGS_CLOCK_IMX7D_H 13 #define __DT_BINDINGS_CLOCK_IMX7D_H 14 15 #define IMX7D_OSC_24M_CLK 0 16 #define IMX7D_PLL_ARM_MAIN 1 17 #define IMX7D_PLL_ARM_MAIN_CLK 2 18 #define IMX7D_PLL_ARM_MAIN_SRC 3 19 #define IMX7D_PLL_ARM_MAIN_BYPASS 4 20 #define IMX7D_PLL_SYS_MAIN 5 21 #define IMX7D_PLL_SYS_MAIN_CLK 6 22 #define IMX7D_PLL_SYS_MAIN_SRC 7 23 #define IMX7D_PLL_SYS_MAIN_BYPASS 8 24 #define IMX7D_PLL_SYS_MAIN_480M 9 25 #define IMX7D_PLL_SYS_MAIN_240M 10 26 #define IMX7D_PLL_SYS_MAIN_120M 11 27 #define IMX7D_PLL_SYS_MAIN_480M_CLK 12 28 #define IMX7D_PLL_SYS_MAIN_240M_CLK 13 29 #define IMX7D_PLL_SYS_MAIN_120M_CLK 14 30 #define IMX7D_PLL_SYS_PFD0_392M_CLK 15 31 #define IMX7D_PLL_SYS_PFD0_196M 16 32 #define IMX7D_PLL_SYS_PFD0_196M_CLK 17 33 #define IMX7D_PLL_SYS_PFD1_332M_CLK 18 34 #define IMX7D_PLL_SYS_PFD1_166M 19 35 #define IMX7D_PLL_SYS_PFD1_166M_CLK 20 36 #define IMX7D_PLL_SYS_PFD2_270M_CLK 21 37 #define IMX7D_PLL_SYS_PFD2_135M 22 38 #define IMX7D_PLL_SYS_PFD2_135M_CLK 23 39 #define IMX7D_PLL_SYS_PFD3_CLK 24 40 #define IMX7D_PLL_SYS_PFD4_CLK 25 41 #define IMX7D_PLL_SYS_PFD5_CLK 26 42 #define IMX7D_PLL_SYS_PFD6_CLK 27 43 #define IMX7D_PLL_SYS_PFD7_CLK 28 44 #define IMX7D_PLL_ENET_MAIN 29 45 #define IMX7D_PLL_ENET_MAIN_CLK 30 46 #define IMX7D_PLL_ENET_MAIN_SRC 31 47 #define IMX7D_PLL_ENET_MAIN_BYPASS 32 48 #define IMX7D_PLL_ENET_MAIN_500M 33 49 #define IMX7D_PLL_ENET_MAIN_250M 34 50 #define IMX7D_PLL_ENET_MAIN_125M 35 51 #define IMX7D_PLL_ENET_MAIN_100M 36 52 #define IMX7D_PLL_ENET_MAIN_50M 37 53 #define IMX7D_PLL_ENET_MAIN_40M 38 54 #define IMX7D_PLL_ENET_MAIN_25M 39 55 #define IMX7D_PLL_ENET_MAIN_500M_CLK 40 56 #define IMX7D_PLL_ENET_MAIN_250M_CLK 41 57 #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 58 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 59 #define IMX7D_PLL_ENET_MAIN_50M_CLK 44 60 #define IMX7D_PLL_ENET_MAIN_40M_CLK 45 61 #define IMX7D_PLL_ENET_MAIN_25M_CLK 46 62 #define IMX7D_PLL_DRAM_MAIN 47 63 #define IMX7D_PLL_DRAM_MAIN_CLK 48 64 #define IMX7D_PLL_DRAM_MAIN_SRC 49 65 #define IMX7D_PLL_DRAM_MAIN_BYPASS 50 66 #define IMX7D_PLL_DRAM_MAIN_533M 51 67 #define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 68 #define IMX7D_PLL_AUDIO_MAIN 53 69 #define IMX7D_PLL_AUDIO_MAIN_CLK 54 70 #define IMX7D_PLL_AUDIO_MAIN_SRC 55 71 #define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 72 #define IMX7D_PLL_VIDEO_MAIN_CLK 57 73 #define IMX7D_PLL_VIDEO_MAIN 58 74 #define IMX7D_PLL_VIDEO_MAIN_SRC 59 75 #define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 76 #define IMX7D_USB_MAIN_480M_CLK 61 77 #define IMX7D_ARM_A7_ROOT_CLK 62 78 #define IMX7D_ARM_A7_ROOT_SRC 63 79 #define IMX7D_ARM_A7_ROOT_CG 64 80 #define IMX7D_ARM_A7_ROOT_DIV 65 81 #define IMX7D_ARM_M4_ROOT_CLK 66 82 #define IMX7D_ARM_M4_ROOT_SRC 67 83 #define IMX7D_ARM_M4_ROOT_CG 68 84 #define IMX7D_ARM_M4_ROOT_DIV 69 85 #define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ 86 #define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ 87 #define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ 88 #define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ 89 #define IMX7D_MAIN_AXI_ROOT_CLK 74 90 #define IMX7D_MAIN_AXI_ROOT_SRC 75 91 #define IMX7D_MAIN_AXI_ROOT_CG 76 92 #define IMX7D_MAIN_AXI_ROOT_DIV 77 93 #define IMX7D_DISP_AXI_ROOT_CLK 78 94 #define IMX7D_DISP_AXI_ROOT_SRC 79 95 #define IMX7D_DISP_AXI_ROOT_CG 80 96 #define IMX7D_DISP_AXI_ROOT_DIV 81 97 #define IMX7D_ENET_AXI_ROOT_CLK 82 98 #define IMX7D_ENET_AXI_ROOT_SRC 83 99 #define IMX7D_ENET_AXI_ROOT_CG 84 100 #define IMX7D_ENET_AXI_ROOT_DIV 85 101 #define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 102 #define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 103 #define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 104 #define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 105 #define IMX7D_AHB_CHANNEL_ROOT_CLK 90 106 #define IMX7D_AHB_CHANNEL_ROOT_SRC 91 107 #define IMX7D_AHB_CHANNEL_ROOT_CG 92 108 #define IMX7D_AHB_CHANNEL_ROOT_DIV 93 109 #define IMX7D_DRAM_PHYM_ROOT_CLK 94 110 #define IMX7D_DRAM_PHYM_ROOT_SRC 95 111 #define IMX7D_DRAM_PHYM_ROOT_CG 96 112 #define IMX7D_DRAM_PHYM_ROOT_DIV 97 113 #define IMX7D_DRAM_ROOT_CLK 98 114 #define IMX7D_DRAM_ROOT_SRC 99 115 #define IMX7D_DRAM_ROOT_CG 100 116 #define IMX7D_DRAM_ROOT_DIV 101 117 #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 118 #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 119 #define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 120 #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 121 #define IMX7D_DRAM_ALT_ROOT_CLK 106 122 #define IMX7D_DRAM_ALT_ROOT_SRC 107 123 #define IMX7D_DRAM_ALT_ROOT_CG 108 124 #define IMX7D_DRAM_ALT_ROOT_DIV 109 125 #define IMX7D_USB_HSIC_ROOT_CLK 110 126 #define IMX7D_USB_HSIC_ROOT_SRC 111 127 #define IMX7D_USB_HSIC_ROOT_CG 112 128 #define IMX7D_USB_HSIC_ROOT_DIV 113 129 #define IMX7D_PCIE_CTRL_ROOT_CLK 114 130 #define IMX7D_PCIE_CTRL_ROOT_SRC 115 131 #define IMX7D_PCIE_CTRL_ROOT_CG 116 132 #define IMX7D_PCIE_CTRL_ROOT_DIV 117 133 #define IMX7D_PCIE_PHY_ROOT_CLK 118 134 #define IMX7D_PCIE_PHY_ROOT_SRC 119 135 #define IMX7D_PCIE_PHY_ROOT_CG 120 136 #define IMX7D_PCIE_PHY_ROOT_DIV 121 137 #define IMX7D_EPDC_PIXEL_ROOT_CLK 122 138 #define IMX7D_EPDC_PIXEL_ROOT_SRC 123 139 #define IMX7D_EPDC_PIXEL_ROOT_CG 124 140 #define IMX7D_EPDC_PIXEL_ROOT_DIV 125 141 #define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 142 #define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 143 #define IMX7D_LCDIF_PIXEL_ROOT_CG 128 144 #define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 145 #define IMX7D_MIPI_DSI_ROOT_CLK 130 146 #define IMX7D_MIPI_DSI_ROOT_SRC 131 147 #define IMX7D_MIPI_DSI_ROOT_CG 132 148 #define IMX7D_MIPI_DSI_ROOT_DIV 133 149 #define IMX7D_MIPI_CSI_ROOT_CLK 134 150 #define IMX7D_MIPI_CSI_ROOT_SRC 135 151 #define IMX7D_MIPI_CSI_ROOT_CG 136 152 #define IMX7D_MIPI_CSI_ROOT_DIV 137 153 #define IMX7D_MIPI_DPHY_ROOT_CLK 138 154 #define IMX7D_MIPI_DPHY_ROOT_SRC 139 155 #define IMX7D_MIPI_DPHY_ROOT_CG 140 156 #define IMX7D_MIPI_DPHY_ROOT_DIV 141 157 #define IMX7D_SAI1_ROOT_CLK 142 158 #define IMX7D_SAI1_ROOT_SRC 143 159 #define IMX7D_SAI1_ROOT_CG 144 160 #define IMX7D_SAI1_ROOT_DIV 145 161 #define IMX7D_SAI2_ROOT_CLK 146 162 #define IMX7D_SAI2_ROOT_SRC 147 163 #define IMX7D_SAI2_ROOT_CG 148 164 #define IMX7D_SAI2_ROOT_DIV 149 165 #define IMX7D_SAI3_ROOT_CLK 150 166 #define IMX7D_SAI3_ROOT_SRC 151 167 #define IMX7D_SAI3_ROOT_CG 152 168 #define IMX7D_SAI3_ROOT_DIV 153 169 #define IMX7D_SPDIF_ROOT_CLK 154 170 #define IMX7D_SPDIF_ROOT_SRC 155 171 #define IMX7D_SPDIF_ROOT_CG 156 172 #define IMX7D_SPDIF_ROOT_DIV 157 173 #define IMX7D_ENET1_IPG_ROOT_CLK 158 174 #define IMX7D_ENET1_REF_ROOT_SRC 159 175 #define IMX7D_ENET1_REF_ROOT_CG 160 176 #define IMX7D_ENET1_REF_ROOT_DIV 161 177 #define IMX7D_ENET1_TIME_ROOT_CLK 162 178 #define IMX7D_ENET1_TIME_ROOT_SRC 163 179 #define IMX7D_ENET1_TIME_ROOT_CG 164 180 #define IMX7D_ENET1_TIME_ROOT_DIV 165 181 #define IMX7D_ENET2_IPG_ROOT_CLK 166 182 #define IMX7D_ENET2_REF_ROOT_SRC 167 183 #define IMX7D_ENET2_REF_ROOT_CG 168 184 #define IMX7D_ENET2_REF_ROOT_DIV 169 185 #define IMX7D_ENET2_TIME_ROOT_CLK 170 186 #define IMX7D_ENET2_TIME_ROOT_SRC 171 187 #define IMX7D_ENET2_TIME_ROOT_CG 172 188 #define IMX7D_ENET2_TIME_ROOT_DIV 173 189 #define IMX7D_ENET_PHY_REF_ROOT_CLK 174 190 #define IMX7D_ENET_PHY_REF_ROOT_SRC 175 191 #define IMX7D_ENET_PHY_REF_ROOT_CG 176 192 #define IMX7D_ENET_PHY_REF_ROOT_DIV 177 193 #define IMX7D_EIM_ROOT_CLK 178 194 #define IMX7D_EIM_ROOT_SRC 179 195 #define IMX7D_EIM_ROOT_CG 180 196 #define IMX7D_EIM_ROOT_DIV 181 197 #define IMX7D_NAND_ROOT_CLK 182 198 #define IMX7D_NAND_ROOT_SRC 183 199 #define IMX7D_NAND_ROOT_CG 184 200 #define IMX7D_NAND_ROOT_DIV 185 201 #define IMX7D_QSPI_ROOT_CLK 186 202 #define IMX7D_QSPI_ROOT_SRC 187 203 #define IMX7D_QSPI_ROOT_CG 188 204 #define IMX7D_QSPI_ROOT_DIV 189 205 #define IMX7D_USDHC1_ROOT_CLK 190 206 #define IMX7D_USDHC1_ROOT_SRC 191 207 #define IMX7D_USDHC1_ROOT_CG 192 208 #define IMX7D_USDHC1_ROOT_DIV 193 209 #define IMX7D_USDHC2_ROOT_CLK 194 210 #define IMX7D_USDHC2_ROOT_SRC 195 211 #define IMX7D_USDHC2_ROOT_CG 196 212 #define IMX7D_USDHC2_ROOT_DIV 197 213 #define IMX7D_USDHC3_ROOT_CLK 198 214 #define IMX7D_USDHC3_ROOT_SRC 199 215 #define IMX7D_USDHC3_ROOT_CG 200 216 #define IMX7D_USDHC3_ROOT_DIV 201 217 #define IMX7D_CAN1_ROOT_CLK 202 218 #define IMX7D_CAN1_ROOT_SRC 203 219 #define IMX7D_CAN1_ROOT_CG 204 220 #define IMX7D_CAN1_ROOT_DIV 205 221 #define IMX7D_CAN2_ROOT_CLK 206 222 #define IMX7D_CAN2_ROOT_SRC 207 223 #define IMX7D_CAN2_ROOT_CG 208 224 #define IMX7D_CAN2_ROOT_DIV 209 225 #define IMX7D_I2C1_ROOT_CLK 210 226 #define IMX7D_I2C1_ROOT_SRC 211 227 #define IMX7D_I2C1_ROOT_CG 212 228 #define IMX7D_I2C1_ROOT_DIV 213 229 #define IMX7D_I2C2_ROOT_CLK 214 230 #define IMX7D_I2C2_ROOT_SRC 215 231 #define IMX7D_I2C2_ROOT_CG 216 232 #define IMX7D_I2C2_ROOT_DIV 217 233 #define IMX7D_I2C3_ROOT_CLK 218 234 #define IMX7D_I2C3_ROOT_SRC 219 235 #define IMX7D_I2C3_ROOT_CG 220 236 #define IMX7D_I2C3_ROOT_DIV 221 237 #define IMX7D_I2C4_ROOT_CLK 222 238 #define IMX7D_I2C4_ROOT_SRC 223 239 #define IMX7D_I2C4_ROOT_CG 224 240 #define IMX7D_I2C4_ROOT_DIV 225 241 #define IMX7D_UART1_ROOT_CLK 226 242 #define IMX7D_UART1_ROOT_SRC 227 243 #define IMX7D_UART1_ROOT_CG 228 244 #define IMX7D_UART1_ROOT_DIV 229 245 #define IMX7D_UART2_ROOT_CLK 230 246 #define IMX7D_UART2_ROOT_SRC 231 247 #define IMX7D_UART2_ROOT_CG 232 248 #define IMX7D_UART2_ROOT_DIV 233 249 #define IMX7D_UART3_ROOT_CLK 234 250 #define IMX7D_UART3_ROOT_SRC 235 251 #define IMX7D_UART3_ROOT_CG 236 252 #define IMX7D_UART3_ROOT_DIV 237 253 #define IMX7D_UART4_ROOT_CLK 238 254 #define IMX7D_UART4_ROOT_SRC 239 255 #define IMX7D_UART4_ROOT_CG 240 256 #define IMX7D_UART4_ROOT_DIV 241 257 #define IMX7D_UART5_ROOT_CLK 242 258 #define IMX7D_UART5_ROOT_SRC 243 259 #define IMX7D_UART5_ROOT_CG 244 260 #define IMX7D_UART5_ROOT_DIV 245 261 #define IMX7D_UART6_ROOT_CLK 246 262 #define IMX7D_UART6_ROOT_SRC 247 263 #define IMX7D_UART6_ROOT_CG 248 264 #define IMX7D_UART6_ROOT_DIV 249 265 #define IMX7D_UART7_ROOT_CLK 250 266 #define IMX7D_UART7_ROOT_SRC 251 267 #define IMX7D_UART7_ROOT_CG 252 268 #define IMX7D_UART7_ROOT_DIV 253 269 #define IMX7D_ECSPI1_ROOT_CLK 254 270 #define IMX7D_ECSPI1_ROOT_SRC 255 271 #define IMX7D_ECSPI1_ROOT_CG 256 272 #define IMX7D_ECSPI1_ROOT_DIV 257 273 #define IMX7D_ECSPI2_ROOT_CLK 258 274 #define IMX7D_ECSPI2_ROOT_SRC 259 275 #define IMX7D_ECSPI2_ROOT_CG 260 276 #define IMX7D_ECSPI2_ROOT_DIV 261 277 #define IMX7D_ECSPI3_ROOT_CLK 262 278 #define IMX7D_ECSPI3_ROOT_SRC 263 279 #define IMX7D_ECSPI3_ROOT_CG 264 280 #define IMX7D_ECSPI3_ROOT_DIV 265 281 #define IMX7D_ECSPI4_ROOT_CLK 266 282 #define IMX7D_ECSPI4_ROOT_SRC 267 283 #define IMX7D_ECSPI4_ROOT_CG 268 284 #define IMX7D_ECSPI4_ROOT_DIV 269 285 #define IMX7D_PWM1_ROOT_CLK 270 286 #define IMX7D_PWM1_ROOT_SRC 271 287 #define IMX7D_PWM1_ROOT_CG 272 288 #define IMX7D_PWM1_ROOT_DIV 273 289 #define IMX7D_PWM2_ROOT_CLK 274 290 #define IMX7D_PWM2_ROOT_SRC 275 291 #define IMX7D_PWM2_ROOT_CG 276 292 #define IMX7D_PWM2_ROOT_DIV 277 293 #define IMX7D_PWM3_ROOT_CLK 278 294 #define IMX7D_PWM3_ROOT_SRC 279 295 #define IMX7D_PWM3_ROOT_CG 280 296 #define IMX7D_PWM3_ROOT_DIV 281 297 #define IMX7D_PWM4_ROOT_CLK 282 298 #define IMX7D_PWM4_ROOT_SRC 283 299 #define IMX7D_PWM4_ROOT_CG 284 300 #define IMX7D_PWM4_ROOT_DIV 285 301 #define IMX7D_FLEXTIMER1_ROOT_CLK 286 302 #define IMX7D_FLEXTIMER1_ROOT_SRC 287 303 #define IMX7D_FLEXTIMER1_ROOT_CG 288 304 #define IMX7D_FLEXTIMER1_ROOT_DIV 289 305 #define IMX7D_FLEXTIMER2_ROOT_CLK 290 306 #define IMX7D_FLEXTIMER2_ROOT_SRC 291 307 #define IMX7D_FLEXTIMER2_ROOT_CG 292 308 #define IMX7D_FLEXTIMER2_ROOT_DIV 293 309 #define IMX7D_SIM1_ROOT_CLK 294 310 #define IMX7D_SIM1_ROOT_SRC 295 311 #define IMX7D_SIM1_ROOT_CG 296 312 #define IMX7D_SIM1_ROOT_DIV 297 313 #define IMX7D_SIM2_ROOT_CLK 298 314 #define IMX7D_SIM2_ROOT_SRC 299 315 #define IMX7D_SIM2_ROOT_CG 300 316 #define IMX7D_SIM2_ROOT_DIV 301 317 #define IMX7D_GPT1_ROOT_CLK 302 318 #define IMX7D_GPT1_ROOT_SRC 303 319 #define IMX7D_GPT1_ROOT_CG 304 320 #define IMX7D_GPT1_ROOT_DIV 305 321 #define IMX7D_GPT2_ROOT_CLK 306 322 #define IMX7D_GPT2_ROOT_SRC 307 323 #define IMX7D_GPT2_ROOT_CG 308 324 #define IMX7D_GPT2_ROOT_DIV 309 325 #define IMX7D_GPT3_ROOT_CLK 310 326 #define IMX7D_GPT3_ROOT_SRC 311 327 #define IMX7D_GPT3_ROOT_CG 312 328 #define IMX7D_GPT3_ROOT_DIV 313 329 #define IMX7D_GPT4_ROOT_CLK 314 330 #define IMX7D_GPT4_ROOT_SRC 315 331 #define IMX7D_GPT4_ROOT_CG 316 332 #define IMX7D_GPT4_ROOT_DIV 317 333 #define IMX7D_TRACE_ROOT_CLK 318 334 #define IMX7D_TRACE_ROOT_SRC 319 335 #define IMX7D_TRACE_ROOT_CG 320 336 #define IMX7D_TRACE_ROOT_DIV 321 337 #define IMX7D_WDOG1_ROOT_CLK 322 338 #define IMX7D_WDOG_ROOT_SRC 323 339 #define IMX7D_WDOG_ROOT_CG 324 340 #define IMX7D_WDOG_ROOT_DIV 325 341 #define IMX7D_CSI_MCLK_ROOT_CLK 326 342 #define IMX7D_CSI_MCLK_ROOT_SRC 327 343 #define IMX7D_CSI_MCLK_ROOT_CG 328 344 #define IMX7D_CSI_MCLK_ROOT_DIV 329 345 #define IMX7D_AUDIO_MCLK_ROOT_CLK 330 346 #define IMX7D_AUDIO_MCLK_ROOT_SRC 331 347 #define IMX7D_AUDIO_MCLK_ROOT_CG 332 348 #define IMX7D_AUDIO_MCLK_ROOT_DIV 333 349 #define IMX7D_WRCLK_ROOT_CLK 334 350 #define IMX7D_WRCLK_ROOT_SRC 335 351 #define IMX7D_WRCLK_ROOT_CG 336 352 #define IMX7D_WRCLK_ROOT_DIV 337 353 #define IMX7D_CLKO1_ROOT_SRC 338 354 #define IMX7D_CLKO1_ROOT_CG 339 355 #define IMX7D_CLKO1_ROOT_DIV 340 356 #define IMX7D_CLKO2_ROOT_SRC 341 357 #define IMX7D_CLKO2_ROOT_CG 342 358 #define IMX7D_CLKO2_ROOT_DIV 343 359 #define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 360 #define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 361 #define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 362 #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 363 #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 364 #define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 365 #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 366 #define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 367 #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 368 #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 369 #define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 370 #define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 371 #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 372 #define IMX7D_SAI1_ROOT_PRE_DIV 357 373 #define IMX7D_SAI2_ROOT_PRE_DIV 358 374 #define IMX7D_SAI3_ROOT_PRE_DIV 359 375 #define IMX7D_SPDIF_ROOT_PRE_DIV 360 376 #define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 377 #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 378 #define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 379 #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 380 #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 381 #define IMX7D_EIM_ROOT_PRE_DIV 366 382 #define IMX7D_NAND_ROOT_PRE_DIV 367 383 #define IMX7D_QSPI_ROOT_PRE_DIV 368 384 #define IMX7D_USDHC1_ROOT_PRE_DIV 369 385 #define IMX7D_USDHC2_ROOT_PRE_DIV 370 386 #define IMX7D_USDHC3_ROOT_PRE_DIV 371 387 #define IMX7D_CAN1_ROOT_PRE_DIV 372 388 #define IMX7D_CAN2_ROOT_PRE_DIV 373 389 #define IMX7D_I2C1_ROOT_PRE_DIV 374 390 #define IMX7D_I2C2_ROOT_PRE_DIV 375 391 #define IMX7D_I2C3_ROOT_PRE_DIV 376 392 #define IMX7D_I2C4_ROOT_PRE_DIV 377 393 #define IMX7D_UART1_ROOT_PRE_DIV 378 394 #define IMX7D_UART2_ROOT_PRE_DIV 379 395 #define IMX7D_UART3_ROOT_PRE_DIV 380 396 #define IMX7D_UART4_ROOT_PRE_DIV 381 397 #define IMX7D_UART5_ROOT_PRE_DIV 382 398 #define IMX7D_UART6_ROOT_PRE_DIV 383 399 #define IMX7D_UART7_ROOT_PRE_DIV 384 400 #define IMX7D_ECSPI1_ROOT_PRE_DIV 385 401 #define IMX7D_ECSPI2_ROOT_PRE_DIV 386 402 #define IMX7D_ECSPI3_ROOT_PRE_DIV 387 403 #define IMX7D_ECSPI4_ROOT_PRE_DIV 388 404 #define IMX7D_PWM1_ROOT_PRE_DIV 389 405 #define IMX7D_PWM2_ROOT_PRE_DIV 390 406 #define IMX7D_PWM3_ROOT_PRE_DIV 391 407 #define IMX7D_PWM4_ROOT_PRE_DIV 392 408 #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 409 #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 410 #define IMX7D_SIM1_ROOT_PRE_DIV 395 411 #define IMX7D_SIM2_ROOT_PRE_DIV 396 412 #define IMX7D_GPT1_ROOT_PRE_DIV 397 413 #define IMX7D_GPT2_ROOT_PRE_DIV 398 414 #define IMX7D_GPT3_ROOT_PRE_DIV 399 415 #define IMX7D_GPT4_ROOT_PRE_DIV 400 416 #define IMX7D_TRACE_ROOT_PRE_DIV 401 417 #define IMX7D_WDOG_ROOT_PRE_DIV 402 418 #define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 419 #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 420 #define IMX7D_WRCLK_ROOT_PRE_DIV 405 421 #define IMX7D_CLKO1_ROOT_PRE_DIV 406 422 #define IMX7D_CLKO2_ROOT_PRE_DIV 407 423 #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 424 #define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 425 #define IMX7D_LVDS1_IN_CLK 410 426 #define IMX7D_LVDS1_OUT_SEL 411 427 #define IMX7D_LVDS1_OUT_CLK 412 428 #define IMX7D_CLK_DUMMY 413 429 #define IMX7D_GPT_3M_CLK 414 430 #define IMX7D_OCRAM_CLK 415 431 #define IMX7D_OCRAM_S_CLK 416 432 #define IMX7D_WDOG2_ROOT_CLK 417 433 #define IMX7D_WDOG3_ROOT_CLK 418 434 #define IMX7D_WDOG4_ROOT_CLK 419 435 #define IMX7D_SDMA_CORE_CLK 420 436 #define IMX7D_USB1_MAIN_480M_CLK 421 437 #define IMX7D_USB_CTRL_CLK 422 438 #define IMX7D_USB_PHY1_CLK 423 439 #define IMX7D_USB_PHY2_CLK 424 440 #define IMX7D_IPG_ROOT_CLK 425 441 #define IMX7D_SAI1_IPG_CLK 426 442 #define IMX7D_SAI2_IPG_CLK 427 443 #define IMX7D_SAI3_IPG_CLK 428 444 #define IMX7D_PLL_AUDIO_TEST_DIV 429 445 #define IMX7D_PLL_AUDIO_POST_DIV 430 446 #define IMX7D_PLL_VIDEO_TEST_DIV 431 447 #define IMX7D_PLL_VIDEO_POST_DIV 432 448 #define IMX7D_MU_ROOT_CLK 433 449 #define IMX7D_SEMA4_HS_ROOT_CLK 434 450 #define IMX7D_PLL_DRAM_TEST_DIV 435 451 #define IMX7D_ADC_ROOT_CLK 436 452 #define IMX7D_CLK_ARM 437 453 #define IMX7D_CKIL 438 454 #define IMX7D_OCOTP_CLK 439 455 #define IMX7D_NAND_RAWNAND_CLK 440 456 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 457 #define IMX7D_SNVS_CLK 442 458 #define IMX7D_CAAM_CLK 443 459 #define IMX7D_KPP_ROOT_CLK 444 460 #define IMX7D_CLK_END 445 461 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 462