1 /* $NetBSD: exynos7-clk.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H 13 #define _DT_BINDINGS_CLOCK_EXYNOS7_H 14 15 /* TOPC */ 16 #define DOUT_ACLK_PERIS 1 17 #define DOUT_SCLK_BUS0_PLL 2 18 #define DOUT_SCLK_BUS1_PLL 3 19 #define DOUT_SCLK_CC_PLL 4 20 #define DOUT_SCLK_MFC_PLL 5 21 #define DOUT_ACLK_CCORE_133 6 22 #define DOUT_ACLK_MSCL_532 7 23 #define ACLK_MSCL_532 8 24 #define DOUT_SCLK_AUD_PLL 9 25 #define FOUT_AUD_PLL 10 26 #define SCLK_AUD_PLL 11 27 #define SCLK_MFC_PLL_B 12 28 #define SCLK_MFC_PLL_A 13 29 #define SCLK_BUS1_PLL_B 14 30 #define SCLK_BUS1_PLL_A 15 31 #define SCLK_BUS0_PLL_B 16 32 #define SCLK_BUS0_PLL_A 17 33 #define SCLK_CC_PLL_B 18 34 #define SCLK_CC_PLL_A 19 35 #define ACLK_CCORE_133 20 36 #define ACLK_PERIS_66 21 37 #define TOPC_NR_CLK 22 38 39 /* TOP0 */ 40 #define DOUT_ACLK_PERIC1 1 41 #define DOUT_ACLK_PERIC0 2 42 #define CLK_SCLK_UART0 3 43 #define CLK_SCLK_UART1 4 44 #define CLK_SCLK_UART2 5 45 #define CLK_SCLK_UART3 6 46 #define CLK_SCLK_SPI0 7 47 #define CLK_SCLK_SPI1 8 48 #define CLK_SCLK_SPI2 9 49 #define CLK_SCLK_SPI3 10 50 #define CLK_SCLK_SPI4 11 51 #define CLK_SCLK_SPDIF 12 52 #define CLK_SCLK_PCM1 13 53 #define CLK_SCLK_I2S1 14 54 #define CLK_ACLK_PERIC0_66 15 55 #define CLK_ACLK_PERIC1_66 16 56 #define TOP0_NR_CLK 17 57 58 /* TOP1 */ 59 #define DOUT_ACLK_FSYS1_200 1 60 #define DOUT_ACLK_FSYS0_200 2 61 #define DOUT_SCLK_MMC2 3 62 #define DOUT_SCLK_MMC1 4 63 #define DOUT_SCLK_MMC0 5 64 #define CLK_SCLK_MMC2 6 65 #define CLK_SCLK_MMC1 7 66 #define CLK_SCLK_MMC0 8 67 #define CLK_ACLK_FSYS0_200 9 68 #define CLK_ACLK_FSYS1_200 10 69 #define CLK_SCLK_PHY_FSYS1 11 70 #define CLK_SCLK_PHY_FSYS1_26M 12 71 #define MOUT_SCLK_UFSUNIPRO20 13 72 #define DOUT_SCLK_UFSUNIPRO20 14 73 #define CLK_SCLK_UFSUNIPRO20 15 74 #define DOUT_SCLK_PHY_FSYS1 16 75 #define DOUT_SCLK_PHY_FSYS1_26M 17 76 #define TOP1_NR_CLK 18 77 78 /* CCORE */ 79 #define PCLK_RTC 1 80 #define CCORE_NR_CLK 2 81 82 /* PERIC0 */ 83 #define PCLK_UART0 1 84 #define SCLK_UART0 2 85 #define PCLK_HSI2C0 3 86 #define PCLK_HSI2C1 4 87 #define PCLK_HSI2C4 5 88 #define PCLK_HSI2C5 6 89 #define PCLK_HSI2C9 7 90 #define PCLK_HSI2C10 8 91 #define PCLK_HSI2C11 9 92 #define PCLK_PWM 10 93 #define SCLK_PWM 11 94 #define PCLK_ADCIF 12 95 #define PERIC0_NR_CLK 13 96 97 /* PERIC1 */ 98 #define PCLK_UART1 1 99 #define PCLK_UART2 2 100 #define PCLK_UART3 3 101 #define SCLK_UART1 4 102 #define SCLK_UART2 5 103 #define SCLK_UART3 6 104 #define PCLK_HSI2C2 7 105 #define PCLK_HSI2C3 8 106 #define PCLK_HSI2C6 9 107 #define PCLK_HSI2C7 10 108 #define PCLK_HSI2C8 11 109 #define PCLK_SPI0 12 110 #define PCLK_SPI1 13 111 #define PCLK_SPI2 14 112 #define PCLK_SPI3 15 113 #define PCLK_SPI4 16 114 #define SCLK_SPI0 17 115 #define SCLK_SPI1 18 116 #define SCLK_SPI2 19 117 #define SCLK_SPI3 20 118 #define SCLK_SPI4 21 119 #define PCLK_I2S1 22 120 #define PCLK_PCM1 23 121 #define PCLK_SPDIF 24 122 #define SCLK_I2S1 25 123 #define SCLK_PCM1 26 124 #define SCLK_SPDIF 27 125 #define PERIC1_NR_CLK 28 126 127 /* PERIS */ 128 #define PCLK_CHIPID 1 129 #define SCLK_CHIPID 2 130 #define PCLK_WDT 3 131 #define PCLK_TMU 4 132 #define SCLK_TMU 5 133 #define PERIS_NR_CLK 6 134 135 /* FSYS0 */ 136 #define ACLK_MMC2 1 137 #define ACLK_AXIUS_USBDRD30X_FSYS0X 2 138 #define ACLK_USBDRD300 3 139 #define SCLK_USBDRD300_SUSPENDCLK 4 140 #define SCLK_USBDRD300_REFCLK 5 141 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 142 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 143 #define OSCCLK_PHY_CLKOUT_USB30_PHY 8 144 #define ACLK_PDMA0 9 145 #define ACLK_PDMA1 10 146 #define FSYS0_NR_CLK 11 147 148 /* FSYS1 */ 149 #define ACLK_MMC1 1 150 #define ACLK_MMC0 2 151 #define PHYCLK_UFS20_TX0_SYMBOL 3 152 #define PHYCLK_UFS20_RX0_SYMBOL 4 153 #define PHYCLK_UFS20_RX1_SYMBOL 5 154 #define ACLK_UFS20_LINK 6 155 #define SCLK_UFSUNIPRO20_USER 7 156 #define PHYCLK_UFS20_RX1_SYMBOL_USER 8 157 #define PHYCLK_UFS20_RX0_SYMBOL_USER 9 158 #define PHYCLK_UFS20_TX0_SYMBOL_USER 10 159 #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 160 #define SCLK_COMBO_PHY_EMBEDDED_26M 12 161 #define DOUT_PCLK_FSYS1 13 162 #define PCLK_GPIO_FSYS1 14 163 #define MOUT_FSYS1_PHYCLK_SEL1 15 164 #define FSYS1_NR_CLK 16 165 166 /* MSCL */ 167 #define USERMUX_ACLK_MSCL_532 1 168 #define DOUT_PCLK_MSCL 2 169 #define ACLK_MSCL_0 3 170 #define ACLK_MSCL_1 4 171 #define ACLK_JPEG 5 172 #define ACLK_G2D 6 173 #define ACLK_LH_ASYNC_SI_MSCL_0 7 174 #define ACLK_LH_ASYNC_SI_MSCL_1 8 175 #define ACLK_AXI2ACEL_BRIDGE 9 176 #define ACLK_XIU_MSCLX_0 10 177 #define ACLK_XIU_MSCLX_1 11 178 #define ACLK_QE_MSCL_0 12 179 #define ACLK_QE_MSCL_1 13 180 #define ACLK_QE_JPEG 14 181 #define ACLK_QE_G2D 15 182 #define ACLK_PPMU_MSCL_0 16 183 #define ACLK_PPMU_MSCL_1 17 184 #define ACLK_MSCLNP_133 18 185 #define ACLK_AHB2APB_MSCL0P 19 186 #define ACLK_AHB2APB_MSCL1P 20 187 188 #define PCLK_MSCL_0 21 189 #define PCLK_MSCL_1 22 190 #define PCLK_JPEG 23 191 #define PCLK_G2D 24 192 #define PCLK_QE_MSCL_0 25 193 #define PCLK_QE_MSCL_1 26 194 #define PCLK_QE_JPEG 27 195 #define PCLK_QE_G2D 28 196 #define PCLK_PPMU_MSCL_0 29 197 #define PCLK_PPMU_MSCL_1 30 198 #define PCLK_AXI2ACEL_BRIDGE 31 199 #define PCLK_PMU_MSCL 32 200 #define MSCL_NR_CLK 33 201 202 /* AUD */ 203 #define SCLK_I2S 1 204 #define SCLK_PCM 2 205 #define PCLK_I2S 3 206 #define PCLK_PCM 4 207 #define ACLK_ADMA 5 208 #define AUD_NR_CLK 6 209 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 210