1 /* $NetBSD: exynos5410.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * Copyright (c) 2016 Krzysztof Kozlowski 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Device Tree binding constants for Exynos5421 clock controller. 12 */ 13 14 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 15 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 16 17 /* core clocks */ 18 #define CLK_FIN_PLL 1 19 #define CLK_FOUT_APLL 2 20 #define CLK_FOUT_CPLL 3 21 #define CLK_FOUT_MPLL 4 22 #define CLK_FOUT_BPLL 5 23 #define CLK_FOUT_KPLL 6 24 #define CLK_FOUT_EPLL 7 25 26 /* gate for special clocks (sclk) */ 27 #define CLK_SCLK_UART0 128 28 #define CLK_SCLK_UART1 129 29 #define CLK_SCLK_UART2 130 30 #define CLK_SCLK_UART3 131 31 #define CLK_SCLK_MMC0 132 32 #define CLK_SCLK_MMC1 133 33 #define CLK_SCLK_MMC2 134 34 #define CLK_SCLK_USBD300 150 35 #define CLK_SCLK_USBD301 151 36 #define CLK_SCLK_USBPHY300 152 37 #define CLK_SCLK_USBPHY301 153 38 #define CLK_SCLK_PWM 155 39 40 /* gate clocks */ 41 #define CLK_UART0 257 42 #define CLK_UART1 258 43 #define CLK_UART2 259 44 #define CLK_I2C0 261 45 #define CLK_I2C1 262 46 #define CLK_I2C2 263 47 #define CLK_I2C3 264 48 #define CLK_USI0 265 49 #define CLK_USI1 266 50 #define CLK_USI2 267 51 #define CLK_USI3 268 52 #define CLK_UART3 260 53 #define CLK_PWM 279 54 #define CLK_MCT 315 55 #define CLK_WDT 316 56 #define CLK_RTC 317 57 #define CLK_TMU 318 58 #define CLK_MMC0 351 59 #define CLK_MMC1 352 60 #define CLK_MMC2 353 61 #define CLK_PDMA0 362 62 #define CLK_PDMA1 363 63 #define CLK_USBH20 365 64 #define CLK_USBD300 366 65 #define CLK_USBD301 367 66 #define CLK_SSS 471 67 68 #define CLK_NR_CLKS 512 69 70 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ 71