1 /* $NetBSD: am4.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright 2017 Texas Instruments, Inc. 6 */ 7 #ifndef __DT_BINDINGS_CLK_AM4_H 8 #define __DT_BINDINGS_CLK_AM4_H 9 10 #define AM4_CLKCTRL_OFFSET 0x20 11 #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 12 13 /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 14 15 /* l4_wkup clocks */ 16 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 17 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 18 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) 19 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) 20 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) 21 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) 22 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) 23 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) 24 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) 25 #define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) 26 #define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) 27 #define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) 28 29 /* mpu clocks */ 30 #define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 31 32 /* gfx_l3 clocks */ 33 #define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 34 35 /* l4_rtc clocks */ 36 #define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 37 38 /* l4_per clocks */ 39 #define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 40 #define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 41 #define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 42 #define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 43 #define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 44 #define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 45 #define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) 46 #define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) 47 #define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 48 #define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 49 #define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 50 #define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 51 #define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 52 #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 53 #define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) 54 #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) 55 #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) 56 #define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) 57 #define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) 58 #define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) 59 #define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) 60 #define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) 61 #define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) 62 #define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) 63 #define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) 64 #define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) 65 #define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) 66 #define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) 67 #define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) 68 #define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) 69 #define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) 70 #define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) 71 #define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) 72 #define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) 73 #define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) 74 #define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) 75 #define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) 76 #define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) 77 #define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) 78 #define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) 79 #define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) 80 #define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) 81 #define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) 82 #define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) 83 #define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) 84 #define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) 85 #define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) 86 #define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) 87 #define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) 88 #define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) 89 #define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) 90 #define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) 91 #define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) 92 #define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) 93 #define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) 94 #define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) 95 #define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) 96 #define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) 97 #define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) 98 #define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) 99 #define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) 100 #define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) 101 #define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) 102 #define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) 103 #define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) 104 #define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) 105 #define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) 106 #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 107 #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 108 109 /* XXX: Compatibility part end. */ 110 111 /* l3s_tsc clocks */ 112 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 113 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) 114 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 115 116 /* l4_wkup_aon clocks */ 117 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 118 #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) 119 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 120 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 121 122 /* l4_wkup clocks */ 123 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 124 #define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) 125 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 126 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 127 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) 128 #define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) 129 #define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) 130 #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) 131 #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) 132 #define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) 133 #define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) 134 135 /* mpu clocks */ 136 #define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 137 138 /* gfx_l3 clocks */ 139 #define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 140 141 /* l4_rtc clocks */ 142 #define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 143 144 /* l3 clocks */ 145 #define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 146 #define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 147 #define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 148 #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 149 #define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 150 #define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 151 #define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 152 #define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 153 #define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 154 #define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 155 #define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 156 157 /* l3s clocks */ 158 #define AM4_L3S_CLKCTRL_OFFSET 0x68 159 #define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) 160 #define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) 161 #define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) 162 #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) 163 #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) 164 #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) 165 #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) 166 #define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) 167 #define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) 168 #define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) 169 170 /* pruss_ocp clocks */ 171 #define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 172 #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) 173 #define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) 174 175 /* l4ls clocks */ 176 #define AM4_L4LS_CLKCTRL_OFFSET 0x420 177 #define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) 178 #define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) 179 #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) 180 #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) 181 #define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) 182 #define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) 183 #define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) 184 #define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) 185 #define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) 186 #define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) 187 #define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) 188 #define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) 189 #define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) 190 #define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) 191 #define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) 192 #define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) 193 #define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) 194 #define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) 195 #define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) 196 #define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) 197 #define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) 198 #define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) 199 #define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) 200 #define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) 201 #define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) 202 #define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) 203 #define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) 204 #define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) 205 #define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) 206 #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) 207 #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) 208 #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) 209 #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) 210 #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) 211 #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) 212 #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) 213 #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) 214 #define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) 215 #define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) 216 #define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) 217 #define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) 218 #define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) 219 #define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) 220 #define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) 221 #define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) 222 #define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) 223 224 /* emif clocks */ 225 #define AM4_EMIF_CLKCTRL_OFFSET 0x720 226 #define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) 227 #define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) 228 229 /* dss clocks */ 230 #define AM4_DSS_CLKCTRL_OFFSET 0xa20 231 #define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) 232 #define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) 233 234 /* cpsw_125mhz clocks */ 235 #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 236 #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) 237 #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) 238 239 #endif 240