1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SAMSUNG EXYNOS5420 SoC device tree source 4 * 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file. 9 * EXYNOS5420 based board files can include this file and provide 10 * values for board specfic bindings. 11 */ 12 13#include "exynos54xx.dtsi" 14#include <dt-bindings/clock/exynos5420.h> 15#include <dt-bindings/clock/exynos-audss-clk.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17 18/ { 19 compatible = "samsung,exynos5420", "samsung,exynos5"; 20 21 aliases { 22 mshc0 = &mmc_0; 23 mshc1 = &mmc_1; 24 mshc2 = &mmc_2; 25 pinctrl0 = &pinctrl_0; 26 pinctrl1 = &pinctrl_1; 27 pinctrl2 = &pinctrl_2; 28 pinctrl3 = &pinctrl_3; 29 pinctrl4 = &pinctrl_4; 30 i2c8 = &hsi2c_8; 31 i2c9 = &hsi2c_9; 32 i2c10 = &hsi2c_10; 33 gsc0 = &gsc_0; 34 gsc1 = &gsc_1; 35 spi0 = &spi_0; 36 spi1 = &spi_1; 37 spi2 = &spi_2; 38 }; 39 40 /* 41 * The 'cpus' node is not present here but instead it is provided 42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. 43 */ 44 45 cluster_a15_opp_table: opp_table0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-1800000000 { 50 opp-hz = /bits/ 64 <1800000000>; 51 opp-microvolt = <1250000>; 52 clock-latency-ns = <140000>; 53 }; 54 opp-1700000000 { 55 opp-hz = /bits/ 64 <1700000000>; 56 opp-microvolt = <1212500>; 57 clock-latency-ns = <140000>; 58 }; 59 opp-1600000000 { 60 opp-hz = /bits/ 64 <1600000000>; 61 opp-microvolt = <1175000>; 62 clock-latency-ns = <140000>; 63 }; 64 opp-1500000000 { 65 opp-hz = /bits/ 64 <1500000000>; 66 opp-microvolt = <1137500>; 67 clock-latency-ns = <140000>; 68 }; 69 opp-1400000000 { 70 opp-hz = /bits/ 64 <1400000000>; 71 opp-microvolt = <1112500>; 72 clock-latency-ns = <140000>; 73 }; 74 opp-1300000000 { 75 opp-hz = /bits/ 64 <1300000000>; 76 opp-microvolt = <1062500>; 77 clock-latency-ns = <140000>; 78 }; 79 opp-1200000000 { 80 opp-hz = /bits/ 64 <1200000000>; 81 opp-microvolt = <1037500>; 82 clock-latency-ns = <140000>; 83 }; 84 opp-1100000000 { 85 opp-hz = /bits/ 64 <1100000000>; 86 opp-microvolt = <1012500>; 87 clock-latency-ns = <140000>; 88 }; 89 opp-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = < 987500>; 92 clock-latency-ns = <140000>; 93 }; 94 opp-900000000 { 95 opp-hz = /bits/ 64 <900000000>; 96 opp-microvolt = < 962500>; 97 clock-latency-ns = <140000>; 98 }; 99 opp-800000000 { 100 opp-hz = /bits/ 64 <800000000>; 101 opp-microvolt = < 937500>; 102 clock-latency-ns = <140000>; 103 }; 104 opp-700000000 { 105 opp-hz = /bits/ 64 <700000000>; 106 opp-microvolt = < 912500>; 107 clock-latency-ns = <140000>; 108 }; 109 }; 110 111 cluster_a7_opp_table: opp_table1 { 112 compatible = "operating-points-v2"; 113 opp-shared; 114 115 opp-1300000000 { 116 opp-hz = /bits/ 64 <1300000000>; 117 opp-microvolt = <1275000>; 118 clock-latency-ns = <140000>; 119 }; 120 opp-1200000000 { 121 opp-hz = /bits/ 64 <1200000000>; 122 opp-microvolt = <1212500>; 123 clock-latency-ns = <140000>; 124 }; 125 opp-1100000000 { 126 opp-hz = /bits/ 64 <1100000000>; 127 opp-microvolt = <1162500>; 128 clock-latency-ns = <140000>; 129 }; 130 opp-1000000000 { 131 opp-hz = /bits/ 64 <1000000000>; 132 opp-microvolt = <1112500>; 133 clock-latency-ns = <140000>; 134 }; 135 opp-900000000 { 136 opp-hz = /bits/ 64 <900000000>; 137 opp-microvolt = <1062500>; 138 clock-latency-ns = <140000>; 139 }; 140 opp-800000000 { 141 opp-hz = /bits/ 64 <800000000>; 142 opp-microvolt = <1025000>; 143 clock-latency-ns = <140000>; 144 }; 145 opp-700000000 { 146 opp-hz = /bits/ 64 <700000000>; 147 opp-microvolt = <975000>; 148 clock-latency-ns = <140000>; 149 }; 150 opp-600000000 { 151 opp-hz = /bits/ 64 <600000000>; 152 opp-microvolt = <937500>; 153 clock-latency-ns = <140000>; 154 }; 155 }; 156 157 soc: soc { 158 cci: cci@10d20000 { 159 compatible = "arm,cci-400"; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 reg = <0x10d20000 0x1000>; 163 ranges = <0x0 0x10d20000 0x6000>; 164 165 cci_control0: slave-if@4000 { 166 compatible = "arm,cci-400-ctrl-if"; 167 interface-type = "ace"; 168 reg = <0x4000 0x1000>; 169 }; 170 cci_control1: slave-if@5000 { 171 compatible = "arm,cci-400-ctrl-if"; 172 interface-type = "ace"; 173 reg = <0x5000 0x1000>; 174 }; 175 }; 176 177 clock: clock-controller@10010000 { 178 compatible = "samsung,exynos5420-clock", "syscon"; 179 reg = <0x10010000 0x30000>; 180 #clock-cells = <1>; 181 }; 182 183 clock_audss: audss-clock-controller@3810000 { 184 compatible = "samsung,exynos5420-audss-clock"; 185 reg = <0x03810000 0x0C>; 186 #clock-cells = <1>; 187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 190 power-domains = <&mau_pd>; 191 }; 192 193 mfc: codec@11000000 { 194 compatible = "samsung,mfc-v7"; 195 reg = <0x11000000 0x10000>; 196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clock CLK_MFC>; 198 clock-names = "mfc"; 199 power-domains = <&mfc_pd>; 200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 201 iommu-names = "left", "right"; 202 }; 203 204 mmc_0: mmc@12200000 { 205 compatible = "samsung,exynos5420-dw-mshc-smu"; 206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 reg = <0x12200000 0x2000>; 210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 211 clock-names = "biu", "ciu"; 212 fifo-depth = <0x40>; 213 status = "disabled"; 214 }; 215 216 mmc_1: mmc@12210000 { 217 compatible = "samsung,exynos5420-dw-mshc-smu"; 218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x12210000 0x2000>; 222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 223 clock-names = "biu", "ciu"; 224 fifo-depth = <0x40>; 225 status = "disabled"; 226 }; 227 228 mmc_2: mmc@12220000 { 229 compatible = "samsung,exynos5420-dw-mshc"; 230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <0x12220000 0x1000>; 234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 235 clock-names = "biu", "ciu"; 236 fifo-depth = <0x40>; 237 status = "disabled"; 238 }; 239 240 dmc: memory-controller@10c20000 { 241 compatible = "samsung,exynos5422-dmc"; 242 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; 243 interrupt-parent = <&combiner>; 244 interrupts = <16 0>, <16 1>; 245 interrupt-names = "drex_0", "drex_1"; 246 clocks = <&clock CLK_FOUT_SPLL>, 247 <&clock CLK_MOUT_SCLK_SPLL>, 248 <&clock CLK_FF_DOUT_SPLL2>, 249 <&clock CLK_FOUT_BPLL>, 250 <&clock CLK_MOUT_BPLL>, 251 <&clock CLK_SCLK_BPLL>, 252 <&clock CLK_MOUT_MX_MSPLL_CCORE>, 253 <&clock CLK_MOUT_MCLK_CDREX>; 254 clock-names = "fout_spll", 255 "mout_sclk_spll", 256 "ff_dout_spll2", 257 "fout_bpll", 258 "mout_bpll", 259 "sclk_bpll", 260 "mout_mx_mspll_ccore", 261 "mout_mclk_cdrex"; 262 samsung,syscon-clk = <&clock>; 263 status = "disabled"; 264 }; 265 266 nocp_mem0_0: nocp@10ca1000 { 267 compatible = "samsung,exynos5420-nocp"; 268 reg = <0x10CA1000 0x200>; 269 status = "disabled"; 270 }; 271 272 nocp_mem0_1: nocp@10ca1400 { 273 compatible = "samsung,exynos5420-nocp"; 274 reg = <0x10CA1400 0x200>; 275 status = "disabled"; 276 }; 277 278 nocp_mem1_0: nocp@10ca1800 { 279 compatible = "samsung,exynos5420-nocp"; 280 reg = <0x10CA1800 0x200>; 281 status = "disabled"; 282 }; 283 284 nocp_mem1_1: nocp@10ca1c00 { 285 compatible = "samsung,exynos5420-nocp"; 286 reg = <0x10CA1C00 0x200>; 287 status = "disabled"; 288 }; 289 290 nocp_g3d_0: nocp@11a51000 { 291 compatible = "samsung,exynos5420-nocp"; 292 reg = <0x11A51000 0x200>; 293 status = "disabled"; 294 }; 295 296 nocp_g3d_1: nocp@11a51400 { 297 compatible = "samsung,exynos5420-nocp"; 298 reg = <0x11A51400 0x200>; 299 status = "disabled"; 300 }; 301 302 ppmu_dmc0_0: ppmu@10d00000 { 303 compatible = "samsung,exynos-ppmu"; 304 reg = <0x10d00000 0x2000>; 305 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; 306 clock-names = "ppmu"; 307 events { 308 ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { 309 event-name = "ppmu-event3-dmc0_0"; 310 }; 311 }; 312 }; 313 314 ppmu_dmc0_1: ppmu@10d10000 { 315 compatible = "samsung,exynos-ppmu"; 316 reg = <0x10d10000 0x2000>; 317 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; 318 clock-names = "ppmu"; 319 events { 320 ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { 321 event-name = "ppmu-event3-dmc0_1"; 322 }; 323 }; 324 }; 325 326 ppmu_dmc1_0: ppmu@10d60000 { 327 compatible = "samsung,exynos-ppmu"; 328 reg = <0x10d60000 0x2000>; 329 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; 330 clock-names = "ppmu"; 331 events { 332 ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { 333 event-name = "ppmu-event3-dmc1_0"; 334 }; 335 }; 336 }; 337 338 ppmu_dmc1_1: ppmu@10d70000 { 339 compatible = "samsung,exynos-ppmu"; 340 reg = <0x10d70000 0x2000>; 341 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; 342 clock-names = "ppmu"; 343 events { 344 ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { 345 event-name = "ppmu-event3-dmc1_1"; 346 }; 347 }; 348 }; 349 350 gsc_pd: power-domain@10044000 { 351 compatible = "samsung,exynos4210-pd"; 352 reg = <0x10044000 0x20>; 353 #power-domain-cells = <0>; 354 label = "GSC"; 355 }; 356 357 isp_pd: power-domain@10044020 { 358 compatible = "samsung,exynos4210-pd"; 359 reg = <0x10044020 0x20>; 360 #power-domain-cells = <0>; 361 label = "ISP"; 362 }; 363 364 mfc_pd: power-domain@10044060 { 365 compatible = "samsung,exynos4210-pd"; 366 reg = <0x10044060 0x20>; 367 #power-domain-cells = <0>; 368 label = "MFC"; 369 }; 370 371 g3d_pd: power-domain@10044080 { 372 compatible = "samsung,exynos4210-pd"; 373 reg = <0x10044080 0x20>; 374 #power-domain-cells = <0>; 375 label = "G3D"; 376 }; 377 378 disp_pd: power-domain@100440c0 { 379 compatible = "samsung,exynos4210-pd"; 380 reg = <0x100440C0 0x20>; 381 #power-domain-cells = <0>; 382 label = "DISP"; 383 }; 384 385 mau_pd: power-domain@100440e0 { 386 compatible = "samsung,exynos4210-pd"; 387 reg = <0x100440E0 0x20>; 388 #power-domain-cells = <0>; 389 label = "MAU"; 390 }; 391 392 msc_pd: power-domain@10044120 { 393 compatible = "samsung,exynos4210-pd"; 394 reg = <0x10044120 0x20>; 395 #power-domain-cells = <0>; 396 label = "MSC"; 397 }; 398 399 pinctrl_0: pinctrl@13400000 { 400 compatible = "samsung,exynos5420-pinctrl"; 401 reg = <0x13400000 0x1000>; 402 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 403 404 wakeup-interrupt-controller { 405 compatible = "samsung,exynos4210-wakeup-eint"; 406 interrupt-parent = <&gic>; 407 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 408 }; 409 }; 410 411 pinctrl_1: pinctrl@13410000 { 412 compatible = "samsung,exynos5420-pinctrl"; 413 reg = <0x13410000 0x1000>; 414 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 415 }; 416 417 pinctrl_2: pinctrl@14000000 { 418 compatible = "samsung,exynos5420-pinctrl"; 419 reg = <0x14000000 0x1000>; 420 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 421 }; 422 423 pinctrl_3: pinctrl@14010000 { 424 compatible = "samsung,exynos5420-pinctrl"; 425 reg = <0x14010000 0x1000>; 426 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 427 }; 428 429 pinctrl_4: pinctrl@3860000 { 430 compatible = "samsung,exynos5420-pinctrl"; 431 reg = <0x03860000 0x1000>; 432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 433 power-domains = <&mau_pd>; 434 }; 435 436 amba { 437 #address-cells = <1>; 438 #size-cells = <1>; 439 compatible = "simple-bus"; 440 interrupt-parent = <&gic>; 441 ranges; 442 443 adma: adma@3880000 { 444 compatible = "arm,pl330", "arm,primecell"; 445 reg = <0x03880000 0x1000>; 446 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clock_audss EXYNOS_ADMA>; 448 clock-names = "apb_pclk"; 449 #dma-cells = <1>; 450 #dma-channels = <6>; 451 #dma-requests = <16>; 452 power-domains = <&mau_pd>; 453 }; 454 455 pdma0: pdma@121a0000 { 456 compatible = "arm,pl330", "arm,primecell"; 457 reg = <0x121A0000 0x1000>; 458 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clock CLK_PDMA0>; 460 clock-names = "apb_pclk"; 461 #dma-cells = <1>; 462 #dma-channels = <8>; 463 #dma-requests = <32>; 464 }; 465 466 pdma1: pdma@121b0000 { 467 compatible = "arm,pl330", "arm,primecell"; 468 reg = <0x121B0000 0x1000>; 469 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clock CLK_PDMA1>; 471 clock-names = "apb_pclk"; 472 #dma-cells = <1>; 473 #dma-channels = <8>; 474 #dma-requests = <32>; 475 }; 476 477 mdma0: mdma@10800000 { 478 compatible = "arm,pl330", "arm,primecell"; 479 reg = <0x10800000 0x1000>; 480 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clock CLK_MDMA0>; 482 clock-names = "apb_pclk"; 483 #dma-cells = <1>; 484 #dma-channels = <8>; 485 #dma-requests = <1>; 486 }; 487 488 mdma1: mdma@11c10000 { 489 compatible = "arm,pl330", "arm,primecell"; 490 reg = <0x11C10000 0x1000>; 491 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clock CLK_MDMA1>; 493 clock-names = "apb_pclk"; 494 #dma-cells = <1>; 495 #dma-channels = <8>; 496 #dma-requests = <1>; 497 /* 498 * MDMA1 can support both secure and non-secure 499 * AXI transactions. When this is enabled in 500 * the kernel for boards that run in secure 501 * mode, we are getting imprecise external 502 * aborts causing the kernel to oops. 503 */ 504 status = "disabled"; 505 }; 506 }; 507 508 i2s0: i2s@3830000 { 509 compatible = "samsung,exynos5420-i2s"; 510 reg = <0x03830000 0x100>; 511 dmas = <&adma 0>, 512 <&adma 2>, 513 <&adma 1>; 514 dma-names = "tx", "rx", "tx-sec"; 515 clocks = <&clock_audss EXYNOS_I2S_BUS>, 516 <&clock_audss EXYNOS_I2S_BUS>, 517 <&clock_audss EXYNOS_SCLK_I2S>; 518 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 519 #clock-cells = <1>; 520 clock-output-names = "i2s_cdclk0"; 521 #sound-dai-cells = <1>; 522 samsung,idma-addr = <0x03000000>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&i2s0_bus>; 525 power-domains = <&mau_pd>; 526 status = "disabled"; 527 }; 528 529 i2s1: i2s@12d60000 { 530 compatible = "samsung,exynos5420-i2s"; 531 reg = <0x12D60000 0x100>; 532 dmas = <&pdma1 12>, 533 <&pdma1 11>; 534 dma-names = "tx", "rx"; 535 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; 536 clock-names = "iis", "i2s_opclk0"; 537 #clock-cells = <1>; 538 clock-output-names = "i2s_cdclk1"; 539 #sound-dai-cells = <1>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2s1_bus>; 542 status = "disabled"; 543 }; 544 545 i2s2: i2s@12d70000 { 546 compatible = "samsung,exynos5420-i2s"; 547 reg = <0x12D70000 0x100>; 548 dmas = <&pdma0 12>, 549 <&pdma0 11>; 550 dma-names = "tx", "rx"; 551 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; 552 clock-names = "iis", "i2s_opclk0"; 553 #clock-cells = <1>; 554 clock-output-names = "i2s_cdclk2"; 555 #sound-dai-cells = <1>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2s2_bus>; 558 status = "disabled"; 559 }; 560 561 spi_0: spi@12d20000 { 562 compatible = "samsung,exynos4210-spi"; 563 reg = <0x12d20000 0x100>; 564 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 565 dmas = <&pdma0 5 566 &pdma0 4>; 567 dma-names = "tx", "rx"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&spi0_bus>; 572 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 573 clock-names = "spi", "spi_busclk0"; 574 status = "disabled"; 575 }; 576 577 spi_1: spi@12d30000 { 578 compatible = "samsung,exynos4210-spi"; 579 reg = <0x12d30000 0x100>; 580 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 581 dmas = <&pdma1 5 582 &pdma1 4>; 583 dma-names = "tx", "rx"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&spi1_bus>; 588 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 589 clock-names = "spi", "spi_busclk0"; 590 status = "disabled"; 591 }; 592 593 spi_2: spi@12d40000 { 594 compatible = "samsung,exynos4210-spi"; 595 reg = <0x12d40000 0x100>; 596 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 597 dmas = <&pdma0 7 598 &pdma0 6>; 599 dma-names = "tx", "rx"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&spi2_bus>; 604 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 605 clock-names = "spi", "spi_busclk0"; 606 status = "disabled"; 607 }; 608 609 dp_phy: dp-video-phy { 610 compatible = "samsung,exynos5420-dp-video-phy"; 611 samsung,pmu-syscon = <&pmu_system_controller>; 612 #phy-cells = <0>; 613 }; 614 615 mipi_phy: mipi-video-phy { 616 compatible = "samsung,s5pv210-mipi-video-phy"; 617 syscon = <&pmu_system_controller>; 618 #phy-cells = <1>; 619 }; 620 621 dsi@14500000 { 622 compatible = "samsung,exynos5410-mipi-dsi"; 623 reg = <0x14500000 0x10000>; 624 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 625 phys = <&mipi_phy 1>; 626 phy-names = "dsim"; 627 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; 628 clock-names = "bus_clk", "pll_clk"; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 status = "disabled"; 632 }; 633 634 hsi2c_8: i2c@12e00000 { 635 compatible = "samsung,exynos5250-hsi2c"; 636 reg = <0x12E00000 0x1000>; 637 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&i2c8_hs_bus>; 642 clocks = <&clock CLK_USI4>; 643 clock-names = "hsi2c"; 644 status = "disabled"; 645 }; 646 647 hsi2c_9: i2c@12e10000 { 648 compatible = "samsung,exynos5250-hsi2c"; 649 reg = <0x12E10000 0x1000>; 650 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&i2c9_hs_bus>; 655 clocks = <&clock CLK_USI5>; 656 clock-names = "hsi2c"; 657 status = "disabled"; 658 }; 659 660 hsi2c_10: i2c@12e20000 { 661 compatible = "samsung,exynos5250-hsi2c"; 662 reg = <0x12E20000 0x1000>; 663 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&i2c10_hs_bus>; 668 clocks = <&clock CLK_USI6>; 669 clock-names = "hsi2c"; 670 status = "disabled"; 671 }; 672 673 hdmi: hdmi@14530000 { 674 compatible = "samsung,exynos5420-hdmi"; 675 reg = <0x14530000 0x70000>; 676 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 678 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 679 <&clock CLK_MOUT_HDMI>; 680 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 681 "sclk_hdmiphy", "mout_hdmi"; 682 phy = <&hdmiphy>; 683 samsung,syscon-phandle = <&pmu_system_controller>; 684 status = "disabled"; 685 power-domains = <&disp_pd>; 686 #sound-dai-cells = <0>; 687 }; 688 689 hdmiphy: hdmiphy@145d0000 { 690 reg = <0x145D0000 0x20>; 691 }; 692 693 hdmicec: cec@101b0000 { 694 compatible = "samsung,s5p-cec"; 695 reg = <0x101B0000 0x200>; 696 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clock CLK_HDMI_CEC>; 698 clock-names = "hdmicec"; 699 samsung,syscon-phandle = <&pmu_system_controller>; 700 hdmi-phandle = <&hdmi>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&hdmi_cec>; 703 status = "disabled"; 704 }; 705 706 mixer: mixer@14450000 { 707 compatible = "samsung,exynos5420-mixer"; 708 reg = <0x14450000 0x10000>; 709 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 711 <&clock CLK_SCLK_HDMI>; 712 clock-names = "mixer", "hdmi", "sclk_hdmi"; 713 power-domains = <&disp_pd>; 714 iommus = <&sysmmu_tv>; 715 status = "disabled"; 716 }; 717 718 rotator: rotator@11c00000 { 719 compatible = "samsung,exynos5250-rotator"; 720 reg = <0x11C00000 0x64>; 721 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clock CLK_ROTATOR>; 723 clock-names = "rotator"; 724 iommus = <&sysmmu_rotator>; 725 }; 726 727 gsc_0: video-scaler@13e00000 { 728 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 729 reg = <0x13e00000 0x1000>; 730 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&clock CLK_GSCL0>; 732 clock-names = "gscl"; 733 power-domains = <&gsc_pd>; 734 iommus = <&sysmmu_gscl0>; 735 }; 736 737 gsc_1: video-scaler@13e10000 { 738 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 739 reg = <0x13e10000 0x1000>; 740 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clock CLK_GSCL1>; 742 clock-names = "gscl"; 743 power-domains = <&gsc_pd>; 744 iommus = <&sysmmu_gscl1>; 745 }; 746 747 scaler_0: scaler@12800000 { 748 compatible = "samsung,exynos5420-scaler"; 749 reg = <0x12800000 0x1294>; 750 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&clock CLK_MSCL0>; 752 clock-names = "mscl"; 753 power-domains = <&msc_pd>; 754 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; 755 }; 756 757 scaler_1: scaler@12810000 { 758 compatible = "samsung,exynos5420-scaler"; 759 reg = <0x12810000 0x1294>; 760 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clock CLK_MSCL1>; 762 clock-names = "mscl"; 763 power-domains = <&msc_pd>; 764 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; 765 }; 766 767 scaler_2: scaler@12820000 { 768 compatible = "samsung,exynos5420-scaler"; 769 reg = <0x12820000 0x1294>; 770 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&clock CLK_MSCL2>; 772 clock-names = "mscl"; 773 power-domains = <&msc_pd>; 774 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; 775 }; 776 777 jpeg_0: jpeg@11f50000 { 778 compatible = "samsung,exynos5420-jpeg"; 779 reg = <0x11F50000 0x1000>; 780 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 781 clock-names = "jpeg"; 782 clocks = <&clock CLK_JPEG>; 783 iommus = <&sysmmu_jpeg0>; 784 }; 785 786 jpeg_1: jpeg@11f60000 { 787 compatible = "samsung,exynos5420-jpeg"; 788 reg = <0x11F60000 0x1000>; 789 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 790 clock-names = "jpeg"; 791 clocks = <&clock CLK_JPEG2>; 792 iommus = <&sysmmu_jpeg1>; 793 }; 794 795 pmu_system_controller: system-controller@10040000 { 796 compatible = "samsung,exynos5420-pmu", "syscon"; 797 reg = <0x10040000 0x5000>; 798 clock-names = "clkout16"; 799 clocks = <&clock CLK_FIN_PLL>; 800 #clock-cells = <1>; 801 interrupt-controller; 802 #interrupt-cells = <3>; 803 interrupt-parent = <&gic>; 804 }; 805 806 tmu_cpu0: tmu@10060000 { 807 compatible = "samsung,exynos5420-tmu"; 808 reg = <0x10060000 0x100>; 809 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&clock CLK_TMU>; 811 clock-names = "tmu_apbif"; 812 #thermal-sensor-cells = <0>; 813 }; 814 815 tmu_cpu1: tmu@10064000 { 816 compatible = "samsung,exynos5420-tmu"; 817 reg = <0x10064000 0x100>; 818 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clock CLK_TMU>; 820 clock-names = "tmu_apbif"; 821 #thermal-sensor-cells = <0>; 822 }; 823 824 tmu_cpu2: tmu@10068000 { 825 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 826 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 827 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 829 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 830 #thermal-sensor-cells = <0>; 831 }; 832 833 tmu_cpu3: tmu@1006c000 { 834 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 835 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 836 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 838 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 839 #thermal-sensor-cells = <0>; 840 }; 841 842 tmu_gpu: tmu@100a0000 { 843 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 844 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 845 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 847 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 848 #thermal-sensor-cells = <0>; 849 }; 850 851 sysmmu_g2dr: sysmmu@10a60000 { 852 compatible = "samsung,exynos-sysmmu"; 853 reg = <0x10A60000 0x1000>; 854 interrupt-parent = <&combiner>; 855 interrupts = <24 5>; 856 clock-names = "sysmmu", "master"; 857 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 858 #iommu-cells = <0>; 859 }; 860 861 sysmmu_g2dw: sysmmu@10a70000 { 862 compatible = "samsung,exynos-sysmmu"; 863 reg = <0x10A70000 0x1000>; 864 interrupt-parent = <&combiner>; 865 interrupts = <22 2>; 866 clock-names = "sysmmu", "master"; 867 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 868 #iommu-cells = <0>; 869 }; 870 871 sysmmu_tv: sysmmu@14650000 { 872 compatible = "samsung,exynos-sysmmu"; 873 reg = <0x14650000 0x1000>; 874 interrupt-parent = <&combiner>; 875 interrupts = <7 4>; 876 clock-names = "sysmmu", "master"; 877 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; 878 power-domains = <&disp_pd>; 879 #iommu-cells = <0>; 880 }; 881 882 sysmmu_gscl0: sysmmu@13e80000 { 883 compatible = "samsung,exynos-sysmmu"; 884 reg = <0x13E80000 0x1000>; 885 interrupt-parent = <&combiner>; 886 interrupts = <2 0>; 887 clock-names = "sysmmu", "master"; 888 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 889 power-domains = <&gsc_pd>; 890 #iommu-cells = <0>; 891 }; 892 893 sysmmu_gscl1: sysmmu@13e90000 { 894 compatible = "samsung,exynos-sysmmu"; 895 reg = <0x13E90000 0x1000>; 896 interrupt-parent = <&combiner>; 897 interrupts = <2 2>; 898 clock-names = "sysmmu", "master"; 899 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 900 power-domains = <&gsc_pd>; 901 #iommu-cells = <0>; 902 }; 903 904 sysmmu_scaler0r: sysmmu@12880000 { 905 compatible = "samsung,exynos-sysmmu"; 906 reg = <0x12880000 0x1000>; 907 interrupt-parent = <&combiner>; 908 interrupts = <22 4>; 909 clock-names = "sysmmu", "master"; 910 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 911 power-domains = <&msc_pd>; 912 #iommu-cells = <0>; 913 }; 914 915 sysmmu_scaler1r: sysmmu@12890000 { 916 compatible = "samsung,exynos-sysmmu"; 917 reg = <0x12890000 0x1000>; 918 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 919 clock-names = "sysmmu", "master"; 920 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 921 power-domains = <&msc_pd>; 922 #iommu-cells = <0>; 923 }; 924 925 sysmmu_scaler2r: sysmmu@128a0000 { 926 compatible = "samsung,exynos-sysmmu"; 927 reg = <0x128A0000 0x1000>; 928 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 929 clock-names = "sysmmu", "master"; 930 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 931 power-domains = <&msc_pd>; 932 #iommu-cells = <0>; 933 }; 934 935 sysmmu_scaler0w: sysmmu@128c0000 { 936 compatible = "samsung,exynos-sysmmu"; 937 reg = <0x128C0000 0x1000>; 938 interrupt-parent = <&combiner>; 939 interrupts = <27 2>; 940 clock-names = "sysmmu", "master"; 941 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 942 power-domains = <&msc_pd>; 943 #iommu-cells = <0>; 944 }; 945 946 sysmmu_scaler1w: sysmmu@128d0000 { 947 compatible = "samsung,exynos-sysmmu"; 948 reg = <0x128D0000 0x1000>; 949 interrupt-parent = <&combiner>; 950 interrupts = <22 6>; 951 clock-names = "sysmmu", "master"; 952 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 953 power-domains = <&msc_pd>; 954 #iommu-cells = <0>; 955 }; 956 957 sysmmu_scaler2w: sysmmu@128e0000 { 958 compatible = "samsung,exynos-sysmmu"; 959 reg = <0x128E0000 0x1000>; 960 interrupt-parent = <&combiner>; 961 interrupts = <19 6>; 962 clock-names = "sysmmu", "master"; 963 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 964 power-domains = <&msc_pd>; 965 #iommu-cells = <0>; 966 }; 967 968 sysmmu_rotator: sysmmu@11d40000 { 969 compatible = "samsung,exynos-sysmmu"; 970 reg = <0x11D40000 0x1000>; 971 interrupt-parent = <&combiner>; 972 interrupts = <4 0>; 973 clock-names = "sysmmu", "master"; 974 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 975 #iommu-cells = <0>; 976 }; 977 978 sysmmu_jpeg0: sysmmu@11f10000 { 979 compatible = "samsung,exynos-sysmmu"; 980 reg = <0x11F10000 0x1000>; 981 interrupt-parent = <&combiner>; 982 interrupts = <4 2>; 983 clock-names = "sysmmu", "master"; 984 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 985 #iommu-cells = <0>; 986 }; 987 988 sysmmu_jpeg1: sysmmu@11f20000 { 989 compatible = "samsung,exynos-sysmmu"; 990 reg = <0x11F20000 0x1000>; 991 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 992 clock-names = "sysmmu", "master"; 993 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; 994 #iommu-cells = <0>; 995 }; 996 997 sysmmu_mfc_l: sysmmu@11200000 { 998 compatible = "samsung,exynos-sysmmu"; 999 reg = <0x11200000 0x1000>; 1000 interrupt-parent = <&combiner>; 1001 interrupts = <6 2>; 1002 clock-names = "sysmmu", "master"; 1003 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 1004 power-domains = <&mfc_pd>; 1005 #iommu-cells = <0>; 1006 }; 1007 1008 sysmmu_mfc_r: sysmmu@11210000 { 1009 compatible = "samsung,exynos-sysmmu"; 1010 reg = <0x11210000 0x1000>; 1011 interrupt-parent = <&combiner>; 1012 interrupts = <8 5>; 1013 clock-names = "sysmmu", "master"; 1014 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 1015 power-domains = <&mfc_pd>; 1016 #iommu-cells = <0>; 1017 }; 1018 1019 sysmmu_fimd1_0: sysmmu@14640000 { 1020 compatible = "samsung,exynos-sysmmu"; 1021 reg = <0x14640000 0x1000>; 1022 interrupt-parent = <&combiner>; 1023 interrupts = <3 2>; 1024 clock-names = "sysmmu", "master"; 1025 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; 1026 power-domains = <&disp_pd>; 1027 #iommu-cells = <0>; 1028 }; 1029 1030 sysmmu_fimd1_1: sysmmu@14680000 { 1031 compatible = "samsung,exynos-sysmmu"; 1032 reg = <0x14680000 0x1000>; 1033 interrupt-parent = <&combiner>; 1034 interrupts = <3 0>; 1035 clock-names = "sysmmu", "master"; 1036 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; 1037 power-domains = <&disp_pd>; 1038 #iommu-cells = <0>; 1039 }; 1040 1041 bus_wcore: bus_wcore { 1042 compatible = "samsung,exynos-bus"; 1043 clocks = <&clock CLK_DOUT_ACLK400_WCORE>; 1044 clock-names = "bus"; 1045 operating-points-v2 = <&bus_wcore_opp_table>; 1046 status = "disabled"; 1047 }; 1048 1049 bus_noc: bus_noc { 1050 compatible = "samsung,exynos-bus"; 1051 clocks = <&clock CLK_DOUT_ACLK100_NOC>; 1052 clock-names = "bus"; 1053 operating-points-v2 = <&bus_noc_opp_table>; 1054 status = "disabled"; 1055 }; 1056 1057 bus_fsys_apb: bus_fsys_apb { 1058 compatible = "samsung,exynos-bus"; 1059 clocks = <&clock CLK_DOUT_PCLK200_FSYS>; 1060 clock-names = "bus"; 1061 operating-points-v2 = <&bus_fsys_apb_opp_table>; 1062 status = "disabled"; 1063 }; 1064 1065 bus_fsys: bus_fsys { 1066 compatible = "samsung,exynos-bus"; 1067 clocks = <&clock CLK_DOUT_ACLK200_FSYS>; 1068 clock-names = "bus"; 1069 operating-points-v2 = <&bus_fsys_apb_opp_table>; 1070 status = "disabled"; 1071 }; 1072 1073 bus_fsys2: bus_fsys2 { 1074 compatible = "samsung,exynos-bus"; 1075 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; 1076 clock-names = "bus"; 1077 operating-points-v2 = <&bus_fsys2_opp_table>; 1078 status = "disabled"; 1079 }; 1080 1081 bus_mfc: bus_mfc { 1082 compatible = "samsung,exynos-bus"; 1083 clocks = <&clock CLK_DOUT_ACLK333>; 1084 clock-names = "bus"; 1085 operating-points-v2 = <&bus_mfc_opp_table>; 1086 status = "disabled"; 1087 }; 1088 1089 bus_gen: bus_gen { 1090 compatible = "samsung,exynos-bus"; 1091 clocks = <&clock CLK_DOUT_ACLK266>; 1092 clock-names = "bus"; 1093 operating-points-v2 = <&bus_gen_opp_table>; 1094 status = "disabled"; 1095 }; 1096 1097 bus_peri: bus_peri { 1098 compatible = "samsung,exynos-bus"; 1099 clocks = <&clock CLK_DOUT_ACLK66>; 1100 clock-names = "bus"; 1101 operating-points-v2 = <&bus_peri_opp_table>; 1102 status = "disabled"; 1103 }; 1104 1105 bus_g2d: bus_g2d { 1106 compatible = "samsung,exynos-bus"; 1107 clocks = <&clock CLK_DOUT_ACLK333_G2D>; 1108 clock-names = "bus"; 1109 operating-points-v2 = <&bus_g2d_opp_table>; 1110 status = "disabled"; 1111 }; 1112 1113 bus_g2d_acp: bus_g2d_acp { 1114 compatible = "samsung,exynos-bus"; 1115 clocks = <&clock CLK_DOUT_ACLK266_G2D>; 1116 clock-names = "bus"; 1117 operating-points-v2 = <&bus_g2d_acp_opp_table>; 1118 status = "disabled"; 1119 }; 1120 1121 bus_jpeg: bus_jpeg { 1122 compatible = "samsung,exynos-bus"; 1123 clocks = <&clock CLK_DOUT_ACLK300_JPEG>; 1124 clock-names = "bus"; 1125 operating-points-v2 = <&bus_jpeg_opp_table>; 1126 status = "disabled"; 1127 }; 1128 1129 bus_jpeg_apb: bus_jpeg_apb { 1130 compatible = "samsung,exynos-bus"; 1131 clocks = <&clock CLK_DOUT_ACLK166>; 1132 clock-names = "bus"; 1133 operating-points-v2 = <&bus_jpeg_apb_opp_table>; 1134 status = "disabled"; 1135 }; 1136 1137 bus_disp1_fimd: bus_disp1_fimd { 1138 compatible = "samsung,exynos-bus"; 1139 clocks = <&clock CLK_DOUT_ACLK300_DISP1>; 1140 clock-names = "bus"; 1141 operating-points-v2 = <&bus_disp1_fimd_opp_table>; 1142 status = "disabled"; 1143 }; 1144 1145 bus_disp1: bus_disp1 { 1146 compatible = "samsung,exynos-bus"; 1147 clocks = <&clock CLK_DOUT_ACLK400_DISP1>; 1148 clock-names = "bus"; 1149 operating-points-v2 = <&bus_disp1_opp_table>; 1150 status = "disabled"; 1151 }; 1152 1153 bus_gscl_scaler: bus_gscl_scaler { 1154 compatible = "samsung,exynos-bus"; 1155 clocks = <&clock CLK_DOUT_ACLK300_GSCL>; 1156 clock-names = "bus"; 1157 operating-points-v2 = <&bus_gscl_opp_table>; 1158 status = "disabled"; 1159 }; 1160 1161 bus_mscl: bus_mscl { 1162 compatible = "samsung,exynos-bus"; 1163 clocks = <&clock CLK_DOUT_ACLK400_MSCL>; 1164 clock-names = "bus"; 1165 operating-points-v2 = <&bus_mscl_opp_table>; 1166 status = "disabled"; 1167 }; 1168 1169 bus_wcore_opp_table: opp_table2 { 1170 compatible = "operating-points-v2"; 1171 1172 opp00 { 1173 opp-hz = /bits/ 64 <84000000>; 1174 opp-microvolt = <925000>; 1175 }; 1176 opp01 { 1177 opp-hz = /bits/ 64 <111000000>; 1178 opp-microvolt = <950000>; 1179 }; 1180 opp02 { 1181 opp-hz = /bits/ 64 <222000000>; 1182 opp-microvolt = <950000>; 1183 }; 1184 opp03 { 1185 opp-hz = /bits/ 64 <333000000>; 1186 opp-microvolt = <950000>; 1187 }; 1188 opp04 { 1189 opp-hz = /bits/ 64 <400000000>; 1190 opp-microvolt = <987500>; 1191 }; 1192 }; 1193 1194 bus_noc_opp_table: opp_table3 { 1195 compatible = "operating-points-v2"; 1196 1197 opp00 { 1198 opp-hz = /bits/ 64 <67000000>; 1199 }; 1200 opp01 { 1201 opp-hz = /bits/ 64 <75000000>; 1202 }; 1203 opp02 { 1204 opp-hz = /bits/ 64 <86000000>; 1205 }; 1206 opp03 { 1207 opp-hz = /bits/ 64 <100000000>; 1208 }; 1209 }; 1210 1211 bus_fsys_apb_opp_table: opp_table4 { 1212 compatible = "operating-points-v2"; 1213 opp-shared; 1214 1215 opp00 { 1216 opp-hz = /bits/ 64 <100000000>; 1217 }; 1218 opp01 { 1219 opp-hz = /bits/ 64 <200000000>; 1220 }; 1221 }; 1222 1223 bus_fsys2_opp_table: opp_table5 { 1224 compatible = "operating-points-v2"; 1225 1226 opp00 { 1227 opp-hz = /bits/ 64 <75000000>; 1228 }; 1229 opp01 { 1230 opp-hz = /bits/ 64 <100000000>; 1231 }; 1232 opp02 { 1233 opp-hz = /bits/ 64 <150000000>; 1234 }; 1235 }; 1236 1237 bus_mfc_opp_table: opp_table6 { 1238 compatible = "operating-points-v2"; 1239 1240 opp00 { 1241 opp-hz = /bits/ 64 <96000000>; 1242 }; 1243 opp01 { 1244 opp-hz = /bits/ 64 <111000000>; 1245 }; 1246 opp02 { 1247 opp-hz = /bits/ 64 <167000000>; 1248 }; 1249 opp03 { 1250 opp-hz = /bits/ 64 <222000000>; 1251 }; 1252 opp04 { 1253 opp-hz = /bits/ 64 <333000000>; 1254 }; 1255 }; 1256 1257 bus_gen_opp_table: opp_table7 { 1258 compatible = "operating-points-v2"; 1259 1260 opp00 { 1261 opp-hz = /bits/ 64 <89000000>; 1262 }; 1263 opp01 { 1264 opp-hz = /bits/ 64 <133000000>; 1265 }; 1266 opp02 { 1267 opp-hz = /bits/ 64 <178000000>; 1268 }; 1269 opp03 { 1270 opp-hz = /bits/ 64 <267000000>; 1271 }; 1272 }; 1273 1274 bus_peri_opp_table: opp_table8 { 1275 compatible = "operating-points-v2"; 1276 1277 opp00 { 1278 opp-hz = /bits/ 64 <67000000>; 1279 }; 1280 }; 1281 1282 bus_g2d_opp_table: opp_table9 { 1283 compatible = "operating-points-v2"; 1284 1285 opp00 { 1286 opp-hz = /bits/ 64 <84000000>; 1287 }; 1288 opp01 { 1289 opp-hz = /bits/ 64 <167000000>; 1290 }; 1291 opp02 { 1292 opp-hz = /bits/ 64 <222000000>; 1293 }; 1294 opp03 { 1295 opp-hz = /bits/ 64 <300000000>; 1296 }; 1297 opp04 { 1298 opp-hz = /bits/ 64 <333000000>; 1299 }; 1300 }; 1301 1302 bus_g2d_acp_opp_table: opp_table10 { 1303 compatible = "operating-points-v2"; 1304 1305 opp00 { 1306 opp-hz = /bits/ 64 <67000000>; 1307 }; 1308 opp01 { 1309 opp-hz = /bits/ 64 <133000000>; 1310 }; 1311 opp02 { 1312 opp-hz = /bits/ 64 <178000000>; 1313 }; 1314 opp03 { 1315 opp-hz = /bits/ 64 <267000000>; 1316 }; 1317 }; 1318 1319 bus_jpeg_opp_table: opp_table11 { 1320 compatible = "operating-points-v2"; 1321 1322 opp00 { 1323 opp-hz = /bits/ 64 <75000000>; 1324 }; 1325 opp01 { 1326 opp-hz = /bits/ 64 <150000000>; 1327 }; 1328 opp02 { 1329 opp-hz = /bits/ 64 <200000000>; 1330 }; 1331 opp03 { 1332 opp-hz = /bits/ 64 <300000000>; 1333 }; 1334 }; 1335 1336 bus_jpeg_apb_opp_table: opp_table12 { 1337 compatible = "operating-points-v2"; 1338 1339 opp00 { 1340 opp-hz = /bits/ 64 <84000000>; 1341 }; 1342 opp01 { 1343 opp-hz = /bits/ 64 <111000000>; 1344 }; 1345 opp02 { 1346 opp-hz = /bits/ 64 <134000000>; 1347 }; 1348 opp03 { 1349 opp-hz = /bits/ 64 <167000000>; 1350 }; 1351 }; 1352 1353 bus_disp1_fimd_opp_table: opp_table13 { 1354 compatible = "operating-points-v2"; 1355 1356 opp00 { 1357 opp-hz = /bits/ 64 <120000000>; 1358 }; 1359 opp01 { 1360 opp-hz = /bits/ 64 <200000000>; 1361 }; 1362 }; 1363 1364 bus_disp1_opp_table: opp_table14 { 1365 compatible = "operating-points-v2"; 1366 1367 opp00 { 1368 opp-hz = /bits/ 64 <120000000>; 1369 }; 1370 opp01 { 1371 opp-hz = /bits/ 64 <200000000>; 1372 }; 1373 opp02 { 1374 opp-hz = /bits/ 64 <300000000>; 1375 }; 1376 }; 1377 1378 bus_gscl_opp_table: opp_table15 { 1379 compatible = "operating-points-v2"; 1380 1381 opp00 { 1382 opp-hz = /bits/ 64 <150000000>; 1383 }; 1384 opp01 { 1385 opp-hz = /bits/ 64 <200000000>; 1386 }; 1387 opp02 { 1388 opp-hz = /bits/ 64 <300000000>; 1389 }; 1390 }; 1391 1392 bus_mscl_opp_table: opp_table16 { 1393 compatible = "operating-points-v2"; 1394 1395 opp00 { 1396 opp-hz = /bits/ 64 <84000000>; 1397 }; 1398 opp01 { 1399 opp-hz = /bits/ 64 <167000000>; 1400 }; 1401 opp02 { 1402 opp-hz = /bits/ 64 <222000000>; 1403 }; 1404 opp03 { 1405 opp-hz = /bits/ 64 <333000000>; 1406 }; 1407 opp04 { 1408 opp-hz = /bits/ 64 <400000000>; 1409 }; 1410 }; 1411 }; 1412 1413 thermal-zones { 1414 cpu0_thermal: cpu0-thermal { 1415 thermal-sensors = <&tmu_cpu0>; 1416 #include "exynos5420-trip-points.dtsi" 1417 }; 1418 cpu1_thermal: cpu1-thermal { 1419 thermal-sensors = <&tmu_cpu1>; 1420 #include "exynos5420-trip-points.dtsi" 1421 }; 1422 cpu2_thermal: cpu2-thermal { 1423 thermal-sensors = <&tmu_cpu2>; 1424 #include "exynos5420-trip-points.dtsi" 1425 }; 1426 cpu3_thermal: cpu3-thermal { 1427 thermal-sensors = <&tmu_cpu3>; 1428 #include "exynos5420-trip-points.dtsi" 1429 }; 1430 gpu_thermal: gpu-thermal { 1431 thermal-sensors = <&tmu_gpu>; 1432 #include "exynos5420-trip-points.dtsi" 1433 }; 1434 }; 1435}; 1436 1437&adc { 1438 clocks = <&clock CLK_TSADC>; 1439 clock-names = "adc"; 1440 samsung,syscon-phandle = <&pmu_system_controller>; 1441}; 1442 1443&dp { 1444 clocks = <&clock CLK_DP1>; 1445 clock-names = "dp"; 1446 phys = <&dp_phy>; 1447 phy-names = "dp"; 1448 power-domains = <&disp_pd>; 1449}; 1450 1451&fimd { 1452 compatible = "samsung,exynos5420-fimd"; 1453 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1454 clock-names = "sclk_fimd", "fimd"; 1455 power-domains = <&disp_pd>; 1456 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; 1457 iommu-names = "m0", "m1"; 1458}; 1459 1460&g2d { 1461 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; 1462 clocks = <&clock CLK_G2D>; 1463 clock-names = "fimg2d"; 1464 status = "okay"; 1465}; 1466 1467&i2c_0 { 1468 clocks = <&clock CLK_I2C0>; 1469 clock-names = "i2c"; 1470 pinctrl-names = "default"; 1471 pinctrl-0 = <&i2c0_bus>; 1472}; 1473 1474&i2c_1 { 1475 clocks = <&clock CLK_I2C1>; 1476 clock-names = "i2c"; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&i2c1_bus>; 1479}; 1480 1481&i2c_2 { 1482 clocks = <&clock CLK_I2C2>; 1483 clock-names = "i2c"; 1484 pinctrl-names = "default"; 1485 pinctrl-0 = <&i2c2_bus>; 1486}; 1487 1488&i2c_3 { 1489 clocks = <&clock CLK_I2C3>; 1490 clock-names = "i2c"; 1491 pinctrl-names = "default"; 1492 pinctrl-0 = <&i2c3_bus>; 1493}; 1494 1495&hsi2c_4 { 1496 clocks = <&clock CLK_USI0>; 1497 clock-names = "hsi2c"; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&i2c4_hs_bus>; 1500}; 1501 1502&hsi2c_5 { 1503 clocks = <&clock CLK_USI1>; 1504 clock-names = "hsi2c"; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&i2c5_hs_bus>; 1507}; 1508 1509&hsi2c_6 { 1510 clocks = <&clock CLK_USI2>; 1511 clock-names = "hsi2c"; 1512 pinctrl-names = "default"; 1513 pinctrl-0 = <&i2c6_hs_bus>; 1514}; 1515 1516&hsi2c_7 { 1517 clocks = <&clock CLK_USI3>; 1518 clock-names = "hsi2c"; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&i2c7_hs_bus>; 1521}; 1522 1523&mct { 1524 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 1525 clock-names = "fin_pll", "mct"; 1526}; 1527 1528&prng { 1529 clocks = <&clock CLK_SSS>; 1530 clock-names = "secss"; 1531}; 1532 1533&pwm { 1534 clocks = <&clock CLK_PWM>; 1535 clock-names = "timers"; 1536}; 1537 1538&rtc { 1539 clocks = <&clock CLK_RTC>; 1540 clock-names = "rtc"; 1541 interrupt-parent = <&pmu_system_controller>; 1542 status = "disabled"; 1543}; 1544 1545&serial_0 { 1546 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1547 clock-names = "uart", "clk_uart_baud0"; 1548 dmas = <&pdma0 13>, <&pdma0 14>; 1549 dma-names = "rx", "tx"; 1550}; 1551 1552&serial_1 { 1553 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1554 clock-names = "uart", "clk_uart_baud0"; 1555 dmas = <&pdma1 15>, <&pdma1 16>; 1556 dma-names = "rx", "tx"; 1557}; 1558 1559&serial_2 { 1560 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1561 clock-names = "uart", "clk_uart_baud0"; 1562 dmas = <&pdma0 15>, <&pdma0 16>; 1563 dma-names = "rx", "tx"; 1564}; 1565 1566&serial_3 { 1567 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1568 clock-names = "uart", "clk_uart_baud0"; 1569 dmas = <&pdma1 17>, <&pdma1 18>; 1570 dma-names = "rx", "tx"; 1571}; 1572 1573&sss { 1574 clocks = <&clock CLK_SSS>; 1575 clock-names = "secss"; 1576}; 1577 1578&trng { 1579 clocks = <&clock CLK_SSS>; 1580 clock-names = "secss"; 1581}; 1582 1583&usbdrd3_0 { 1584 clocks = <&clock CLK_USBD300>; 1585 clock-names = "usbdrd30"; 1586}; 1587 1588&usbdrd_phy0 { 1589 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 1590 clock-names = "phy", "ref"; 1591 samsung,pmu-syscon = <&pmu_system_controller>; 1592}; 1593 1594&usbdrd3_1 { 1595 clocks = <&clock CLK_USBD301>; 1596 clock-names = "usbdrd30"; 1597}; 1598 1599&usbdrd_dwc3_1 { 1600 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1601}; 1602 1603&usbdrd_phy1 { 1604 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 1605 clock-names = "phy", "ref"; 1606 samsung,pmu-syscon = <&pmu_system_controller>; 1607}; 1608 1609&usbhost1 { 1610 clocks = <&clock CLK_USBH20>; 1611 clock-names = "usbhost"; 1612}; 1613 1614&usbhost2 { 1615 clocks = <&clock CLK_USBH20>; 1616 clock-names = "usbhost"; 1617}; 1618 1619&usb2_phy { 1620 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 1621 clock-names = "phy", "ref"; 1622 samsung,sysreg-phandle = <&sysreg_system_controller>; 1623 samsung,pmureg-phandle = <&pmu_system_controller>; 1624}; 1625 1626&watchdog { 1627 clocks = <&clock CLK_WDT>; 1628 clock-names = "watchdog"; 1629 samsung,syscon-phandle = <&pmu_system_controller>; 1630}; 1631 1632#include "exynos5420-pinctrl.dtsi" 1633#include "exynos-syscon-restart.dtsi" 1634