1/* 2 * SAMSUNG EXYNOS5420 SoC device tree source 3 * 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. 8 * EXYNOS5420 based board files can include this file and provide 9 * values for board specfic bindings. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include "exynos54xx.dtsi" 17#include <dt-bindings/clock/exynos5420.h> 18#include <dt-bindings/clock/exynos-audss-clk.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20 21/ { 22 compatible = "samsung,exynos5420", "samsung,exynos5"; 23 24 aliases { 25 mshc0 = &mmc_0; 26 mshc1 = &mmc_1; 27 mshc2 = &mmc_2; 28 pinctrl0 = &pinctrl_0; 29 pinctrl1 = &pinctrl_1; 30 pinctrl2 = &pinctrl_2; 31 pinctrl3 = &pinctrl_3; 32 pinctrl4 = &pinctrl_4; 33 i2c8 = &hsi2c_8; 34 i2c9 = &hsi2c_9; 35 i2c10 = &hsi2c_10; 36 gsc0 = &gsc_0; 37 gsc1 = &gsc_1; 38 spi0 = &spi_0; 39 spi1 = &spi_1; 40 spi2 = &spi_2; 41 }; 42 43 /* 44 * The 'cpus' node is not present here but instead it is provided 45 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. 46 */ 47 48 soc: soc { 49 cluster_a15_opp_table: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 opp-1800000000 { 53 opp-hz = /bits/ 64 <1800000000>; 54 opp-microvolt = <1250000>; 55 clock-latency-ns = <140000>; 56 }; 57 opp-1700000000 { 58 opp-hz = /bits/ 64 <1700000000>; 59 opp-microvolt = <1212500>; 60 clock-latency-ns = <140000>; 61 }; 62 opp-1600000000 { 63 opp-hz = /bits/ 64 <1600000000>; 64 opp-microvolt = <1175000>; 65 clock-latency-ns = <140000>; 66 }; 67 opp-1500000000 { 68 opp-hz = /bits/ 64 <1500000000>; 69 opp-microvolt = <1137500>; 70 clock-latency-ns = <140000>; 71 }; 72 opp-1400000000 { 73 opp-hz = /bits/ 64 <1400000000>; 74 opp-microvolt = <1112500>; 75 clock-latency-ns = <140000>; 76 }; 77 opp-1300000000 { 78 opp-hz = /bits/ 64 <1300000000>; 79 opp-microvolt = <1062500>; 80 clock-latency-ns = <140000>; 81 }; 82 opp-1200000000 { 83 opp-hz = /bits/ 64 <1200000000>; 84 opp-microvolt = <1037500>; 85 clock-latency-ns = <140000>; 86 }; 87 opp-1100000000 { 88 opp-hz = /bits/ 64 <1100000000>; 89 opp-microvolt = <1012500>; 90 clock-latency-ns = <140000>; 91 }; 92 opp-1000000000 { 93 opp-hz = /bits/ 64 <1000000000>; 94 opp-microvolt = < 987500>; 95 clock-latency-ns = <140000>; 96 }; 97 opp-900000000 { 98 opp-hz = /bits/ 64 <900000000>; 99 opp-microvolt = < 962500>; 100 clock-latency-ns = <140000>; 101 }; 102 opp-800000000 { 103 opp-hz = /bits/ 64 <800000000>; 104 opp-microvolt = < 937500>; 105 clock-latency-ns = <140000>; 106 }; 107 opp-700000000 { 108 opp-hz = /bits/ 64 <700000000>; 109 opp-microvolt = < 912500>; 110 clock-latency-ns = <140000>; 111 }; 112 }; 113 114 cluster_a7_opp_table: opp_table1 { 115 compatible = "operating-points-v2"; 116 opp-shared; 117 opp-1300000000 { 118 opp-hz = /bits/ 64 <1300000000>; 119 opp-microvolt = <1275000>; 120 clock-latency-ns = <140000>; 121 }; 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <1212500>; 125 clock-latency-ns = <140000>; 126 }; 127 opp-1100000000 { 128 opp-hz = /bits/ 64 <1100000000>; 129 opp-microvolt = <1162500>; 130 clock-latency-ns = <140000>; 131 }; 132 opp-1000000000 { 133 opp-hz = /bits/ 64 <1000000000>; 134 opp-microvolt = <1112500>; 135 clock-latency-ns = <140000>; 136 }; 137 opp-900000000 { 138 opp-hz = /bits/ 64 <900000000>; 139 opp-microvolt = <1062500>; 140 clock-latency-ns = <140000>; 141 }; 142 opp-800000000 { 143 opp-hz = /bits/ 64 <800000000>; 144 opp-microvolt = <1025000>; 145 clock-latency-ns = <140000>; 146 }; 147 opp-700000000 { 148 opp-hz = /bits/ 64 <700000000>; 149 opp-microvolt = <975000>; 150 clock-latency-ns = <140000>; 151 }; 152 opp-600000000 { 153 opp-hz = /bits/ 64 <600000000>; 154 opp-microvolt = <937500>; 155 clock-latency-ns = <140000>; 156 }; 157 }; 158 159 cci: cci@10d20000 { 160 compatible = "arm,cci-400"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 reg = <0x10d20000 0x1000>; 164 ranges = <0x0 0x10d20000 0x6000>; 165 166 cci_control0: slave-if@4000 { 167 compatible = "arm,cci-400-ctrl-if"; 168 interface-type = "ace"; 169 reg = <0x4000 0x1000>; 170 }; 171 cci_control1: slave-if@5000 { 172 compatible = "arm,cci-400-ctrl-if"; 173 interface-type = "ace"; 174 reg = <0x5000 0x1000>; 175 }; 176 }; 177 178 clock: clock-controller@10010000 { 179 compatible = "samsung,exynos5420-clock"; 180 reg = <0x10010000 0x30000>; 181 #clock-cells = <1>; 182 }; 183 184 clock_audss: audss-clock-controller@3810000 { 185 compatible = "samsung,exynos5420-audss-clock"; 186 reg = <0x03810000 0x0C>; 187 #clock-cells = <1>; 188 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 189 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 190 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 191 }; 192 193 mfc: codec@11000000 { 194 compatible = "samsung,mfc-v7"; 195 reg = <0x11000000 0x10000>; 196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clock CLK_MFC>; 198 clock-names = "mfc"; 199 power-domains = <&mfc_pd>; 200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 201 iommu-names = "left", "right"; 202 }; 203 204 mmc_0: mmc@12200000 { 205 compatible = "samsung,exynos5420-dw-mshc-smu"; 206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 reg = <0x12200000 0x2000>; 210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 211 clock-names = "biu", "ciu"; 212 fifo-depth = <0x40>; 213 status = "disabled"; 214 }; 215 216 mmc_1: mmc@12210000 { 217 compatible = "samsung,exynos5420-dw-mshc-smu"; 218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x12210000 0x2000>; 222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 223 clock-names = "biu", "ciu"; 224 fifo-depth = <0x40>; 225 status = "disabled"; 226 }; 227 228 mmc_2: mmc@12220000 { 229 compatible = "samsung,exynos5420-dw-mshc"; 230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <0x12220000 0x1000>; 234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 235 clock-names = "biu", "ciu"; 236 fifo-depth = <0x40>; 237 status = "disabled"; 238 }; 239 240 nocp_mem0_0: nocp@10CA1000 { 241 compatible = "samsung,exynos5420-nocp"; 242 reg = <0x10CA1000 0x200>; 243 status = "disabled"; 244 }; 245 246 nocp_mem0_1: nocp@10CA1400 { 247 compatible = "samsung,exynos5420-nocp"; 248 reg = <0x10CA1400 0x200>; 249 status = "disabled"; 250 }; 251 252 nocp_mem1_0: nocp@10CA1800 { 253 compatible = "samsung,exynos5420-nocp"; 254 reg = <0x10CA1800 0x200>; 255 status = "disabled"; 256 }; 257 258 nocp_mem1_1: nocp@10CA1C00 { 259 compatible = "samsung,exynos5420-nocp"; 260 reg = <0x10CA1C00 0x200>; 261 status = "disabled"; 262 }; 263 264 nocp_g3d_0: nocp@11A51000 { 265 compatible = "samsung,exynos5420-nocp"; 266 reg = <0x11A51000 0x200>; 267 status = "disabled"; 268 }; 269 270 nocp_g3d_1: nocp@11A51400 { 271 compatible = "samsung,exynos5420-nocp"; 272 reg = <0x11A51400 0x200>; 273 status = "disabled"; 274 }; 275 276 gsc_pd: power-domain@10044000 { 277 compatible = "samsung,exynos4210-pd"; 278 reg = <0x10044000 0x20>; 279 #power-domain-cells = <0>; 280 label = "GSC"; 281 clocks = <&clock CLK_FIN_PLL>, 282 <&clock CLK_MOUT_USER_ACLK300_GSCL>, 283 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; 284 clock-names = "oscclk", "clk0", "asb0", "asb1"; 285 }; 286 287 isp_pd: power-domain@10044020 { 288 compatible = "samsung,exynos4210-pd"; 289 reg = <0x10044020 0x20>; 290 #power-domain-cells = <0>; 291 label = "ISP"; 292 }; 293 294 mfc_pd: power-domain@10044060 { 295 compatible = "samsung,exynos4210-pd"; 296 reg = <0x10044060 0x20>; 297 clocks = <&clock CLK_FIN_PLL>, 298 <&clock CLK_MOUT_USER_ACLK333>, 299 <&clock CLK_ACLK333>; 300 clock-names = "oscclk", "clk0","asb0"; 301 #power-domain-cells = <0>; 302 label = "MFC"; 303 }; 304 305 msc_pd: power-domain@10044120 { 306 compatible = "samsung,exynos4210-pd"; 307 reg = <0x10044120 0x20>; 308 #power-domain-cells = <0>; 309 label = "MSC"; 310 }; 311 312 disp_pd: power-domain@100440C0 { 313 compatible = "samsung,exynos4210-pd"; 314 reg = <0x100440C0 0x20>; 315 #power-domain-cells = <0>; 316 label = "DISP"; 317 clocks = <&clock CLK_FIN_PLL>, 318 <&clock CLK_MOUT_USER_ACLK200_DISP1>, 319 <&clock CLK_MOUT_USER_ACLK300_DISP1>, 320 <&clock CLK_MOUT_USER_ACLK400_DISP1>, 321 <&clock CLK_FIMD1>, <&clock CLK_MIXER>; 322 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; 323 }; 324 325 pinctrl_0: pinctrl@13400000 { 326 compatible = "samsung,exynos5420-pinctrl"; 327 reg = <0x13400000 0x1000>; 328 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 329 330 wakeup-interrupt-controller { 331 compatible = "samsung,exynos4210-wakeup-eint"; 332 interrupt-parent = <&gic>; 333 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 }; 336 337 pinctrl_1: pinctrl@13410000 { 338 compatible = "samsung,exynos5420-pinctrl"; 339 reg = <0x13410000 0x1000>; 340 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 341 }; 342 343 pinctrl_2: pinctrl@14000000 { 344 compatible = "samsung,exynos5420-pinctrl"; 345 reg = <0x14000000 0x1000>; 346 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 347 }; 348 349 pinctrl_3: pinctrl@14010000 { 350 compatible = "samsung,exynos5420-pinctrl"; 351 reg = <0x14010000 0x1000>; 352 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 353 }; 354 355 pinctrl_4: pinctrl@3860000 { 356 compatible = "samsung,exynos5420-pinctrl"; 357 reg = <0x03860000 0x1000>; 358 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 359 }; 360 361 amba { 362 #address-cells = <1>; 363 #size-cells = <1>; 364 compatible = "simple-bus"; 365 interrupt-parent = <&gic>; 366 ranges; 367 368 adma: adma@3880000 { 369 compatible = "arm,pl330", "arm,primecell"; 370 reg = <0x03880000 0x1000>; 371 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clock_audss EXYNOS_ADMA>; 373 clock-names = "apb_pclk"; 374 #dma-cells = <1>; 375 #dma-channels = <6>; 376 #dma-requests = <16>; 377 }; 378 379 pdma0: pdma@121A0000 { 380 compatible = "arm,pl330", "arm,primecell"; 381 reg = <0x121A0000 0x1000>; 382 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&clock CLK_PDMA0>; 384 clock-names = "apb_pclk"; 385 #dma-cells = <1>; 386 #dma-channels = <8>; 387 #dma-requests = <32>; 388 }; 389 390 pdma1: pdma@121B0000 { 391 compatible = "arm,pl330", "arm,primecell"; 392 reg = <0x121B0000 0x1000>; 393 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&clock CLK_PDMA1>; 395 clock-names = "apb_pclk"; 396 #dma-cells = <1>; 397 #dma-channels = <8>; 398 #dma-requests = <32>; 399 }; 400 401 mdma0: mdma@10800000 { 402 compatible = "arm,pl330", "arm,primecell"; 403 reg = <0x10800000 0x1000>; 404 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&clock CLK_MDMA0>; 406 clock-names = "apb_pclk"; 407 #dma-cells = <1>; 408 #dma-channels = <8>; 409 #dma-requests = <1>; 410 }; 411 412 mdma1: mdma@11C10000 { 413 compatible = "arm,pl330", "arm,primecell"; 414 reg = <0x11C10000 0x1000>; 415 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clock CLK_MDMA1>; 417 clock-names = "apb_pclk"; 418 #dma-cells = <1>; 419 #dma-channels = <8>; 420 #dma-requests = <1>; 421 /* 422 * MDMA1 can support both secure and non-secure 423 * AXI transactions. When this is enabled in 424 * the kernel for boards that run in secure 425 * mode, we are getting imprecise external 426 * aborts causing the kernel to oops. 427 */ 428 status = "disabled"; 429 }; 430 }; 431 432 i2s0: i2s@3830000 { 433 compatible = "samsung,exynos5420-i2s"; 434 reg = <0x03830000 0x100>; 435 dmas = <&adma 0 436 &adma 2 437 &adma 1>; 438 dma-names = "tx", "rx", "tx-sec"; 439 clocks = <&clock_audss EXYNOS_I2S_BUS>, 440 <&clock_audss EXYNOS_I2S_BUS>, 441 <&clock_audss EXYNOS_SCLK_I2S>; 442 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 443 #clock-cells = <1>; 444 clock-output-names = "i2s_cdclk0"; 445 #sound-dai-cells = <1>; 446 samsung,idma-addr = <0x03000000>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&i2s0_bus>; 449 status = "disabled"; 450 }; 451 452 i2s1: i2s@12D60000 { 453 compatible = "samsung,exynos5420-i2s"; 454 reg = <0x12D60000 0x100>; 455 dmas = <&pdma1 12 456 &pdma1 11>; 457 dma-names = "tx", "rx"; 458 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; 459 clock-names = "iis", "i2s_opclk0"; 460 #clock-cells = <1>; 461 clock-output-names = "i2s_cdclk1"; 462 #sound-dai-cells = <1>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&i2s1_bus>; 465 status = "disabled"; 466 }; 467 468 i2s2: i2s@12D70000 { 469 compatible = "samsung,exynos5420-i2s"; 470 reg = <0x12D70000 0x100>; 471 dmas = <&pdma0 12 472 &pdma0 11>; 473 dma-names = "tx", "rx"; 474 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; 475 clock-names = "iis", "i2s_opclk0"; 476 #clock-cells = <1>; 477 clock-output-names = "i2s_cdclk2"; 478 #sound-dai-cells = <1>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&i2s2_bus>; 481 status = "disabled"; 482 }; 483 484 spi_0: spi@12d20000 { 485 compatible = "samsung,exynos4210-spi"; 486 reg = <0x12d20000 0x100>; 487 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 488 dmas = <&pdma0 5 489 &pdma0 4>; 490 dma-names = "tx", "rx"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&spi0_bus>; 495 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 496 clock-names = "spi", "spi_busclk0"; 497 status = "disabled"; 498 }; 499 500 spi_1: spi@12d30000 { 501 compatible = "samsung,exynos4210-spi"; 502 reg = <0x12d30000 0x100>; 503 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 504 dmas = <&pdma1 5 505 &pdma1 4>; 506 dma-names = "tx", "rx"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&spi1_bus>; 511 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 512 clock-names = "spi", "spi_busclk0"; 513 status = "disabled"; 514 }; 515 516 spi_2: spi@12d40000 { 517 compatible = "samsung,exynos4210-spi"; 518 reg = <0x12d40000 0x100>; 519 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 520 dmas = <&pdma0 7 521 &pdma0 6>; 522 dma-names = "tx", "rx"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&spi2_bus>; 527 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 528 clock-names = "spi", "spi_busclk0"; 529 status = "disabled"; 530 }; 531 532 dp_phy: dp-video-phy { 533 compatible = "samsung,exynos5420-dp-video-phy"; 534 samsung,pmu-syscon = <&pmu_system_controller>; 535 #phy-cells = <0>; 536 }; 537 538 mipi_phy: mipi-video-phy { 539 compatible = "samsung,s5pv210-mipi-video-phy"; 540 syscon = <&pmu_system_controller>; 541 #phy-cells = <1>; 542 }; 543 544 dsi@14500000 { 545 compatible = "samsung,exynos5410-mipi-dsi"; 546 reg = <0x14500000 0x10000>; 547 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 548 phys = <&mipi_phy 1>; 549 phy-names = "dsim"; 550 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; 551 clock-names = "bus_clk", "pll_clk"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 adc: adc@12D10000 { 558 compatible = "samsung,exynos-adc-v2"; 559 reg = <0x12D10000 0x100>; 560 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&clock CLK_TSADC>; 562 clock-names = "adc"; 563 #io-channel-cells = <1>; 564 io-channel-ranges; 565 samsung,syscon-phandle = <&pmu_system_controller>; 566 status = "disabled"; 567 }; 568 569 hsi2c_8: i2c@12E00000 { 570 compatible = "samsung,exynos5250-hsi2c"; 571 reg = <0x12E00000 0x1000>; 572 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&i2c8_hs_bus>; 577 clocks = <&clock CLK_USI4>; 578 clock-names = "hsi2c"; 579 status = "disabled"; 580 }; 581 582 hsi2c_9: i2c@12E10000 { 583 compatible = "samsung,exynos5250-hsi2c"; 584 reg = <0x12E10000 0x1000>; 585 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&i2c9_hs_bus>; 590 clocks = <&clock CLK_USI5>; 591 clock-names = "hsi2c"; 592 status = "disabled"; 593 }; 594 595 hsi2c_10: i2c@12E20000 { 596 compatible = "samsung,exynos5250-hsi2c"; 597 reg = <0x12E20000 0x1000>; 598 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&i2c10_hs_bus>; 603 clocks = <&clock CLK_USI6>; 604 clock-names = "hsi2c"; 605 status = "disabled"; 606 }; 607 608 hdmi: hdmi@14530000 { 609 compatible = "samsung,exynos5420-hdmi"; 610 reg = <0x14530000 0x70000>; 611 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 613 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 614 <&clock CLK_MOUT_HDMI>; 615 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 616 "sclk_hdmiphy", "mout_hdmi"; 617 phy = <&hdmiphy>; 618 samsung,syscon-phandle = <&pmu_system_controller>; 619 status = "disabled"; 620 power-domains = <&disp_pd>; 621 }; 622 623 hdmiphy: hdmiphy@145D0000 { 624 reg = <0x145D0000 0x20>; 625 }; 626 627 hdmicec: cec@101B0000 { 628 compatible = "samsung,s5p-cec"; 629 reg = <0x101B0000 0x200>; 630 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clock CLK_HDMI_CEC>; 632 clock-names = "hdmicec"; 633 samsung,syscon-phandle = <&pmu_system_controller>; 634 hdmi-phandle = <&hdmi>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&hdmi_cec>; 637 status = "disabled"; 638 }; 639 640 mixer: mixer@14450000 { 641 compatible = "samsung,exynos5420-mixer"; 642 reg = <0x14450000 0x10000>; 643 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 645 <&clock CLK_SCLK_HDMI>; 646 clock-names = "mixer", "hdmi", "sclk_hdmi"; 647 power-domains = <&disp_pd>; 648 iommus = <&sysmmu_tv>; 649 status = "disabled"; 650 }; 651 652 rotator: rotator@11C00000 { 653 compatible = "samsung,exynos5250-rotator"; 654 reg = <0x11C00000 0x64>; 655 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clock CLK_ROTATOR>; 657 clock-names = "rotator"; 658 iommus = <&sysmmu_rotator>; 659 }; 660 661 gsc_0: video-scaler@13e00000 { 662 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 663 reg = <0x13e00000 0x1000>; 664 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&clock CLK_GSCL0>; 666 clock-names = "gscl"; 667 power-domains = <&gsc_pd>; 668 iommus = <&sysmmu_gscl0>; 669 }; 670 671 gsc_1: video-scaler@13e10000 { 672 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 673 reg = <0x13e10000 0x1000>; 674 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&clock CLK_GSCL1>; 676 clock-names = "gscl"; 677 power-domains = <&gsc_pd>; 678 iommus = <&sysmmu_gscl1>; 679 }; 680 681 jpeg_0: jpeg@11F50000 { 682 compatible = "samsung,exynos5420-jpeg"; 683 reg = <0x11F50000 0x1000>; 684 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 685 clock-names = "jpeg"; 686 clocks = <&clock CLK_JPEG>; 687 iommus = <&sysmmu_jpeg0>; 688 }; 689 690 jpeg_1: jpeg@11F60000 { 691 compatible = "samsung,exynos5420-jpeg"; 692 reg = <0x11F60000 0x1000>; 693 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 694 clock-names = "jpeg"; 695 clocks = <&clock CLK_JPEG2>; 696 iommus = <&sysmmu_jpeg1>; 697 }; 698 699 pmu_system_controller: system-controller@10040000 { 700 compatible = "samsung,exynos5420-pmu", "syscon"; 701 reg = <0x10040000 0x5000>; 702 clock-names = "clkout16"; 703 clocks = <&clock CLK_FIN_PLL>; 704 #clock-cells = <1>; 705 interrupt-controller; 706 #interrupt-cells = <3>; 707 interrupt-parent = <&gic>; 708 }; 709 710 tmu_cpu0: tmu@10060000 { 711 compatible = "samsung,exynos5420-tmu"; 712 reg = <0x10060000 0x100>; 713 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clock CLK_TMU>; 715 clock-names = "tmu_apbif"; 716 #include "exynos5420-tmu-sensor-conf.dtsi" 717 }; 718 719 tmu_cpu1: tmu@10064000 { 720 compatible = "samsung,exynos5420-tmu"; 721 reg = <0x10064000 0x100>; 722 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&clock CLK_TMU>; 724 clock-names = "tmu_apbif"; 725 #include "exynos5420-tmu-sensor-conf.dtsi" 726 }; 727 728 tmu_cpu2: tmu@10068000 { 729 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 730 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 731 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 733 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 734 #include "exynos5420-tmu-sensor-conf.dtsi" 735 }; 736 737 tmu_cpu3: tmu@1006c000 { 738 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 739 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 740 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 742 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 743 #include "exynos5420-tmu-sensor-conf.dtsi" 744 }; 745 746 tmu_gpu: tmu@100a0000 { 747 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 748 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 749 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 751 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 752 #include "exynos5420-tmu-sensor-conf.dtsi" 753 }; 754 755 sysmmu_g2dr: sysmmu@0x10A60000 { 756 compatible = "samsung,exynos-sysmmu"; 757 reg = <0x10A60000 0x1000>; 758 interrupt-parent = <&combiner>; 759 interrupts = <24 5>; 760 clock-names = "sysmmu", "master"; 761 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 762 #iommu-cells = <0>; 763 }; 764 765 sysmmu_g2dw: sysmmu@0x10A70000 { 766 compatible = "samsung,exynos-sysmmu"; 767 reg = <0x10A70000 0x1000>; 768 interrupt-parent = <&combiner>; 769 interrupts = <22 2>; 770 clock-names = "sysmmu", "master"; 771 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 772 #iommu-cells = <0>; 773 }; 774 775 sysmmu_tv: sysmmu@0x14650000 { 776 compatible = "samsung,exynos-sysmmu"; 777 reg = <0x14650000 0x1000>; 778 interrupt-parent = <&combiner>; 779 interrupts = <7 4>; 780 clock-names = "sysmmu", "master"; 781 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; 782 power-domains = <&disp_pd>; 783 #iommu-cells = <0>; 784 }; 785 786 sysmmu_gscl0: sysmmu@0x13E80000 { 787 compatible = "samsung,exynos-sysmmu"; 788 reg = <0x13E80000 0x1000>; 789 interrupt-parent = <&combiner>; 790 interrupts = <2 0>; 791 clock-names = "sysmmu", "master"; 792 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 793 power-domains = <&gsc_pd>; 794 #iommu-cells = <0>; 795 }; 796 797 sysmmu_gscl1: sysmmu@0x13E90000 { 798 compatible = "samsung,exynos-sysmmu"; 799 reg = <0x13E90000 0x1000>; 800 interrupt-parent = <&combiner>; 801 interrupts = <2 2>; 802 clock-names = "sysmmu", "master"; 803 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 804 power-domains = <&gsc_pd>; 805 #iommu-cells = <0>; 806 }; 807 808 sysmmu_scaler0r: sysmmu@0x12880000 { 809 compatible = "samsung,exynos-sysmmu"; 810 reg = <0x12880000 0x1000>; 811 interrupt-parent = <&combiner>; 812 interrupts = <22 4>; 813 clock-names = "sysmmu", "master"; 814 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 815 #iommu-cells = <0>; 816 }; 817 818 sysmmu_scaler1r: sysmmu@0x12890000 { 819 compatible = "samsung,exynos-sysmmu"; 820 reg = <0x12890000 0x1000>; 821 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 822 clock-names = "sysmmu", "master"; 823 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 824 #iommu-cells = <0>; 825 }; 826 827 sysmmu_scaler2r: sysmmu@0x128A0000 { 828 compatible = "samsung,exynos-sysmmu"; 829 reg = <0x128A0000 0x1000>; 830 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 831 clock-names = "sysmmu", "master"; 832 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 833 #iommu-cells = <0>; 834 }; 835 836 sysmmu_scaler0w: sysmmu@0x128C0000 { 837 compatible = "samsung,exynos-sysmmu"; 838 reg = <0x128C0000 0x1000>; 839 interrupt-parent = <&combiner>; 840 interrupts = <27 2>; 841 clock-names = "sysmmu", "master"; 842 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 843 #iommu-cells = <0>; 844 }; 845 846 sysmmu_scaler1w: sysmmu@0x128D0000 { 847 compatible = "samsung,exynos-sysmmu"; 848 reg = <0x128D0000 0x1000>; 849 interrupt-parent = <&combiner>; 850 interrupts = <22 6>; 851 clock-names = "sysmmu", "master"; 852 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 853 #iommu-cells = <0>; 854 }; 855 856 sysmmu_scaler2w: sysmmu@0x128E0000 { 857 compatible = "samsung,exynos-sysmmu"; 858 reg = <0x128E0000 0x1000>; 859 interrupt-parent = <&combiner>; 860 interrupts = <19 6>; 861 clock-names = "sysmmu", "master"; 862 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 863 #iommu-cells = <0>; 864 }; 865 866 sysmmu_rotator: sysmmu@0x11D40000 { 867 compatible = "samsung,exynos-sysmmu"; 868 reg = <0x11D40000 0x1000>; 869 interrupt-parent = <&combiner>; 870 interrupts = <4 0>; 871 clock-names = "sysmmu", "master"; 872 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 873 #iommu-cells = <0>; 874 }; 875 876 sysmmu_jpeg0: sysmmu@0x11F10000 { 877 compatible = "samsung,exynos-sysmmu"; 878 reg = <0x11F10000 0x1000>; 879 interrupt-parent = <&combiner>; 880 interrupts = <4 2>; 881 clock-names = "sysmmu", "master"; 882 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 883 #iommu-cells = <0>; 884 }; 885 886 sysmmu_jpeg1: sysmmu@0x11F20000 { 887 compatible = "samsung,exynos-sysmmu"; 888 reg = <0x11F20000 0x1000>; 889 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 890 clock-names = "sysmmu", "master"; 891 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; 892 #iommu-cells = <0>; 893 }; 894 895 sysmmu_mfc_l: sysmmu@0x11200000 { 896 compatible = "samsung,exynos-sysmmu"; 897 reg = <0x11200000 0x1000>; 898 interrupt-parent = <&combiner>; 899 interrupts = <6 2>; 900 clock-names = "sysmmu", "master"; 901 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 902 power-domains = <&mfc_pd>; 903 #iommu-cells = <0>; 904 }; 905 906 sysmmu_mfc_r: sysmmu@0x11210000 { 907 compatible = "samsung,exynos-sysmmu"; 908 reg = <0x11210000 0x1000>; 909 interrupt-parent = <&combiner>; 910 interrupts = <8 5>; 911 clock-names = "sysmmu", "master"; 912 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 913 power-domains = <&mfc_pd>; 914 #iommu-cells = <0>; 915 }; 916 917 sysmmu_fimd1_0: sysmmu@0x14640000 { 918 compatible = "samsung,exynos-sysmmu"; 919 reg = <0x14640000 0x1000>; 920 interrupt-parent = <&combiner>; 921 interrupts = <3 2>; 922 clock-names = "sysmmu", "master"; 923 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; 924 power-domains = <&disp_pd>; 925 #iommu-cells = <0>; 926 }; 927 928 sysmmu_fimd1_1: sysmmu@0x14680000 { 929 compatible = "samsung,exynos-sysmmu"; 930 reg = <0x14680000 0x1000>; 931 interrupt-parent = <&combiner>; 932 interrupts = <3 0>; 933 clock-names = "sysmmu", "master"; 934 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; 935 power-domains = <&disp_pd>; 936 #iommu-cells = <0>; 937 }; 938 939 bus_wcore: bus_wcore { 940 compatible = "samsung,exynos-bus"; 941 clocks = <&clock CLK_DOUT_ACLK400_WCORE>; 942 clock-names = "bus"; 943 operating-points-v2 = <&bus_wcore_opp_table>; 944 status = "disabled"; 945 }; 946 947 bus_noc: bus_noc { 948 compatible = "samsung,exynos-bus"; 949 clocks = <&clock CLK_DOUT_ACLK100_NOC>; 950 clock-names = "bus"; 951 operating-points-v2 = <&bus_noc_opp_table>; 952 status = "disabled"; 953 }; 954 955 bus_fsys_apb: bus_fsys_apb { 956 compatible = "samsung,exynos-bus"; 957 clocks = <&clock CLK_DOUT_PCLK200_FSYS>; 958 clock-names = "bus"; 959 operating-points-v2 = <&bus_fsys_apb_opp_table>; 960 status = "disabled"; 961 }; 962 963 bus_fsys: bus_fsys { 964 compatible = "samsung,exynos-bus"; 965 clocks = <&clock CLK_DOUT_ACLK200_FSYS>; 966 clock-names = "bus"; 967 operating-points-v2 = <&bus_fsys_apb_opp_table>; 968 status = "disabled"; 969 }; 970 971 bus_fsys2: bus_fsys2 { 972 compatible = "samsung,exynos-bus"; 973 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; 974 clock-names = "bus"; 975 operating-points-v2 = <&bus_fsys2_opp_table>; 976 status = "disabled"; 977 }; 978 979 bus_mfc: bus_mfc { 980 compatible = "samsung,exynos-bus"; 981 clocks = <&clock CLK_DOUT_ACLK333>; 982 clock-names = "bus"; 983 operating-points-v2 = <&bus_mfc_opp_table>; 984 status = "disabled"; 985 }; 986 987 bus_gen: bus_gen { 988 compatible = "samsung,exynos-bus"; 989 clocks = <&clock CLK_DOUT_ACLK266>; 990 clock-names = "bus"; 991 operating-points-v2 = <&bus_gen_opp_table>; 992 status = "disabled"; 993 }; 994 995 bus_peri: bus_peri { 996 compatible = "samsung,exynos-bus"; 997 clocks = <&clock CLK_DOUT_ACLK66>; 998 clock-names = "bus"; 999 operating-points-v2 = <&bus_peri_opp_table>; 1000 status = "disabled"; 1001 }; 1002 1003 bus_g2d: bus_g2d { 1004 compatible = "samsung,exynos-bus"; 1005 clocks = <&clock CLK_DOUT_ACLK333_G2D>; 1006 clock-names = "bus"; 1007 operating-points-v2 = <&bus_g2d_opp_table>; 1008 status = "disabled"; 1009 }; 1010 1011 bus_g2d_acp: bus_g2d_acp { 1012 compatible = "samsung,exynos-bus"; 1013 clocks = <&clock CLK_DOUT_ACLK266_G2D>; 1014 clock-names = "bus"; 1015 operating-points-v2 = <&bus_g2d_acp_opp_table>; 1016 status = "disabled"; 1017 }; 1018 1019 bus_jpeg: bus_jpeg { 1020 compatible = "samsung,exynos-bus"; 1021 clocks = <&clock CLK_DOUT_ACLK300_JPEG>; 1022 clock-names = "bus"; 1023 operating-points-v2 = <&bus_jpeg_opp_table>; 1024 status = "disabled"; 1025 }; 1026 1027 bus_jpeg_apb: bus_jpeg_apb { 1028 compatible = "samsung,exynos-bus"; 1029 clocks = <&clock CLK_DOUT_ACLK166>; 1030 clock-names = "bus"; 1031 operating-points-v2 = <&bus_jpeg_apb_opp_table>; 1032 status = "disabled"; 1033 }; 1034 1035 bus_disp1_fimd: bus_disp1_fimd { 1036 compatible = "samsung,exynos-bus"; 1037 clocks = <&clock CLK_DOUT_ACLK300_DISP1>; 1038 clock-names = "bus"; 1039 operating-points-v2 = <&bus_disp1_fimd_opp_table>; 1040 status = "disabled"; 1041 }; 1042 1043 bus_disp1: bus_disp1 { 1044 compatible = "samsung,exynos-bus"; 1045 clocks = <&clock CLK_DOUT_ACLK400_DISP1>; 1046 clock-names = "bus"; 1047 operating-points-v2 = <&bus_disp1_opp_table>; 1048 status = "disabled"; 1049 }; 1050 1051 bus_gscl_scaler: bus_gscl_scaler { 1052 compatible = "samsung,exynos-bus"; 1053 clocks = <&clock CLK_DOUT_ACLK300_GSCL>; 1054 clock-names = "bus"; 1055 operating-points-v2 = <&bus_gscl_opp_table>; 1056 status = "disabled"; 1057 }; 1058 1059 bus_mscl: bus_mscl { 1060 compatible = "samsung,exynos-bus"; 1061 clocks = <&clock CLK_DOUT_ACLK400_MSCL>; 1062 clock-names = "bus"; 1063 operating-points-v2 = <&bus_mscl_opp_table>; 1064 status = "disabled"; 1065 }; 1066 1067 bus_wcore_opp_table: opp_table2 { 1068 compatible = "operating-points-v2"; 1069 1070 opp00 { 1071 opp-hz = /bits/ 64 <84000000>; 1072 opp-microvolt = <925000>; 1073 }; 1074 opp01 { 1075 opp-hz = /bits/ 64 <111000000>; 1076 opp-microvolt = <950000>; 1077 }; 1078 opp02 { 1079 opp-hz = /bits/ 64 <222000000>; 1080 opp-microvolt = <950000>; 1081 }; 1082 opp03 { 1083 opp-hz = /bits/ 64 <333000000>; 1084 opp-microvolt = <950000>; 1085 }; 1086 opp04 { 1087 opp-hz = /bits/ 64 <400000000>; 1088 opp-microvolt = <987500>; 1089 }; 1090 }; 1091 1092 bus_noc_opp_table: opp_table3 { 1093 compatible = "operating-points-v2"; 1094 1095 opp00 { 1096 opp-hz = /bits/ 64 <67000000>; 1097 }; 1098 opp01 { 1099 opp-hz = /bits/ 64 <75000000>; 1100 }; 1101 opp02 { 1102 opp-hz = /bits/ 64 <86000000>; 1103 }; 1104 opp03 { 1105 opp-hz = /bits/ 64 <100000000>; 1106 }; 1107 }; 1108 1109 bus_fsys_apb_opp_table: opp_table4 { 1110 compatible = "operating-points-v2"; 1111 opp-shared; 1112 1113 opp00 { 1114 opp-hz = /bits/ 64 <100000000>; 1115 }; 1116 opp01 { 1117 opp-hz = /bits/ 64 <200000000>; 1118 }; 1119 }; 1120 1121 bus_fsys2_opp_table: opp_table5 { 1122 compatible = "operating-points-v2"; 1123 1124 opp00 { 1125 opp-hz = /bits/ 64 <75000000>; 1126 }; 1127 opp01 { 1128 opp-hz = /bits/ 64 <100000000>; 1129 }; 1130 opp02 { 1131 opp-hz = /bits/ 64 <150000000>; 1132 }; 1133 }; 1134 1135 bus_mfc_opp_table: opp_table6 { 1136 compatible = "operating-points-v2"; 1137 1138 opp00 { 1139 opp-hz = /bits/ 64 <96000000>; 1140 }; 1141 opp01 { 1142 opp-hz = /bits/ 64 <111000000>; 1143 }; 1144 opp02 { 1145 opp-hz = /bits/ 64 <167000000>; 1146 }; 1147 opp03 { 1148 opp-hz = /bits/ 64 <222000000>; 1149 }; 1150 opp04 { 1151 opp-hz = /bits/ 64 <333000000>; 1152 }; 1153 }; 1154 1155 bus_gen_opp_table: opp_table7 { 1156 compatible = "operating-points-v2"; 1157 1158 opp00 { 1159 opp-hz = /bits/ 64 <89000000>; 1160 }; 1161 opp01 { 1162 opp-hz = /bits/ 64 <133000000>; 1163 }; 1164 opp02 { 1165 opp-hz = /bits/ 64 <178000000>; 1166 }; 1167 opp03 { 1168 opp-hz = /bits/ 64 <267000000>; 1169 }; 1170 }; 1171 1172 bus_peri_opp_table: opp_table8 { 1173 compatible = "operating-points-v2"; 1174 1175 opp00 { 1176 opp-hz = /bits/ 64 <67000000>; 1177 }; 1178 }; 1179 1180 bus_g2d_opp_table: opp_table9 { 1181 compatible = "operating-points-v2"; 1182 1183 opp00 { 1184 opp-hz = /bits/ 64 <84000000>; 1185 }; 1186 opp01 { 1187 opp-hz = /bits/ 64 <167000000>; 1188 }; 1189 opp02 { 1190 opp-hz = /bits/ 64 <222000000>; 1191 }; 1192 opp03 { 1193 opp-hz = /bits/ 64 <300000000>; 1194 }; 1195 opp04 { 1196 opp-hz = /bits/ 64 <333000000>; 1197 }; 1198 }; 1199 1200 bus_g2d_acp_opp_table: opp_table10 { 1201 compatible = "operating-points-v2"; 1202 1203 opp00 { 1204 opp-hz = /bits/ 64 <67000000>; 1205 }; 1206 opp01 { 1207 opp-hz = /bits/ 64 <133000000>; 1208 }; 1209 opp02 { 1210 opp-hz = /bits/ 64 <178000000>; 1211 }; 1212 opp03 { 1213 opp-hz = /bits/ 64 <267000000>; 1214 }; 1215 }; 1216 1217 bus_jpeg_opp_table: opp_table11 { 1218 compatible = "operating-points-v2"; 1219 1220 opp00 { 1221 opp-hz = /bits/ 64 <75000000>; 1222 }; 1223 opp01 { 1224 opp-hz = /bits/ 64 <150000000>; 1225 }; 1226 opp02 { 1227 opp-hz = /bits/ 64 <200000000>; 1228 }; 1229 opp03 { 1230 opp-hz = /bits/ 64 <300000000>; 1231 }; 1232 }; 1233 1234 bus_jpeg_apb_opp_table: opp_table12 { 1235 compatible = "operating-points-v2"; 1236 1237 opp00 { 1238 opp-hz = /bits/ 64 <84000000>; 1239 }; 1240 opp01 { 1241 opp-hz = /bits/ 64 <111000000>; 1242 }; 1243 opp02 { 1244 opp-hz = /bits/ 64 <134000000>; 1245 }; 1246 opp03 { 1247 opp-hz = /bits/ 64 <167000000>; 1248 }; 1249 }; 1250 1251 bus_disp1_fimd_opp_table: opp_table13 { 1252 compatible = "operating-points-v2"; 1253 1254 opp00 { 1255 opp-hz = /bits/ 64 <120000000>; 1256 }; 1257 opp01 { 1258 opp-hz = /bits/ 64 <200000000>; 1259 }; 1260 }; 1261 1262 bus_disp1_opp_table: opp_table14 { 1263 compatible = "operating-points-v2"; 1264 1265 opp00 { 1266 opp-hz = /bits/ 64 <120000000>; 1267 }; 1268 opp01 { 1269 opp-hz = /bits/ 64 <200000000>; 1270 }; 1271 opp02 { 1272 opp-hz = /bits/ 64 <300000000>; 1273 }; 1274 }; 1275 1276 bus_gscl_opp_table: opp_table15 { 1277 compatible = "operating-points-v2"; 1278 1279 opp00 { 1280 opp-hz = /bits/ 64 <150000000>; 1281 }; 1282 opp01 { 1283 opp-hz = /bits/ 64 <200000000>; 1284 }; 1285 opp02 { 1286 opp-hz = /bits/ 64 <300000000>; 1287 }; 1288 }; 1289 1290 bus_mscl_opp_table: opp_table16 { 1291 compatible = "operating-points-v2"; 1292 1293 opp00 { 1294 opp-hz = /bits/ 64 <84000000>; 1295 }; 1296 opp01 { 1297 opp-hz = /bits/ 64 <167000000>; 1298 }; 1299 opp02 { 1300 opp-hz = /bits/ 64 <222000000>; 1301 }; 1302 opp03 { 1303 opp-hz = /bits/ 64 <333000000>; 1304 }; 1305 opp04 { 1306 opp-hz = /bits/ 64 <400000000>; 1307 }; 1308 }; 1309 }; 1310 1311 thermal-zones { 1312 cpu0_thermal: cpu0-thermal { 1313 thermal-sensors = <&tmu_cpu0>; 1314 #include "exynos5420-trip-points.dtsi" 1315 }; 1316 cpu1_thermal: cpu1-thermal { 1317 thermal-sensors = <&tmu_cpu1>; 1318 #include "exynos5420-trip-points.dtsi" 1319 }; 1320 cpu2_thermal: cpu2-thermal { 1321 thermal-sensors = <&tmu_cpu2>; 1322 #include "exynos5420-trip-points.dtsi" 1323 }; 1324 cpu3_thermal: cpu3-thermal { 1325 thermal-sensors = <&tmu_cpu3>; 1326 #include "exynos5420-trip-points.dtsi" 1327 }; 1328 gpu_thermal: gpu-thermal { 1329 thermal-sensors = <&tmu_gpu>; 1330 #include "exynos5420-trip-points.dtsi" 1331 }; 1332 }; 1333}; 1334 1335&dp { 1336 clocks = <&clock CLK_DP1>; 1337 clock-names = "dp"; 1338 phys = <&dp_phy>; 1339 phy-names = "dp"; 1340 power-domains = <&disp_pd>; 1341}; 1342 1343&fimd { 1344 compatible = "samsung,exynos5420-fimd"; 1345 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1346 clock-names = "sclk_fimd", "fimd"; 1347 power-domains = <&disp_pd>; 1348 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; 1349 iommu-names = "m0", "m1"; 1350}; 1351 1352&i2c_0 { 1353 clocks = <&clock CLK_I2C0>; 1354 clock-names = "i2c"; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&i2c0_bus>; 1357}; 1358 1359&i2c_1 { 1360 clocks = <&clock CLK_I2C1>; 1361 clock-names = "i2c"; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&i2c1_bus>; 1364}; 1365 1366&i2c_2 { 1367 clocks = <&clock CLK_I2C2>; 1368 clock-names = "i2c"; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&i2c2_bus>; 1371}; 1372 1373&i2c_3 { 1374 clocks = <&clock CLK_I2C3>; 1375 clock-names = "i2c"; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&i2c3_bus>; 1378}; 1379 1380&hsi2c_4 { 1381 clocks = <&clock CLK_USI0>; 1382 clock-names = "hsi2c"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&i2c4_hs_bus>; 1385}; 1386 1387&hsi2c_5 { 1388 clocks = <&clock CLK_USI1>; 1389 clock-names = "hsi2c"; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&i2c5_hs_bus>; 1392}; 1393 1394&hsi2c_6 { 1395 clocks = <&clock CLK_USI2>; 1396 clock-names = "hsi2c"; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&i2c6_hs_bus>; 1399}; 1400 1401&hsi2c_7 { 1402 clocks = <&clock CLK_USI3>; 1403 clock-names = "hsi2c"; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&i2c7_hs_bus>; 1406}; 1407 1408&mct { 1409 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 1410 clock-names = "fin_pll", "mct"; 1411}; 1412 1413&pwm { 1414 clocks = <&clock CLK_PWM>; 1415 clock-names = "timers"; 1416}; 1417 1418&rtc { 1419 clocks = <&clock CLK_RTC>; 1420 clock-names = "rtc"; 1421 interrupt-parent = <&pmu_system_controller>; 1422 status = "disabled"; 1423}; 1424 1425&serial_0 { 1426 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1427 clock-names = "uart", "clk_uart_baud0"; 1428 dmas = <&pdma0 13>, <&pdma0 14>; 1429 dma-names = "rx", "tx"; 1430}; 1431 1432&serial_1 { 1433 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1434 clock-names = "uart", "clk_uart_baud0"; 1435 dmas = <&pdma1 15>, <&pdma1 16>; 1436 dma-names = "rx", "tx"; 1437}; 1438 1439&serial_2 { 1440 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1441 clock-names = "uart", "clk_uart_baud0"; 1442 dmas = <&pdma0 15>, <&pdma0 16>; 1443 dma-names = "rx", "tx"; 1444}; 1445 1446&serial_3 { 1447 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1448 clock-names = "uart", "clk_uart_baud0"; 1449 dmas = <&pdma1 17>, <&pdma1 18>; 1450 dma-names = "rx", "tx"; 1451}; 1452 1453&sss { 1454 clocks = <&clock CLK_SSS>; 1455 clock-names = "secss"; 1456}; 1457 1458&usbdrd3_0 { 1459 clocks = <&clock CLK_USBD300>; 1460 clock-names = "usbdrd30"; 1461}; 1462 1463&usbdrd_phy0 { 1464 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 1465 clock-names = "phy", "ref"; 1466 samsung,pmu-syscon = <&pmu_system_controller>; 1467}; 1468 1469&usbdrd3_1 { 1470 clocks = <&clock CLK_USBD301>; 1471 clock-names = "usbdrd30"; 1472}; 1473 1474&usbdrd_dwc3_1 { 1475 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1476}; 1477 1478&usbdrd_phy1 { 1479 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 1480 clock-names = "phy", "ref"; 1481 samsung,pmu-syscon = <&pmu_system_controller>; 1482}; 1483 1484&usbhost1 { 1485 clocks = <&clock CLK_USBH20>; 1486 clock-names = "usbhost"; 1487}; 1488 1489&usbhost2 { 1490 clocks = <&clock CLK_USBH20>; 1491 clock-names = "usbhost"; 1492}; 1493 1494&usb2_phy { 1495 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 1496 clock-names = "phy", "ref"; 1497 samsung,sysreg-phandle = <&sysreg_system_controller>; 1498 samsung,pmureg-phandle = <&pmu_system_controller>; 1499}; 1500 1501&watchdog { 1502 clocks = <&clock CLK_WDT>; 1503 clock-names = "watchdog"; 1504 samsung,syscon-phandle = <&pmu_system_controller>; 1505}; 1506 1507#include "exynos5420-pinctrl.dtsi" 1508