1/* $NetBSD: uldiv.S,v 1.1.1.1 2018/08/16 18:17:47 jmcneill Exp $ */ 2 3//------------------------------------------------------------------------------ 4// 5// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 6// 7// This program and the accompanying materials 8// are licensed and made available under the terms and conditions of the BSD License 9// which accompanies this distribution. The full text of the license may be found at 10// http://opensource.org/licenses/bsd-license.php 11// 12// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14// 15//------------------------------------------------------------------------------ 16 17#include "edk2asm.h" 18 19 .text 20 .align 2 21 GCC_ASM_EXPORT(__aeabi_uldivmod) 22 23// 24//UINT64 25//EFIAPI 26//__aeabi_uldivmod ( 27// IN UINT64 Dividend 28// IN UINT64 Divisor 29// ) 30// 31ASM_PFX(__aeabi_uldivmod): 32 stmdb sp!, {r4, r5, r6, lr} 33 mov r4, r1 34 mov r5, r0 35 mov r6, #0 // 0x0 36 orrs ip, r3, r2, lsr #31 37 bne ASM_PFX(__aeabi_uldivmod_label1) 38 tst r2, r2 39 beq ASM_PFX(_ll_div0) 40 movs ip, r2, lsr #15 41 addeq r6, r6, #16 // 0x10 42 mov ip, r2, lsl r6 43 movs lr, ip, lsr #23 44 moveq ip, ip, lsl #8 45 addeq r6, r6, #8 // 0x8 46 movs lr, ip, lsr #27 47 moveq ip, ip, lsl #4 48 addeq r6, r6, #4 // 0x4 49 movs lr, ip, lsr #29 50 moveq ip, ip, lsl #2 51 addeq r6, r6, #2 // 0x2 52 movs lr, ip, lsr #30 53 moveq ip, ip, lsl #1 54 addeq r6, r6, #1 // 0x1 55 b ASM_PFX(_ll_udiv_small) 56ASM_PFX(__aeabi_uldivmod_label1): 57 tst r3, #-2147483648 // 0x80000000 58 bne ASM_PFX(__aeabi_uldivmod_label2) 59 movs ip, r3, lsr #15 60 addeq r6, r6, #16 // 0x10 61 mov ip, r3, lsl r6 62 movs lr, ip, lsr #23 63 moveq ip, ip, lsl #8 64 addeq r6, r6, #8 // 0x8 65 movs lr, ip, lsr #27 66 moveq ip, ip, lsl #4 67 addeq r6, r6, #4 // 0x4 68 movs lr, ip, lsr #29 69 moveq ip, ip, lsl #2 70 addeq r6, r6, #2 // 0x2 71 movs lr, ip, lsr #30 72 addeq r6, r6, #1 // 0x1 73 rsb r3, r6, #32 // 0x20 74 moveq ip, ip, lsl #1 75 orr ip, ip, r2, lsr r3 76 mov lr, r2, lsl r6 77 b ASM_PFX(_ll_udiv_big) 78ASM_PFX(__aeabi_uldivmod_label2): 79 mov ip, r3 80 mov lr, r2 81 b ASM_PFX(_ll_udiv_ginormous) 82 83ASM_PFX(_ll_udiv_small): 84 cmp r4, ip, lsl #1 85 mov r3, #0 // 0x0 86 subcs r4, r4, ip, lsl #1 87 addcs r3, r3, #2 // 0x2 88 cmp r4, ip 89 subcs r4, r4, ip 90 adcs r3, r3, #0 // 0x0 91 add r2, r6, #32 // 0x20 92 cmp r2, #32 // 0x20 93 rsb ip, ip, #0 // 0x0 94 bcc ASM_PFX(_ll_udiv_small_label1) 95 orrs r0, r4, r5, lsr #30 96 moveq r4, r5 97 moveq r5, #0 // 0x0 98 subeq r2, r2, #32 // 0x20 99ASM_PFX(_ll_udiv_small_label1): 100 mov r1, #0 // 0x0 101 cmp r2, #16 // 0x10 102 bcc ASM_PFX(_ll_udiv_small_label2) 103 movs r0, r4, lsr #14 104 moveq r4, r4, lsl #16 105 addeq r1, r1, #16 // 0x10 106ASM_PFX(_ll_udiv_small_label2): 107 sub lr, r2, r1 108 cmp lr, #8 // 0x8 109 bcc ASM_PFX(_ll_udiv_small_label3) 110 movs r0, r4, lsr #22 111 moveq r4, r4, lsl #8 112 addeq r1, r1, #8 // 0x8 113ASM_PFX(_ll_udiv_small_label3): 114 rsb r0, r1, #32 // 0x20 115 sub r2, r2, r1 116 orr r4, r4, r5, lsr r0 117 mov r5, r5, lsl r1 118 cmp r2, #1 // 0x1 119 bcc ASM_PFX(_ll_udiv_small_label5) 120 sub r2, r2, #1 // 0x1 121 and r0, r2, #7 // 0x7 122 eor r0, r0, #7 // 0x7 123 adds r0, r0, r0, lsl #1 124 add pc, pc, r0, lsl #2 125 nop // (mov r0,r0) 126ASM_PFX(_ll_udiv_small_label4): 127 adcs r5, r5, r5 128 adcs r4, ip, r4, lsl #1 129 rsbcc r4, ip, r4 130 adcs r5, r5, r5 131 adcs r4, ip, r4, lsl #1 132 rsbcc r4, ip, r4 133 adcs r5, r5, r5 134 adcs r4, ip, r4, lsl #1 135 rsbcc r4, ip, r4 136 adcs r5, r5, r5 137 adcs r4, ip, r4, lsl #1 138 rsbcc r4, ip, r4 139 adcs r5, r5, r5 140 adcs r4, ip, r4, lsl #1 141 rsbcc r4, ip, r4 142 adcs r5, r5, r5 143 adcs r4, ip, r4, lsl #1 144 rsbcc r4, ip, r4 145 adcs r5, r5, r5 146 adcs r4, ip, r4, lsl #1 147 rsbcc r4, ip, r4 148 adcs r5, r5, r5 149 adcs r4, ip, r4, lsl #1 150 sub r2, r2, #8 // 0x8 151 tst r2, r2 152 rsbcc r4, ip, r4 153 bpl ASM_PFX(_ll_udiv_small_label4) 154ASM_PFX(_ll_udiv_small_label5): 155 mov r2, r4, lsr r6 156 bic r4, r4, r2, lsl r6 157 adcs r0, r5, r5 158 adc r1, r4, r4 159 add r1, r1, r3, lsl r6 160 mov r3, #0 // 0x0 161 ldmia sp!, {r4, r5, r6, pc} 162 163ASM_PFX(_ll_udiv_big): 164 subs r0, r5, lr 165 mov r3, #0 // 0x0 166 sbcs r1, r4, ip 167 movcs r5, r0 168 movcs r4, r1 169 adcs r3, r3, #0 // 0x0 170 subs r0, r5, lr 171 sbcs r1, r4, ip 172 movcs r5, r0 173 movcs r4, r1 174 adcs r3, r3, #0 // 0x0 175 subs r0, r5, lr 176 sbcs r1, r4, ip 177 movcs r5, r0 178 movcs r4, r1 179 adcs r3, r3, #0 // 0x0 180 mov r1, #0 // 0x0 181 rsbs lr, lr, #0 // 0x0 182 rsc ip, ip, #0 // 0x0 183 cmp r6, #16 // 0x10 184 bcc ASM_PFX(_ll_udiv_big_label1) 185 movs r0, r4, lsr #14 186 moveq r4, r4, lsl #16 187 addeq r1, r1, #16 // 0x10 188ASM_PFX(_ll_udiv_big_label1): 189 sub r2, r6, r1 190 cmp r2, #8 // 0x8 191 bcc ASM_PFX(_ll_udiv_big_label2) 192 movs r0, r4, lsr #22 193 moveq r4, r4, lsl #8 194 addeq r1, r1, #8 // 0x8 195ASM_PFX(_ll_udiv_big_label2): 196 rsb r0, r1, #32 // 0x20 197 sub r2, r6, r1 198 orr r4, r4, r5, lsr r0 199 mov r5, r5, lsl r1 200 cmp r2, #1 // 0x1 201 bcc ASM_PFX(_ll_udiv_big_label4) 202 sub r2, r2, #1 // 0x1 203 and r0, r2, #3 // 0x3 204 rsb r0, r0, #3 // 0x3 205 adds r0, r0, r0, lsl #1 206 add pc, pc, r0, lsl #3 207 nop // (mov r0,r0) 208ASM_PFX(_ll_udiv_big_label3): 209 adcs r5, r5, r5 210 adcs r4, r4, r4 211 adcs r0, lr, r5 212 adcs r1, ip, r4 213 movcs r5, r0 214 movcs r4, r1 215 adcs r5, r5, r5 216 adcs r4, r4, r4 217 adcs r0, lr, r5 218 adcs r1, ip, r4 219 movcs r5, r0 220 movcs r4, r1 221 adcs r5, r5, r5 222 adcs r4, r4, r4 223 adcs r0, lr, r5 224 adcs r1, ip, r4 225 movcs r5, r0 226 movcs r4, r1 227 sub r2, r2, #4 // 0x4 228 adcs r5, r5, r5 229 adcs r4, r4, r4 230 adcs r0, lr, r5 231 adcs r1, ip, r4 232 tst r2, r2 233 movcs r5, r0 234 movcs r4, r1 235 bpl ASM_PFX(_ll_udiv_big_label3) 236ASM_PFX(_ll_udiv_big_label4): 237 mov r1, #0 // 0x0 238 mov r2, r5, lsr r6 239 bic r5, r5, r2, lsl r6 240 adcs r0, r5, r5 241 adc r1, r1, #0 // 0x0 242 movs lr, r3, lsl r6 243 mov r3, r4, lsr r6 244 bic r4, r4, r3, lsl r6 245 adc r1, r1, #0 // 0x0 246 adds r0, r0, lr 247 orr r2, r2, r4, ror r6 248 adc r1, r1, #0 // 0x0 249 ldmia sp!, {r4, r5, r6, pc} 250 251ASM_PFX(_ll_udiv_ginormous): 252 subs r2, r5, lr 253 mov r1, #0 // 0x0 254 sbcs r3, r4, ip 255 adc r0, r1, r1 256 movcc r2, r5 257 movcc r3, r4 258 ldmia sp!, {r4, r5, r6, pc} 259 260ASM_PFX(_ll_div0): 261 ldmia sp!, {r4, r5, r6, lr} 262 mov r0, #0 // 0x0 263 mov r1, #0 // 0x0 264 b ASM_PFX(__aeabi_ldiv0) 265 266ASM_PFX(__aeabi_ldiv0): 267 bx r14 268 269 270