1 /* $NetBSD: dwc2var.h,v 1.7 2020/02/12 16:01:00 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DWC2VAR_H_ 33 #define _DWC2VAR_H_ 34 35 #include <sys/pool.h> 36 37 struct dwc2_hsotg; 38 struct dwc2_qtd; 39 40 struct dwc2_xfer { 41 struct usbd_xfer xfer; /* Needs to be first */ 42 43 struct dwc2_hcd_urb *urb; 44 45 TAILQ_ENTRY(dwc2_xfer) xnext; /* list of complete xfers */ 46 usbd_status intr_status; 47 }; 48 49 struct dwc2_pipe { 50 struct usbd_pipe pipe; /* Must be first */ 51 52 /* Current transfer */ 53 void *priv; /* QH */ 54 55 /* DMA buffer for control endpoint requests */ 56 usb_dma_t req_dma; 57 }; 58 59 60 #define DWC2_BUS2SC(bus) ((bus)->ub_hcpriv) 61 #define DWC2_PIPE2SC(pipe) DWC2_BUS2SC((pipe)->up_dev->ud_bus) 62 #define DWC2_XFER2SC(xfer) DWC2_BUS2SC((xfer)->ux_bus) 63 #define DWC2_DPIPE2SC(d) DWC2_BUS2SC((d)->pipe.up_dev->ud_bus) 64 65 #define DWC2_XFER2DXFER(x) (struct dwc2_xfer *)(x) 66 67 #define DWC2_XFER2DPIPE(x) (struct dwc2_pipe *)(x)->ux_pipe; 68 #define DWC2_PIPE2DPIPE(p) (struct dwc2_pipe *)(p) 69 70 71 typedef struct dwc2_softc { 72 device_t sc_dev; 73 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 bus_dma_tag_t sc_dmat; 77 struct dwc2_core_params *sc_params; 78 int (*sc_set_dma_addr)(device_t, bus_addr_t, int); 79 80 /* 81 * Private 82 */ 83 84 struct usbd_bus sc_bus; 85 struct dwc2_hsotg *sc_hsotg; 86 87 kmutex_t sc_lock; 88 89 bool sc_hcdenabled; 90 void *sc_rhc_si; 91 92 struct usbd_xfer *sc_intrxfer; 93 94 device_t sc_child; /* /dev/usb# device */ 95 char sc_dying; 96 97 TAILQ_HEAD(, dwc2_xfer) sc_complete; /* complete transfers */ 98 99 pool_cache_t sc_xferpool; 100 pool_cache_t sc_qhpool; 101 pool_cache_t sc_qtdpool; 102 103 } dwc2_softc_t; 104 105 int dwc2_init(struct dwc2_softc *); 106 int dwc2_intr(void *); 107 int dwc2_detach(dwc2_softc_t *, int); 108 bool dwc2_shutdown(device_t, int); 109 void dwc2_childdet(device_t, device_t); 110 int dwc2_activate(device_t, enum devact); 111 bool dwc2_resume(device_t, const pmf_qual_t *); 112 bool dwc2_suspend(device_t, const pmf_qual_t *); 113 114 void dwc2_worker(struct work *, void *); 115 116 void dwc2_host_complete(struct dwc2_hsotg *, struct dwc2_qtd *, 117 int); 118 119 static inline void 120 dwc2_root_intr(dwc2_softc_t *sc) 121 { 122 123 softint_schedule(sc->sc_rhc_si); 124 } 125 126 #endif /* _DWC_OTGVAR_H_ */ 127