1 /* $NetBSD: dwc2.c,v 1.76 2021/01/07 13:25:51 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: dwc2.c,v 1.76 2021/01/07 13:25:51 skrll Exp $"); 34 35 #include "opt_usb.h" 36 37 #include <sys/param.h> 38 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/kmem.h> 43 #include <sys/proc.h> 44 #include <sys/queue.h> 45 #include <sys/select.h> 46 #include <sys/sysctl.h> 47 #include <sys/systm.h> 48 49 #include <machine/endian.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdivar.h> 54 #include <dev/usb/usb_mem.h> 55 #include <dev/usb/usbroothub.h> 56 57 #include <dwc2/dwc2.h> 58 #include <dwc2/dwc2var.h> 59 60 #include "dwc2_core.h" 61 #include "dwc2_hcd.h" 62 63 #ifdef DWC2_COUNTERS 64 #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b))) 65 #else 66 #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0) 67 #endif 68 #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1) 69 70 #ifdef DWC2_DEBUG 71 #define DPRINTFN(n,fmt,...) do { \ 72 if (dwc2debug >= (n)) { \ 73 printf("%s: " fmt, \ 74 __FUNCTION__,## __VA_ARGS__); \ 75 } \ 76 } while (0) 77 #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__) 78 int dwc2debug = 0; 79 80 SYSCTL_SETUP(sysctl_hw_dwc2_setup, "sysctl hw.dwc2 setup") 81 { 82 int err; 83 const struct sysctlnode *rnode; 84 const struct sysctlnode *cnode; 85 86 err = sysctl_createv(clog, 0, NULL, &rnode, 87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "dwc2", 88 SYSCTL_DESCR("dwc2 global controls"), 89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 90 91 if (err) 92 goto fail; 93 94 /* control debugging printfs */ 95 err = sysctl_createv(clog, 0, &rnode, &cnode, 96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 97 "debug", SYSCTL_DESCR("Enable debugging output"), 98 NULL, 0, &dwc2debug, sizeof(dwc2debug), CTL_CREATE, CTL_EOL); 99 if (err) 100 goto fail; 101 102 return; 103 fail: 104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 105 } 106 #else 107 #define DPRINTF(...) do { } while (0) 108 #define DPRINTFN(...) do { } while (0) 109 #endif 110 111 Static usbd_status dwc2_open(struct usbd_pipe *); 112 Static void dwc2_poll(struct usbd_bus *); 113 Static void dwc2_softintr(void *); 114 115 Static struct usbd_xfer * 116 dwc2_allocx(struct usbd_bus *, unsigned int); 117 Static void dwc2_freex(struct usbd_bus *, struct usbd_xfer *); 118 Static void dwc2_get_lock(struct usbd_bus *, kmutex_t **); 119 Static bool dwc2_dying(struct usbd_bus *); 120 Static int dwc2_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 121 void *, int); 122 123 Static usbd_status dwc2_root_intr_transfer(struct usbd_xfer *); 124 Static usbd_status dwc2_root_intr_start(struct usbd_xfer *); 125 Static void dwc2_root_intr_abort(struct usbd_xfer *); 126 Static void dwc2_root_intr_close(struct usbd_pipe *); 127 Static void dwc2_root_intr_done(struct usbd_xfer *); 128 129 Static usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *); 130 Static usbd_status dwc2_device_ctrl_start(struct usbd_xfer *); 131 Static void dwc2_device_ctrl_abort(struct usbd_xfer *); 132 Static void dwc2_device_ctrl_close(struct usbd_pipe *); 133 Static void dwc2_device_ctrl_done(struct usbd_xfer *); 134 135 Static usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *); 136 Static void dwc2_device_bulk_abort(struct usbd_xfer *); 137 Static void dwc2_device_bulk_close(struct usbd_pipe *); 138 Static void dwc2_device_bulk_done(struct usbd_xfer *); 139 140 Static usbd_status dwc2_device_intr_transfer(struct usbd_xfer *); 141 Static usbd_status dwc2_device_intr_start(struct usbd_xfer *); 142 Static void dwc2_device_intr_abort(struct usbd_xfer *); 143 Static void dwc2_device_intr_close(struct usbd_pipe *); 144 Static void dwc2_device_intr_done(struct usbd_xfer *); 145 146 Static usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *); 147 Static void dwc2_device_isoc_abort(struct usbd_xfer *); 148 Static void dwc2_device_isoc_close(struct usbd_pipe *); 149 Static void dwc2_device_isoc_done(struct usbd_xfer *); 150 151 Static usbd_status dwc2_device_start(struct usbd_xfer *); 152 153 Static void dwc2_close_pipe(struct usbd_pipe *); 154 Static void dwc2_abortx(struct usbd_xfer *); 155 156 Static void dwc2_device_clear_toggle(struct usbd_pipe *); 157 Static void dwc2_noop(struct usbd_pipe *pipe); 158 159 Static int dwc2_interrupt(struct dwc2_softc *); 160 Static void dwc2_rhc(void *); 161 162 163 static inline void 164 dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 165 struct usbd_xfer *xfer) 166 { 167 } 168 169 static inline void 170 dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 171 struct usbd_xfer *xfer) 172 { 173 } 174 175 Static const struct usbd_bus_methods dwc2_bus_methods = { 176 .ubm_open = dwc2_open, 177 .ubm_softint = dwc2_softintr, 178 .ubm_dopoll = dwc2_poll, 179 .ubm_allocx = dwc2_allocx, 180 .ubm_freex = dwc2_freex, 181 .ubm_abortx = dwc2_abortx, 182 .ubm_dying = dwc2_dying, 183 .ubm_getlock = dwc2_get_lock, 184 .ubm_rhctrl = dwc2_roothub_ctrl, 185 }; 186 187 Static const struct usbd_pipe_methods dwc2_root_intr_methods = { 188 .upm_transfer = dwc2_root_intr_transfer, 189 .upm_start = dwc2_root_intr_start, 190 .upm_abort = dwc2_root_intr_abort, 191 .upm_close = dwc2_root_intr_close, 192 .upm_cleartoggle = dwc2_noop, 193 .upm_done = dwc2_root_intr_done, 194 }; 195 196 Static const struct usbd_pipe_methods dwc2_device_ctrl_methods = { 197 .upm_transfer = dwc2_device_ctrl_transfer, 198 .upm_start = dwc2_device_ctrl_start, 199 .upm_abort = dwc2_device_ctrl_abort, 200 .upm_close = dwc2_device_ctrl_close, 201 .upm_cleartoggle = dwc2_noop, 202 .upm_done = dwc2_device_ctrl_done, 203 }; 204 205 Static const struct usbd_pipe_methods dwc2_device_intr_methods = { 206 .upm_transfer = dwc2_device_intr_transfer, 207 .upm_start = dwc2_device_intr_start, 208 .upm_abort = dwc2_device_intr_abort, 209 .upm_close = dwc2_device_intr_close, 210 .upm_cleartoggle = dwc2_device_clear_toggle, 211 .upm_done = dwc2_device_intr_done, 212 }; 213 214 Static const struct usbd_pipe_methods dwc2_device_bulk_methods = { 215 .upm_transfer = dwc2_device_bulk_transfer, 216 .upm_abort = dwc2_device_bulk_abort, 217 .upm_close = dwc2_device_bulk_close, 218 .upm_cleartoggle = dwc2_device_clear_toggle, 219 .upm_done = dwc2_device_bulk_done, 220 }; 221 222 Static const struct usbd_pipe_methods dwc2_device_isoc_methods = { 223 .upm_transfer = dwc2_device_isoc_transfer, 224 .upm_abort = dwc2_device_isoc_abort, 225 .upm_close = dwc2_device_isoc_close, 226 .upm_cleartoggle = dwc2_noop, 227 .upm_done = dwc2_device_isoc_done, 228 }; 229 230 struct usbd_xfer * 231 dwc2_allocx(struct usbd_bus *bus, unsigned int nframes) 232 { 233 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 234 struct dwc2_xfer *dxfer; 235 236 DPRINTFN(10, "\n"); 237 238 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget); 239 dxfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 240 if (dxfer != NULL) { 241 memset(dxfer, 0, sizeof(*dxfer)); 242 dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg, 243 nframes, GFP_KERNEL); 244 #ifdef DIAGNOSTIC 245 dxfer->xfer.ux_state = XFER_BUSY; 246 #endif 247 } 248 return (struct usbd_xfer *)dxfer; 249 } 250 251 void 252 dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 253 { 254 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 255 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 256 257 DPRINTFN(10, "\n"); 258 259 #ifdef DIAGNOSTIC 260 if (xfer->ux_state != XFER_BUSY && 261 xfer->ux_status != USBD_NOT_STARTED) { 262 DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 263 } 264 xfer->ux_state = XFER_FREE; 265 #endif 266 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput); 267 dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, dxfer->urb->packet_count); 268 pool_cache_put(sc->sc_xferpool, xfer); 269 } 270 271 Static bool 272 dwc2_dying(struct usbd_bus *bus) 273 { 274 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 275 276 return sc->sc_dying; 277 } 278 279 Static void 280 dwc2_get_lock(struct usbd_bus *bus, kmutex_t **lock) 281 { 282 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 283 284 *lock = &sc->sc_lock; 285 } 286 287 Static void 288 dwc2_rhc(void *addr) 289 { 290 struct dwc2_softc *sc = addr; 291 struct usbd_xfer *xfer; 292 u_char *p; 293 294 DPRINTF("\n"); 295 mutex_enter(&sc->sc_lock); 296 xfer = sc->sc_intrxfer; 297 298 if (xfer == NULL) { 299 /* Just ignore the change. */ 300 mutex_exit(&sc->sc_lock); 301 return; 302 303 } 304 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 305 306 /* set port bit */ 307 p = KERNADDR(&xfer->ux_dmabuf, 0); 308 309 p[0] = 0x02; /* we only have one port (1 << 1) */ 310 311 xfer->ux_actlen = xfer->ux_length; 312 xfer->ux_status = USBD_NORMAL_COMPLETION; 313 314 usb_transfer_complete(xfer); 315 mutex_exit(&sc->sc_lock); 316 } 317 318 Static void 319 dwc2_softintr(void *v) 320 { 321 struct usbd_bus *bus = v; 322 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 323 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 324 struct dwc2_xfer *dxfer, *next; 325 TAILQ_HEAD(, dwc2_xfer) claimed = TAILQ_HEAD_INITIALIZER(claimed); 326 327 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 328 329 /* 330 * Grab all the xfers that have not been aborted or timed out. 331 * Do so under a single lock -- without dropping it to run 332 * usb_transfer_complete as we go -- so that dwc2_abortx won't 333 * remove next out from under us during iteration when we've 334 * dropped the lock. 335 */ 336 mutex_spin_enter(&hsotg->lock); 337 TAILQ_FOREACH_SAFE(dxfer, &sc->sc_complete, xnext, next) { 338 if (!usbd_xfer_trycomplete(&dxfer->xfer)) 339 /* 340 * The hard interrput handler decided to 341 * complete the xfer, and put it on sc_complete 342 * to pass it to us in the soft interrupt 343 * handler, but in the time between hard 344 * interrupt and soft interrupt, the xfer was 345 * aborted or timed out and we lost the race. 346 */ 347 continue; 348 KASSERT(dxfer->xfer.ux_status == USBD_IN_PROGRESS); 349 KASSERT(dxfer->intr_status != USBD_CANCELLED); 350 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 351 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 352 TAILQ_INSERT_TAIL(&claimed, dxfer, xnext); 353 } 354 mutex_spin_exit(&hsotg->lock); 355 356 /* Now complete them. */ 357 while (!TAILQ_EMPTY(&claimed)) { 358 dxfer = TAILQ_FIRST(&claimed); 359 KASSERT(dxfer->xfer.ux_status == USBD_IN_PROGRESS); 360 KASSERT(dxfer->intr_status != USBD_CANCELLED); 361 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 362 TAILQ_REMOVE(&claimed, dxfer, xnext); 363 364 dxfer->xfer.ux_status = dxfer->intr_status; 365 usb_transfer_complete(&dxfer->xfer); 366 } 367 } 368 369 usbd_status 370 dwc2_open(struct usbd_pipe *pipe) 371 { 372 struct usbd_device *dev = pipe->up_dev; 373 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 374 struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe); 375 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 376 uint8_t addr = dev->ud_addr; 377 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 378 379 DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype, 380 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out"); 381 382 if (sc->sc_dying) { 383 return USBD_IOERROR; 384 } 385 386 if (addr == dev->ud_bus->ub_rhaddr) { 387 switch (ed->bEndpointAddress) { 388 case USB_CONTROL_ENDPOINT: 389 pipe->up_methods = &roothub_ctrl_methods; 390 break; 391 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 392 pipe->up_methods = &dwc2_root_intr_methods; 393 break; 394 default: 395 DPRINTF("bad bEndpointAddress 0x%02x\n", 396 ed->bEndpointAddress); 397 return USBD_INVAL; 398 } 399 DPRINTF("root hub pipe open\n"); 400 return USBD_NORMAL_COMPLETION; 401 } 402 403 switch (xfertype) { 404 case UE_CONTROL: 405 pipe->up_methods = &dwc2_device_ctrl_methods; 406 int err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 407 0, USBMALLOC_COHERENT, &dpipe->req_dma); 408 if (err) 409 return USBD_NOMEM; 410 break; 411 case UE_INTERRUPT: 412 pipe->up_methods = &dwc2_device_intr_methods; 413 break; 414 case UE_ISOCHRONOUS: 415 pipe->up_serialise = false; 416 pipe->up_methods = &dwc2_device_isoc_methods; 417 break; 418 case UE_BULK: 419 pipe->up_serialise = false; 420 pipe->up_methods = &dwc2_device_bulk_methods; 421 break; 422 default: 423 DPRINTF("bad xfer type %d\n", xfertype); 424 return USBD_INVAL; 425 } 426 427 /* QH */ 428 dpipe->priv = NULL; 429 430 return USBD_NORMAL_COMPLETION; 431 } 432 433 Static void 434 dwc2_poll(struct usbd_bus *bus) 435 { 436 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 437 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 438 439 mutex_spin_enter(&hsotg->lock); 440 dwc2_interrupt(sc); 441 mutex_spin_exit(&hsotg->lock); 442 } 443 444 /* 445 * Close a reqular pipe. 446 * Assumes that there are no pending transactions. 447 */ 448 Static void 449 dwc2_close_pipe(struct usbd_pipe *pipe) 450 { 451 struct dwc2_softc *sc __diagused = pipe->up_dev->ud_bus->ub_hcpriv; 452 453 KASSERT(mutex_owned(&sc->sc_lock)); 454 } 455 456 /* 457 * Abort a device request. 458 */ 459 Static void 460 dwc2_abortx(struct usbd_xfer *xfer) 461 { 462 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 463 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 464 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 465 struct dwc2_xfer *d; 466 int err; 467 468 DPRINTF("xfer %p pipe %p status 0x%08x", xfer, xfer->ux_pipe, 469 xfer->ux_status); 470 471 KASSERT(mutex_owned(&sc->sc_lock)); 472 ASSERT_SLEEPABLE(); 473 474 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 475 xfer->ux_status == USBD_TIMEOUT), 476 "bad abort status: %d", xfer->ux_status); 477 478 mutex_spin_enter(&hsotg->lock); 479 480 /* 481 * Check whether we aborted or timed out after the hardware 482 * completion interrupt determined that it's done but before 483 * the soft interrupt could actually complete it. If so, it's 484 * too late for the soft interrupt -- at this point we've 485 * already committed to abort it or time it out, so we need to 486 * take it off the softint's list of work in case the caller, 487 * say, frees the xfer before the softint runs. 488 * 489 * This logic is unusual among host controller drivers, and 490 * happens because dwc2 decides to complete xfers in the hard 491 * interrupt handler rather than in the soft interrupt handler, 492 * but usb_transfer_complete must be deferred to softint -- and 493 * we happened to swoop in between the hard interrupt and the 494 * soft interrupt. Other host controller drivers do almost all 495 * processing in the softint so there's no intermediate stage. 496 * 497 * Fortunately, this linear search to discern the intermediate 498 * stage is not likely to be a serious performance impact 499 * because it happens only on abort or timeout. 500 */ 501 TAILQ_FOREACH(d, &sc->sc_complete, xnext) { 502 if (d == dxfer) { 503 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 504 break; 505 } 506 } 507 508 /* 509 * If we're dying, skip the hardware action and just notify the 510 * software that we're done. 511 */ 512 if (sc->sc_dying) { 513 DPRINTFN(4, "xfer %p dying 0x%08x", xfer, xfer->ux_status); 514 goto dying; 515 } 516 517 /* 518 * HC Step 1: Handle the hardware. 519 */ 520 err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb); 521 if (err) { 522 DPRINTF("dwc2_hcd_urb_dequeue failed\n"); 523 } 524 525 dying: 526 mutex_spin_exit(&hsotg->lock); 527 528 /* 529 * Final Step: Notify completion to waiting xfers. 530 */ 531 usb_transfer_complete(xfer); 532 KASSERT(mutex_owned(&sc->sc_lock)); 533 } 534 535 Static void 536 dwc2_noop(struct usbd_pipe *pipe) 537 { 538 539 } 540 541 Static void 542 dwc2_device_clear_toggle(struct usbd_pipe *pipe) 543 { 544 545 DPRINTF("toggle %d -> 0", pipe->up_endpoint->ue_toggle); 546 } 547 548 /***********************************************************************/ 549 550 Static int 551 dwc2_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 552 void *buf, int buflen) 553 { 554 struct dwc2_softc *sc = bus->ub_hcpriv; 555 usbd_status err = USBD_IOERROR; 556 uint16_t len, value, index; 557 int totlen = 0; 558 559 if (sc->sc_dying) 560 return -1; 561 562 DPRINTFN(4, "type=0x%02x request=%02x\n", 563 req->bmRequestType, req->bRequest); 564 565 len = UGETW(req->wLength); 566 value = UGETW(req->wValue); 567 index = UGETW(req->wIndex); 568 569 #define C(x,y) ((x) | ((y) << 8)) 570 switch (C(req->bRequest, req->bmRequestType)) { 571 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 572 DPRINTFN(8, "wValue=0x%04x\n", value); 573 574 if (len == 0) 575 break; 576 switch (value) { 577 #define sd ((usb_string_descriptor_t *)buf) 578 case C(2, UDESC_STRING): 579 /* Product */ 580 totlen = usb_makestrdesc(sd, len, "DWC2 root hub"); 581 break; 582 #undef sd 583 default: 584 /* default from usbroothub */ 585 return buflen; 586 } 587 break; 588 589 case C(UR_GET_CONFIG, UT_READ_DEVICE): 590 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 591 case C(UR_GET_STATUS, UT_READ_INTERFACE): 592 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 593 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 594 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 595 /* default from usbroothub */ 596 DPRINTFN(4, "returning %d (usbroothub default)", buflen); 597 598 return buflen; 599 600 default: 601 /* Hub requests */ 602 err = dwc2_hcd_hub_control(sc->sc_hsotg, 603 C(req->bRequest, req->bmRequestType), value, index, 604 buf, len); 605 if (err) { 606 return -1; 607 } 608 totlen = len; 609 } 610 611 return totlen; 612 } 613 614 Static usbd_status 615 dwc2_root_intr_transfer(struct usbd_xfer *xfer) 616 { 617 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 618 usbd_status err; 619 620 DPRINTF("\n"); 621 622 /* Insert last in queue. */ 623 mutex_enter(&sc->sc_lock); 624 err = usb_insert_transfer(xfer); 625 mutex_exit(&sc->sc_lock); 626 if (err) 627 return err; 628 629 /* Pipe isn't running, start first */ 630 return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 631 } 632 633 Static usbd_status 634 dwc2_root_intr_start(struct usbd_xfer *xfer) 635 { 636 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 637 const bool polling = sc->sc_bus.ub_usepolling; 638 639 DPRINTF("\n"); 640 641 if (sc->sc_dying) 642 return USBD_IOERROR; 643 644 if (!polling) 645 mutex_enter(&sc->sc_lock); 646 KASSERT(sc->sc_intrxfer == NULL); 647 sc->sc_intrxfer = xfer; 648 xfer->ux_status = USBD_IN_PROGRESS; 649 if (!polling) 650 mutex_exit(&sc->sc_lock); 651 652 return USBD_IN_PROGRESS; 653 } 654 655 /* Abort a root interrupt request. */ 656 Static void 657 dwc2_root_intr_abort(struct usbd_xfer *xfer) 658 { 659 struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer); 660 661 DPRINTF("xfer=%p\n", xfer); 662 663 KASSERT(mutex_owned(&sc->sc_lock)); 664 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 665 666 /* If xfer has already completed, nothing to do here. */ 667 if (sc->sc_intrxfer == NULL) 668 return; 669 670 /* 671 * Otherwise, sc->sc_intrxfer had better be this transfer. 672 * Cancel it. 673 */ 674 KASSERT(sc->sc_intrxfer == xfer); 675 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 676 xfer->ux_status = USBD_CANCELLED; 677 usb_transfer_complete(xfer); 678 } 679 680 Static void 681 dwc2_root_intr_close(struct usbd_pipe *pipe) 682 { 683 struct dwc2_softc *sc __diagused = DWC2_PIPE2SC(pipe); 684 685 DPRINTF("\n"); 686 687 KASSERT(mutex_owned(&sc->sc_lock)); 688 689 /* 690 * Caller must guarantee the xfer has completed first, by 691 * closing the pipe only after normal completion or an abort. 692 */ 693 KASSERT(sc->sc_intrxfer == NULL); 694 } 695 696 Static void 697 dwc2_root_intr_done(struct usbd_xfer *xfer) 698 { 699 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 700 701 DPRINTF("\n"); 702 703 /* Claim the xfer so it doesn't get completed again. */ 704 KASSERT(sc->sc_intrxfer == xfer); 705 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 706 sc->sc_intrxfer = NULL; 707 } 708 709 /***********************************************************************/ 710 711 Static usbd_status 712 dwc2_device_ctrl_transfer(struct usbd_xfer *xfer) 713 { 714 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 715 usbd_status err; 716 717 DPRINTF("\n"); 718 719 /* Insert last in queue. */ 720 mutex_enter(&sc->sc_lock); 721 err = usb_insert_transfer(xfer); 722 mutex_exit(&sc->sc_lock); 723 if (err) 724 return err; 725 726 /* Pipe isn't running, start first */ 727 return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 728 } 729 730 Static usbd_status 731 dwc2_device_ctrl_start(struct usbd_xfer *xfer) 732 { 733 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 734 usbd_status err; 735 const bool polling = sc->sc_bus.ub_usepolling; 736 737 DPRINTF("\n"); 738 739 if (!polling) 740 mutex_enter(&sc->sc_lock); 741 xfer->ux_status = USBD_IN_PROGRESS; 742 err = dwc2_device_start(xfer); 743 if (!polling) 744 mutex_exit(&sc->sc_lock); 745 746 if (err) 747 return err; 748 749 return USBD_IN_PROGRESS; 750 } 751 752 Static void 753 dwc2_device_ctrl_abort(struct usbd_xfer *xfer) 754 { 755 struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer); 756 757 KASSERT(mutex_owned(&sc->sc_lock)); 758 759 DPRINTF("xfer=%p\n", xfer); 760 usbd_xfer_abort(xfer); 761 } 762 763 Static void 764 dwc2_device_ctrl_close(struct usbd_pipe *pipe) 765 { 766 struct dwc2_softc * const sc = DWC2_PIPE2SC(pipe); 767 struct dwc2_pipe * const dpipe = DWC2_PIPE2DPIPE(pipe); 768 769 DPRINTF("pipe=%p\n", pipe); 770 dwc2_close_pipe(pipe); 771 772 usb_freemem(&sc->sc_bus, &dpipe->req_dma); 773 } 774 775 Static void 776 dwc2_device_ctrl_done(struct usbd_xfer *xfer) 777 { 778 779 DPRINTF("xfer=%p\n", xfer); 780 } 781 782 /***********************************************************************/ 783 784 Static usbd_status 785 dwc2_device_bulk_transfer(struct usbd_xfer *xfer) 786 { 787 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 788 usbd_status err; 789 790 DPRINTF("xfer=%p\n", xfer); 791 792 /* Insert last in queue. */ 793 mutex_enter(&sc->sc_lock); 794 err = usb_insert_transfer(xfer); 795 796 KASSERT(err == USBD_NORMAL_COMPLETION); 797 798 xfer->ux_status = USBD_IN_PROGRESS; 799 err = dwc2_device_start(xfer); 800 mutex_exit(&sc->sc_lock); 801 802 return err; 803 } 804 805 Static void 806 dwc2_device_bulk_abort(struct usbd_xfer *xfer) 807 { 808 struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer); 809 810 KASSERT(mutex_owned(&sc->sc_lock)); 811 812 DPRINTF("xfer=%p\n", xfer); 813 usbd_xfer_abort(xfer); 814 } 815 816 Static void 817 dwc2_device_bulk_close(struct usbd_pipe *pipe) 818 { 819 820 DPRINTF("pipe=%p\n", pipe); 821 822 dwc2_close_pipe(pipe); 823 } 824 825 Static void 826 dwc2_device_bulk_done(struct usbd_xfer *xfer) 827 { 828 829 DPRINTF("xfer=%p\n", xfer); 830 } 831 832 /***********************************************************************/ 833 834 Static usbd_status 835 dwc2_device_intr_transfer(struct usbd_xfer *xfer) 836 { 837 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 838 usbd_status err; 839 840 DPRINTF("xfer=%p\n", xfer); 841 842 /* Insert last in queue. */ 843 mutex_enter(&sc->sc_lock); 844 err = usb_insert_transfer(xfer); 845 mutex_exit(&sc->sc_lock); 846 if (err) 847 return err; 848 849 /* Pipe isn't running, start first */ 850 return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 851 } 852 853 Static usbd_status 854 dwc2_device_intr_start(struct usbd_xfer *xfer) 855 { 856 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer) 857 struct usbd_device *dev = dpipe->pipe.up_dev; 858 struct dwc2_softc *sc = dev->ud_bus->ub_hcpriv; 859 usbd_status err; 860 const bool polling = sc->sc_bus.ub_usepolling; 861 862 if (!polling) 863 mutex_enter(&sc->sc_lock); 864 xfer->ux_status = USBD_IN_PROGRESS; 865 err = dwc2_device_start(xfer); 866 if (!polling) 867 mutex_exit(&sc->sc_lock); 868 869 if (err) 870 return err; 871 872 return USBD_IN_PROGRESS; 873 } 874 875 /* Abort a device interrupt request. */ 876 Static void 877 dwc2_device_intr_abort(struct usbd_xfer *xfer) 878 { 879 struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer); 880 881 KASSERT(mutex_owned(&sc->sc_lock)); 882 883 DPRINTF("xfer=%p\n", xfer); 884 usbd_xfer_abort(xfer); 885 } 886 887 Static void 888 dwc2_device_intr_close(struct usbd_pipe *pipe) 889 { 890 891 DPRINTF("pipe=%p\n", pipe); 892 893 dwc2_close_pipe(pipe); 894 } 895 896 Static void 897 dwc2_device_intr_done(struct usbd_xfer *xfer) 898 { 899 900 DPRINTF("\n"); 901 } 902 903 /***********************************************************************/ 904 905 usbd_status 906 dwc2_device_isoc_transfer(struct usbd_xfer *xfer) 907 { 908 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 909 usbd_status err; 910 911 DPRINTF("xfer=%p\n", xfer); 912 913 /* Insert last in queue. */ 914 mutex_enter(&sc->sc_lock); 915 err = usb_insert_transfer(xfer); 916 917 KASSERT(err == USBD_NORMAL_COMPLETION); 918 919 xfer->ux_status = USBD_IN_PROGRESS; 920 err = dwc2_device_start(xfer); 921 mutex_exit(&sc->sc_lock); 922 923 return err; 924 } 925 926 void 927 dwc2_device_isoc_abort(struct usbd_xfer *xfer) 928 { 929 struct dwc2_softc *sc __diagused = DWC2_XFER2SC(xfer); 930 KASSERT(mutex_owned(&sc->sc_lock)); 931 932 DPRINTF("xfer=%p\n", xfer); 933 usbd_xfer_abort(xfer); 934 } 935 936 void 937 dwc2_device_isoc_close(struct usbd_pipe *pipe) 938 { 939 DPRINTF("\n"); 940 941 dwc2_close_pipe(pipe); 942 } 943 944 void 945 dwc2_device_isoc_done(struct usbd_xfer *xfer) 946 { 947 948 DPRINTF("\n"); 949 } 950 951 952 usbd_status 953 dwc2_device_start(struct usbd_xfer *xfer) 954 { 955 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 956 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 957 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 958 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 959 struct dwc2_hcd_urb *dwc2_urb; 960 961 struct usbd_device *dev = xfer->ux_pipe->up_dev; 962 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 963 uint8_t addr = dev->ud_addr; 964 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 965 uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress); 966 uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 967 uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize)); 968 uint32_t len; 969 970 uint32_t flags = 0; 971 uint32_t off = 0; 972 int retval, err; 973 int alloc_bandwidth = 0; 974 975 DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->ux_pipe); 976 977 if (xfertype == UE_ISOCHRONOUS || 978 xfertype == UE_INTERRUPT) { 979 mutex_spin_enter(&hsotg->lock); 980 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer)) 981 alloc_bandwidth = 1; 982 mutex_spin_exit(&hsotg->lock); 983 } 984 985 /* 986 * For Control pipe the direction is from the request, all other 987 * transfers have been set correctly at pipe open time. 988 */ 989 if (xfertype == UE_CONTROL) { 990 usb_device_request_t *req = &xfer->ux_request; 991 992 DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x " 993 "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d " 994 "mps=%d\n", 995 xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue), 996 UGETW(req->wIndex), UGETW(req->wLength), dev->ud_addr, 997 epnum, dir == UT_READ ? "in" :"out", dev->ud_speed, mps); 998 999 /* Copy request packet to our DMA buffer */ 1000 memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req)); 1001 usb_syncmem(&dpipe->req_dma, 0, sizeof(*req), 1002 BUS_DMASYNC_PREWRITE); 1003 len = UGETW(req->wLength); 1004 if ((req->bmRequestType & UT_READ) == UT_READ) { 1005 dir = UE_DIR_IN; 1006 } else { 1007 dir = UE_DIR_OUT; 1008 } 1009 1010 DPRINTFN(3, "req = %p dma = %" PRIxBUSADDR " len %d dir %s\n", 1011 KERNADDR(&dpipe->req_dma, 0), DMAADDR(&dpipe->req_dma, 0), 1012 len, dir == UE_DIR_IN ? "in" : "out"); 1013 } else if (xfertype == UE_ISOCHRONOUS) { 1014 DPRINTFN(3, "xfer=%p nframes=%d flags=%d addr=%d endpt=%d," 1015 " mps=%d dir %s\n", xfer, xfer->ux_nframes, xfer->ux_flags, addr, 1016 epnum, mps, dir == UT_READ ? "in" :"out"); 1017 1018 #ifdef DIAGNOSTIC 1019 len = 0; 1020 for (size_t i = 0; i < xfer->ux_nframes; i++) 1021 len += xfer->ux_frlengths[i]; 1022 if (len != xfer->ux_length) 1023 panic("len (%d) != xfer->ux_length (%d)", len, 1024 xfer->ux_length); 1025 #endif 1026 len = xfer->ux_length; 1027 } else { 1028 DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d," 1029 " mps=%d dir %s\n", xfer, xfer->ux_length, xfer->ux_flags, addr, 1030 epnum, mps, dir == UT_READ ? "in" :"out"); 1031 1032 len = xfer->ux_length; 1033 } 1034 1035 dwc2_urb = dxfer->urb; 1036 if (!dwc2_urb) 1037 return USBD_NOMEM; 1038 1039 KASSERT(dwc2_urb->packet_count == xfer->ux_nframes); 1040 memset(dwc2_urb, 0, sizeof(*dwc2_urb) + 1041 sizeof(dwc2_urb->iso_descs[0]) * dwc2_urb->packet_count); 1042 1043 dwc2_urb->priv = xfer; 1044 dwc2_urb->packet_count = xfer->ux_nframes; 1045 1046 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir, 1047 mps); 1048 1049 if (xfertype == UE_CONTROL) { 1050 dwc2_urb->setup_usbdma = &dpipe->req_dma; 1051 dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0); 1052 dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0); 1053 } else { 1054 /* XXXNH - % mps required? */ 1055 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0) 1056 flags |= URB_SEND_ZERO_PACKET; 1057 } 1058 flags |= URB_GIVEBACK_ASAP; 1059 1060 /* 1061 * control transfers with no data phase don't touch usbdma, but 1062 * everything else does. 1063 */ 1064 if (!(xfertype == UE_CONTROL && len == 0)) { 1065 dwc2_urb->usbdma = &xfer->ux_dmabuf; 1066 dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0); 1067 dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0); 1068 1069 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1070 dir == UE_DIR_IN ? 1071 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1072 } 1073 dwc2_urb->length = len; 1074 dwc2_urb->flags = flags; 1075 dwc2_urb->status = -EINPROGRESS; 1076 1077 if (xfertype == UE_INTERRUPT || 1078 xfertype == UE_ISOCHRONOUS) { 1079 uint16_t ival; 1080 1081 if (xfertype == UE_INTERRUPT && 1082 dpipe->pipe.up_interval != USBD_DEFAULT_INTERVAL) { 1083 ival = dpipe->pipe.up_interval; 1084 } else { 1085 ival = ed->bInterval; 1086 } 1087 1088 if (ival < 1) { 1089 retval = -ENODEV; 1090 goto fail; 1091 } 1092 if (dev->ud_speed == USB_SPEED_HIGH || 1093 (dev->ud_speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) { 1094 if (ival > 16) { 1095 /* 1096 * illegal with HS/FS, but there were 1097 * documentation bugs in the spec 1098 */ 1099 ival = 256; 1100 } else { 1101 ival = (1 << (ival - 1)); 1102 } 1103 } else { 1104 if (xfertype == UE_INTERRUPT && ival < 10) 1105 ival = 10; 1106 } 1107 dwc2_urb->interval = ival; 1108 } 1109 1110 /* XXXNH bring down from callers?? */ 1111 // mutex_enter(&sc->sc_lock); 1112 1113 xfer->ux_actlen = 0; 1114 1115 KASSERT(xfertype != UE_ISOCHRONOUS || 1116 xfer->ux_nframes <= dwc2_urb->packet_count); 1117 KASSERTMSG(xfer->ux_nframes == 0 || xfertype == UE_ISOCHRONOUS, 1118 "nframes %d xfertype %d\n", xfer->ux_nframes, xfertype); 1119 1120 off = 0; 1121 for (size_t i = 0; i < xfer->ux_nframes; ++i) { 1122 DPRINTFN(3, "xfer=%p frame=%zd offset=%d length=%d\n", xfer, i, 1123 off, xfer->ux_frlengths[i]); 1124 1125 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off, 1126 xfer->ux_frlengths[i]); 1127 off += xfer->ux_frlengths[i]; 1128 } 1129 1130 struct dwc2_qh *qh = dpipe->priv; 1131 struct dwc2_qtd *qtd; 1132 bool qh_allocated = false; 1133 1134 /* Create QH for the endpoint if it doesn't exist */ 1135 if (!qh) { 1136 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, GFP_ATOMIC); 1137 if (!qh) { 1138 retval = -ENOMEM; 1139 goto fail; 1140 } 1141 dpipe->priv = qh; 1142 qh_allocated = true; 1143 } 1144 1145 qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT); 1146 if (!qtd) { 1147 retval = -ENOMEM; 1148 goto fail1; 1149 } 1150 memset(qtd, 0, sizeof(*qtd)); 1151 1152 /* might need to check cpu_intr_p */ 1153 mutex_spin_enter(&hsotg->lock); 1154 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 1155 if (retval) 1156 goto fail2; 1157 usbd_xfer_schedule_timeout(xfer); 1158 xfer->ux_status = USBD_IN_PROGRESS; 1159 1160 if (alloc_bandwidth) { 1161 dwc2_allocate_bus_bandwidth(hsotg, 1162 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1163 xfer); 1164 } 1165 1166 mutex_spin_exit(&hsotg->lock); 1167 // mutex_exit(&sc->sc_lock); 1168 1169 return USBD_IN_PROGRESS; 1170 1171 fail2: 1172 dwc2_urb->priv = NULL; 1173 mutex_spin_exit(&hsotg->lock); 1174 pool_cache_put(sc->sc_qtdpool, qtd); 1175 1176 fail1: 1177 if (qh_allocated) { 1178 dpipe->priv = NULL; 1179 dwc2_hcd_qh_free(hsotg, qh); 1180 } 1181 fail: 1182 1183 switch (retval) { 1184 case -EINVAL: 1185 case -ENODEV: 1186 err = USBD_INVAL; 1187 break; 1188 case -ENOMEM: 1189 err = USBD_NOMEM; 1190 break; 1191 default: 1192 err = USBD_IOERROR; 1193 } 1194 1195 return err; 1196 1197 } 1198 1199 int dwc2_intr(void *p) 1200 { 1201 struct dwc2_softc *sc = p; 1202 struct dwc2_hsotg *hsotg; 1203 int ret = 0; 1204 1205 if (sc == NULL) 1206 return 0; 1207 1208 hsotg = sc->sc_hsotg; 1209 mutex_spin_enter(&hsotg->lock); 1210 1211 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1212 goto done; 1213 1214 if (sc->sc_bus.ub_usepolling) { 1215 uint32_t intrs; 1216 1217 intrs = dwc2_read_core_intr(hsotg); 1218 DWC2_WRITE_4(hsotg, GINTSTS, intrs); 1219 } else { 1220 ret = dwc2_interrupt(sc); 1221 } 1222 1223 done: 1224 mutex_spin_exit(&hsotg->lock); 1225 1226 return ret; 1227 } 1228 1229 int 1230 dwc2_interrupt(struct dwc2_softc *sc) 1231 { 1232 int ret = 0; 1233 1234 if (sc->sc_hcdenabled) { 1235 ret |= dwc2_handle_hcd_intr(sc->sc_hsotg); 1236 } 1237 1238 ret |= dwc2_handle_common_intr(sc->sc_hsotg); 1239 1240 return ret; 1241 } 1242 1243 /***********************************************************************/ 1244 1245 int 1246 dwc2_detach(struct dwc2_softc *sc, int flags) 1247 { 1248 int rv = 0; 1249 1250 if (sc->sc_child != NULL) 1251 rv = config_detach(sc->sc_child, flags); 1252 1253 return rv; 1254 } 1255 1256 bool 1257 dwc2_shutdown(device_t self, int flags) 1258 { 1259 struct dwc2_softc *sc = device_private(self); 1260 1261 sc = sc; 1262 1263 return true; 1264 } 1265 1266 void 1267 dwc2_childdet(device_t self, device_t child) 1268 { 1269 struct dwc2_softc *sc = device_private(self); 1270 1271 sc = sc; 1272 } 1273 1274 int 1275 dwc2_activate(device_t self, enum devact act) 1276 { 1277 struct dwc2_softc *sc = device_private(self); 1278 1279 sc = sc; 1280 1281 return 0; 1282 } 1283 1284 bool 1285 dwc2_resume(device_t dv, const pmf_qual_t *qual) 1286 { 1287 struct dwc2_softc *sc = device_private(dv); 1288 1289 sc = sc; 1290 1291 return true; 1292 } 1293 1294 bool 1295 dwc2_suspend(device_t dv, const pmf_qual_t *qual) 1296 { 1297 struct dwc2_softc *sc = device_private(dv); 1298 1299 sc = sc; 1300 1301 return true; 1302 } 1303 1304 /***********************************************************************/ 1305 int 1306 dwc2_init(struct dwc2_softc *sc) 1307 { 1308 int err = 0; 1309 1310 err = linux_workqueue_init(); 1311 if (err) 1312 return err; 1313 1314 sc->sc_bus.ub_hcpriv = sc; 1315 sc->sc_bus.ub_revision = USBREV_2_0; 1316 sc->sc_bus.ub_methods = &dwc2_bus_methods; 1317 sc->sc_bus.ub_pipesize = sizeof(struct dwc2_pipe); 1318 sc->sc_bus.ub_usedma = true; 1319 sc->sc_hcdenabled = false; 1320 1321 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1322 1323 TAILQ_INIT(&sc->sc_complete); 1324 1325 sc->sc_rhc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 1326 dwc2_rhc, sc); 1327 1328 sc->sc_xferpool = pool_cache_init(sizeof(struct dwc2_xfer), 0, 0, 0, 1329 "dwc2xfer", NULL, IPL_USB, NULL, NULL, NULL); 1330 sc->sc_qhpool = pool_cache_init(sizeof(struct dwc2_qh), 0, 0, 0, 1331 "dwc2qh", NULL, IPL_USB, NULL, NULL, NULL); 1332 sc->sc_qtdpool = pool_cache_init(sizeof(struct dwc2_qtd), 0, 0, 0, 1333 "dwc2qtd", NULL, IPL_USB, NULL, NULL, NULL); 1334 1335 sc->sc_hsotg = kmem_zalloc(sizeof(struct dwc2_hsotg), KM_SLEEP); 1336 sc->sc_hsotg->hsotg_sc = sc; 1337 sc->sc_hsotg->dev = sc->sc_dev; 1338 sc->sc_hcdenabled = true; 1339 1340 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1341 struct dwc2_core_params defparams; 1342 int retval; 1343 1344 if (sc->sc_params == NULL) { 1345 /* Default all params to autodetect */ 1346 dwc2_set_all_params(&defparams, -1); 1347 sc->sc_params = &defparams; 1348 1349 /* 1350 * Disable descriptor dma mode by default as the HW can support 1351 * it, but does not support it for SPLIT transactions. 1352 */ 1353 defparams.dma_desc_enable = 0; 1354 } 1355 hsotg->dr_mode = USB_DR_MODE_HOST; 1356 1357 /* Detect config values from hardware */ 1358 retval = dwc2_get_hwparams(hsotg); 1359 if (retval) { 1360 goto fail2; 1361 } 1362 1363 hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP); 1364 dwc2_set_all_params(hsotg->core_params, -1); 1365 1366 /* Validate parameter values */ 1367 dwc2_set_parameters(hsotg, sc->sc_params); 1368 1369 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1370 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1371 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 1372 retval = dwc2_gadget_init(hsotg); 1373 if (retval) 1374 goto fail2; 1375 hsotg->gadget_enabled = 1; 1376 } 1377 #endif 1378 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \ 1379 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1380 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 1381 retval = dwc2_hcd_init(hsotg); 1382 if (retval) { 1383 if (hsotg->gadget_enabled) 1384 dwc2_hsotg_remove(hsotg); 1385 goto fail2; 1386 } 1387 hsotg->hcd_enabled = 1; 1388 } 1389 #endif 1390 1391 uint32_t snpsid = hsotg->hw_params.snpsid; 1392 aprint_verbose_dev(sc->sc_dev, "Core Release: %x.%x%x%x (snpsid=%x)\n", 1393 snpsid >> 12 & 0xf, snpsid >> 8 & 0xf, 1394 snpsid >> 4 & 0xf, snpsid & 0xf, snpsid); 1395 1396 return 0; 1397 1398 fail2: 1399 err = -retval; 1400 kmem_free(sc->sc_hsotg, sizeof(struct dwc2_hsotg)); 1401 softint_disestablish(sc->sc_rhc_si); 1402 1403 return err; 1404 } 1405 1406 #if 0 1407 /* 1408 * curmode is a mode indication bit 0 = device, 1 = host 1409 */ 1410 static const char * const intnames[32] = { 1411 "curmode", "modemis", "otgint", "sof", 1412 "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff", 1413 "ulpickint", "i2cint", "erlysusp", "usbsusp", 1414 "usbrst", "enumdone", "isooutdrop", "eopf", 1415 "restore_done", "epmis", "iepint", "oepint", 1416 "incompisoin", "incomplp", "fetsusp", "resetdet", 1417 "prtint", "hchint", "ptxfemp", "lpm", 1418 "conidstschng", "disconnint", "sessreqint", "wkupint" 1419 }; 1420 1421 1422 /***********************************************************************/ 1423 1424 #endif 1425 1426 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 1427 int *hub_port) 1428 { 1429 struct usbd_xfer *xfer = context; 1430 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1431 struct usbd_device *dev = dpipe->pipe.up_dev; 1432 1433 *hub_addr = dev->ud_myhsport->up_parent->ud_addr; 1434 *hub_port = dev->ud_myhsport->up_portno; 1435 } 1436 1437 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 1438 { 1439 struct usbd_xfer *xfer = context; 1440 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1441 struct usbd_device *dev = dpipe->pipe.up_dev; 1442 1443 return dev->ud_speed; 1444 } 1445 1446 /* 1447 * Sets the final status of an URB and returns it to the upper layer. Any 1448 * required cleanup of the URB is performed. 1449 * 1450 * Must be called with interrupt disabled and spinlock held 1451 */ 1452 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 1453 int status) 1454 { 1455 struct usbd_xfer *xfer; 1456 struct dwc2_xfer *dxfer; 1457 struct dwc2_softc *sc; 1458 usb_endpoint_descriptor_t *ed; 1459 uint8_t xfertype; 1460 1461 KASSERT(mutex_owned(&hsotg->lock)); 1462 1463 if (!qtd) { 1464 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 1465 return; 1466 } 1467 1468 if (!qtd->urb) { 1469 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 1470 return; 1471 } 1472 1473 xfer = qtd->urb->priv; 1474 if (!xfer) { 1475 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 1476 return; 1477 } 1478 1479 dxfer = DWC2_XFER2DXFER(xfer); 1480 sc = DWC2_XFER2SC(xfer); 1481 ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1482 xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1483 1484 struct dwc2_hcd_urb *urb = qtd->urb; 1485 xfer->ux_actlen = dwc2_hcd_urb_get_actual_length(urb); 1486 1487 DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->ux_actlen); 1488 1489 if (xfertype == UE_ISOCHRONOUS) { 1490 xfer->ux_actlen = 0; 1491 for (size_t i = 0; i < xfer->ux_nframes; ++i) { 1492 xfer->ux_frlengths[i] = 1493 dwc2_hcd_urb_get_iso_desc_actual_length( 1494 urb, i); 1495 DPRINTFN(1, "xfer=%p frame=%zu length=%d\n", xfer, i, 1496 xfer->ux_frlengths[i]); 1497 xfer->ux_actlen += xfer->ux_frlengths[i]; 1498 } 1499 DPRINTFN(1, "xfer=%p actlen=%d (isoc)\n", xfer, xfer->ux_actlen); 1500 } 1501 1502 if (xfertype == UE_ISOCHRONOUS && dbg_perio()) { 1503 for (size_t i = 0; i < xfer->ux_nframes; i++) 1504 dev_vdbg(hsotg->dev, " ISO Desc %zu status %d\n", 1505 i, urb->iso_descs[i].status); 1506 } 1507 1508 if (!status) { 1509 if (!(xfer->ux_flags & USBD_SHORT_XFER_OK) && 1510 xfer->ux_actlen < xfer->ux_length) 1511 status = -EIO; 1512 } 1513 1514 switch (status) { 1515 case 0: 1516 dxfer->intr_status = USBD_NORMAL_COMPLETION; 1517 break; 1518 case -EPIPE: 1519 dxfer->intr_status = USBD_STALLED; 1520 break; 1521 case -EPROTO: 1522 dxfer->intr_status = USBD_INVAL; 1523 break; 1524 case -EIO: 1525 dxfer->intr_status = USBD_IOERROR; 1526 break; 1527 case -EOVERFLOW: 1528 dxfer->intr_status = USBD_IOERROR; 1529 break; 1530 default: 1531 dxfer->intr_status = USBD_IOERROR; 1532 printf("%s: unknown error status %d\n", __func__, status); 1533 } 1534 1535 if (dxfer->intr_status == USBD_NORMAL_COMPLETION) { 1536 /* 1537 * control transfers with no data phase don't touch dmabuf, but 1538 * everything else does. 1539 */ 1540 if (!(xfertype == UE_CONTROL && 1541 UGETW(xfer->ux_request.wLength) == 0) && 1542 xfer->ux_actlen > 0 /* XXX PR/53503 */ 1543 ) { 1544 int rd = usbd_xfer_isread(xfer); 1545 1546 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_actlen, 1547 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1548 } 1549 } 1550 1551 if (xfertype == UE_ISOCHRONOUS || 1552 xfertype == UE_INTERRUPT) { 1553 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1554 1555 dwc2_free_bus_bandwidth(hsotg, 1556 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1557 xfer); 1558 } 1559 1560 qtd->urb = NULL; 1561 KASSERT(mutex_owned(&hsotg->lock)); 1562 1563 TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext); 1564 1565 mutex_spin_exit(&hsotg->lock); 1566 usb_schedsoftintr(&sc->sc_bus); 1567 mutex_spin_enter(&hsotg->lock); 1568 } 1569 1570 1571 int 1572 _dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1573 { 1574 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 1575 1576 mutex_spin_enter(&hsotg->lock); 1577 1578 hsotg->lx_state = DWC2_L0; 1579 1580 if (dwc2_is_device_mode(hsotg)) { 1581 mutex_spin_exit(&hsotg->lock); 1582 return 0; /* why 0 ?? */ 1583 } 1584 1585 dwc2_hcd_reinit(hsotg); 1586 1587 mutex_spin_exit(&hsotg->lock); 1588 return 0; 1589 } 1590 1591 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1592 { 1593 1594 return false; 1595 } 1596