1 /* 2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the functions to manage Queue Heads and Queue 39 * Transfer Descriptors for Host mode 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcdqueue.c,v 1.2 2013/09/05 20:25:27 skrll Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/kmem.h> 47 #include <sys/pool.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 #include <dev/usb/usbdivar.h> 52 #include <dev/usb/usb_mem.h> 53 54 #include <machine/param.h> 55 56 #include <linux/kernel.h> 57 58 #include <dwc2/dwc2.h> 59 #include <dwc2/dwc2var.h> 60 61 #include "dwc2_core.h" 62 #include "dwc2_hcd.h" 63 64 static u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int); 65 66 /** 67 * dwc2_qh_init() - Initializes a QH structure 68 * 69 * @hsotg: The HCD state structure for the DWC OTG controller 70 * @qh: The QH to init 71 * @urb: Holds the information about the device/endpoint needed to initialize 72 * the QH 73 */ 74 #define SCHEDULE_SLOP 10 75 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 76 struct dwc2_hcd_urb *urb) 77 { 78 int dev_speed, hub_addr, hub_port; 79 const char *speed, *type; 80 81 dev_vdbg(hsotg->dev, "%s()\n", __func__); 82 83 /* Initialize QH */ 84 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 85 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 86 87 qh->data_toggle = DWC2_HC_PID_DATA0; 88 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 89 INIT_LIST_HEAD(&qh->qtd_list); 90 INIT_LIST_HEAD(&qh->qh_list_entry); 91 92 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 93 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 94 95 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 96 qh->nak_frame = 0xffff; 97 98 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 99 hub_addr != 0 && hub_addr != 1) { 100 dev_vdbg(hsotg->dev, 101 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 102 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 103 hub_port); 104 qh->do_split = 1; 105 } 106 107 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 108 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 109 /* Compute scheduling parameters once and save them */ 110 u32 hprt, prtspd; 111 112 /* Todo: Account for split transfers in the bus time */ 113 int bytecount = 114 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 115 116 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ? 117 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 118 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 119 bytecount); 120 /* Start in a slightly future (micro)frame */ 121 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 122 SCHEDULE_SLOP); 123 qh->interval = urb->interval; 124 #if 0 125 /* Increase interrupt polling rate for debugging */ 126 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 127 qh->interval = 8; 128 #endif 129 hprt = DWC2_READ_4(hsotg, HPRT0); 130 prtspd = hprt & HPRT0_SPD_MASK; 131 if (prtspd == HPRT0_SPD_HIGH_SPEED && 132 (dev_speed == USB_SPEED_LOW || 133 dev_speed == USB_SPEED_FULL)) { 134 qh->interval *= 8; 135 qh->sched_frame |= 0x7; 136 qh->start_split_frame = qh->sched_frame; 137 } 138 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 139 } 140 141 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 142 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 143 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 144 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 145 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 146 dwc2_hcd_get_ep_num(&urb->pipe_info), 147 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 148 149 qh->dev_speed = dev_speed; 150 151 switch (dev_speed) { 152 case USB_SPEED_LOW: 153 speed = "low"; 154 break; 155 case USB_SPEED_FULL: 156 speed = "full"; 157 break; 158 case USB_SPEED_HIGH: 159 speed = "high"; 160 break; 161 default: 162 speed = "?"; 163 break; 164 } 165 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 166 167 switch (qh->ep_type) { 168 case USB_ENDPOINT_XFER_ISOC: 169 type = "isochronous"; 170 break; 171 case USB_ENDPOINT_XFER_INT: 172 type = "interrupt"; 173 break; 174 case USB_ENDPOINT_XFER_CONTROL: 175 type = "control"; 176 break; 177 case USB_ENDPOINT_XFER_BULK: 178 type = "bulk"; 179 break; 180 default: 181 type = "?"; 182 break; 183 } 184 185 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 186 187 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 188 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 189 qh->usecs); 190 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 191 qh->interval); 192 } 193 } 194 195 /** 196 * dwc2_hcd_qh_create() - Allocates and initializes a QH 197 * 198 * @hsotg: The HCD state structure for the DWC OTG controller 199 * @urb: Holds the information about the device/endpoint needed 200 * to initialize the QH 201 * @atomic_alloc: Flag to do atomic allocation if needed 202 * 203 * Return: Pointer to the newly allocated QH, or NULL on error 204 */ 205 static struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 206 struct dwc2_hcd_urb *urb, 207 gfp_t mem_flags) 208 { 209 struct dwc2_softc *sc = hsotg->hsotg_sc; 210 struct dwc2_qh *qh; 211 212 if (!urb->priv) 213 return NULL; 214 215 /* Allocate memory */ 216 qh = pool_cache_get(sc->sc_qhpool, PR_NOWAIT); 217 if (!qh) 218 return NULL; 219 220 memset(qh, 0, sizeof(*qh)); 221 dwc2_qh_init(hsotg, qh, urb); 222 223 if (hsotg->core_params->dma_desc_enable > 0 && 224 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 225 dwc2_hcd_qh_free(hsotg, qh); 226 return NULL; 227 } 228 229 return qh; 230 } 231 232 /** 233 * dwc2_hcd_qh_free() - Frees the QH 234 * 235 * @hsotg: HCD instance 236 * @qh: The QH to free 237 * 238 * QH should already be removed from the list. QTD list should already be empty 239 * if called from URB Dequeue. 240 * 241 * Must NOT be called with interrupt disabled or spinlock held 242 */ 243 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 244 { 245 struct dwc2_softc *sc = hsotg->hsotg_sc; 246 u32 buf_size; 247 248 if (hsotg->core_params->dma_desc_enable > 0) { 249 dwc2_hcd_qh_free_ddma(hsotg, qh); 250 } else if (qh->dw_align_buf) { 251 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC) 252 buf_size = 4096; 253 else 254 buf_size = hsotg->core_params->max_transfer_size; 255 /* XXXNH */ 256 usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->dw_align_buf_usbdma); 257 } 258 259 pool_cache_put(sc->sc_qhpool, qh); 260 } 261 262 /** 263 * dwc2_periodic_channel_available() - Checks that a channel is available for a 264 * periodic transfer 265 * 266 * @hsotg: The HCD state structure for the DWC OTG controller 267 * 268 * Return: 0 if successful, negative error code otherise 269 */ 270 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 271 { 272 /* 273 * Currently assuming that there is a dedicated host channnel for 274 * each periodic transaction plus at least one host channel for 275 * non-periodic transactions 276 */ 277 int status; 278 int num_channels; 279 280 num_channels = hsotg->core_params->host_channels; 281 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 282 num_channels 283 && hsotg->periodic_channels < num_channels - 1) { 284 status = 0; 285 } else { 286 dev_dbg(hsotg->dev, 287 "%s: Total channels: %d, Periodic: %d, " 288 "Non-periodic: %d\n", __func__, num_channels, 289 hsotg->periodic_channels, hsotg->non_periodic_channels); 290 status = -ENOSPC; 291 } 292 293 return status; 294 } 295 296 /** 297 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 298 * for the specified QH in the periodic schedule 299 * 300 * @hsotg: The HCD state structure for the DWC OTG controller 301 * @qh: QH containing periodic bandwidth required 302 * 303 * Return: 0 if successful, negative error code otherwise 304 * 305 * For simplicity, this calculation assumes that all the transfers in the 306 * periodic schedule may occur in the same (micro)frame 307 */ 308 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 309 struct dwc2_qh *qh) 310 { 311 int status; 312 s16 max_claimed_usecs; 313 314 status = 0; 315 316 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 317 /* 318 * High speed mode 319 * Max periodic usecs is 80% x 125 usec = 100 usec 320 */ 321 max_claimed_usecs = 100 - qh->usecs; 322 } else { 323 /* 324 * Full speed mode 325 * Max periodic usecs is 90% x 1000 usec = 900 usec 326 */ 327 max_claimed_usecs = 900 - qh->usecs; 328 } 329 330 if (hsotg->periodic_usecs > max_claimed_usecs) { 331 dev_err(hsotg->dev, 332 "%s: already claimed usecs %d, required usecs %d\n", 333 __func__, hsotg->periodic_usecs, qh->usecs); 334 status = -ENOSPC; 335 } 336 337 return status; 338 } 339 340 /** 341 * Microframe scheduler 342 * track the total use in hsotg->frame_usecs 343 * keep each qh use in qh->frame_usecs 344 * when surrendering the qh then donate the time back 345 */ 346 static const unsigned short max_uframe_usecs[] = { 347 100, 100, 100, 100, 100, 100, 30, 0 348 }; 349 350 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 351 { 352 int i; 353 354 for (i = 0; i < 8; i++) 355 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 356 } 357 358 static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 359 { 360 unsigned short utime = qh->usecs; 361 int done = 0; 362 int i = 0; 363 int ret = -1; 364 365 while (!done) { 366 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 367 if (utime <= hsotg->frame_usecs[i]) { 368 hsotg->frame_usecs[i] -= utime; 369 qh->frame_usecs[i] += utime; 370 ret = i; 371 done = 1; 372 } else { 373 i++; 374 if (i == 8) 375 done = 1; 376 } 377 } 378 379 return ret; 380 } 381 382 /* 383 * use this for FS apps that can span multiple uframes 384 */ 385 static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 386 { 387 unsigned short utime = qh->usecs; 388 unsigned short xtime; 389 int t_left = utime; 390 int done = 0; 391 int i = 0; 392 int j; 393 int ret = -1; 394 395 while (!done) { 396 if (hsotg->frame_usecs[i] <= 0) { 397 i++; 398 if (i == 8) { 399 ret = -1; 400 done = 1; 401 } 402 continue; 403 } 404 405 /* 406 * we need n consecutive slots so use j as a start slot 407 * j plus j+1 must be enough time (for now) 408 */ 409 xtime = hsotg->frame_usecs[i]; 410 for (j = i + 1; j < 8; j++) { 411 /* 412 * if we add this frame remaining time to xtime we may 413 * be OK, if not we need to test j for a complete frame 414 */ 415 if (xtime + hsotg->frame_usecs[j] < utime) { 416 if (hsotg->frame_usecs[j] < 417 max_uframe_usecs[j]) { 418 ret = -1; 419 break; 420 } 421 } 422 if (xtime >= utime) { 423 ret = i; 424 break; 425 } 426 /* add the frame time to x time */ 427 xtime += hsotg->frame_usecs[j]; 428 /* we must have a fully available next frame or break */ 429 if (xtime < utime && 430 hsotg->frame_usecs[j] == max_uframe_usecs[j]) { 431 ret = -1; 432 break; 433 } 434 } 435 if (ret >= 0) { 436 t_left = utime; 437 for (j = i; t_left > 0 && j < 8; j++) { 438 t_left -= hsotg->frame_usecs[j]; 439 if (t_left <= 0) { 440 qh->frame_usecs[j] += 441 hsotg->frame_usecs[j] + t_left; 442 hsotg->frame_usecs[j] = -t_left; 443 ret = i; 444 done = 1; 445 } else { 446 qh->frame_usecs[j] += 447 hsotg->frame_usecs[j]; 448 hsotg->frame_usecs[j] = 0; 449 } 450 } 451 } else { 452 i++; 453 if (i == 8) { 454 ret = -1; 455 done = 1; 456 } 457 } 458 } 459 460 return ret; 461 } 462 463 static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 464 { 465 int ret; 466 467 if (qh->dev_speed == USB_SPEED_HIGH) { 468 /* if this is a hs transaction we need a full frame */ 469 ret = dwc2_find_single_uframe(hsotg, qh); 470 } else { 471 /* 472 * if this is a fs transaction we may need a sequence 473 * of frames 474 */ 475 ret = dwc2_find_multi_uframe(hsotg, qh); 476 } 477 return ret; 478 } 479 480 /** 481 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 482 * host channel is large enough to handle the maximum data transfer in a single 483 * (micro)frame for a periodic transfer 484 * 485 * @hsotg: The HCD state structure for the DWC OTG controller 486 * @qh: QH for a periodic endpoint 487 * 488 * Return: 0 if successful, negative error code otherwise 489 */ 490 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 491 struct dwc2_qh *qh) 492 { 493 u32 max_xfer_size; 494 u32 max_channel_xfer_size; 495 int status = 0; 496 497 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 498 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 499 500 if (max_xfer_size > max_channel_xfer_size) { 501 dev_err(hsotg->dev, 502 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 503 __func__, max_xfer_size, max_channel_xfer_size); 504 status = -ENOSPC; 505 } 506 507 return status; 508 } 509 510 /** 511 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 512 * the periodic schedule 513 * 514 * @hsotg: The HCD state structure for the DWC OTG controller 515 * @qh: QH for the periodic transfer. The QH should already contain the 516 * scheduling information. 517 * 518 * Return: 0 if successful, negative error code otherwise 519 */ 520 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 521 { 522 int status; 523 524 if (hsotg->core_params->uframe_sched > 0) { 525 int frame = -1; 526 527 status = dwc2_find_uframe(hsotg, qh); 528 if (status == 0) 529 frame = 7; 530 else if (status > 0) 531 frame = status - 1; 532 533 /* Set the new frame up */ 534 if (frame > -1) { 535 qh->sched_frame &= ~0x7; 536 qh->sched_frame |= (frame & 7); 537 } 538 539 if (status != -1) 540 status = 0; 541 } else { 542 status = dwc2_periodic_channel_available(hsotg); 543 if (status) { 544 dev_info(hsotg->dev, 545 "%s: No host channel available for periodic transfer\n", 546 __func__); 547 return status; 548 } 549 550 status = dwc2_check_periodic_bandwidth(hsotg, qh); 551 } 552 553 if (status) { 554 dev_dbg(hsotg->dev, 555 "%s: Insufficient periodic bandwidth for periodic transfer\n", 556 __func__); 557 return status; 558 } 559 560 status = dwc2_check_max_xfer_size(hsotg, qh); 561 if (status) { 562 dev_dbg(hsotg->dev, 563 "%s: Channel max transfer size too small for periodic transfer\n", 564 __func__); 565 return status; 566 } 567 568 if (hsotg->core_params->dma_desc_enable > 0) { 569 /* Don't rely on SOF and start in ready schedule */ 570 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 571 dev_dbg(hsotg->dev, "periodic_sched_ready\n"); 572 } else { 573 if (list_empty(&hsotg->periodic_sched_inactive) || 574 dwc2_frame_num_le(qh->sched_frame, hsotg->next_sched_frame)) 575 hsotg->next_sched_frame = qh->sched_frame; 576 577 /* Always start in inactive schedule */ 578 list_add_tail(&qh->qh_list_entry, 579 &hsotg->periodic_sched_inactive); 580 } 581 582 if (hsotg->core_params->uframe_sched <= 0) 583 /* Reserve periodic channel */ 584 hsotg->periodic_channels++; 585 586 /* Update claimed usecs per (micro)frame */ 587 hsotg->periodic_usecs += qh->usecs; 588 589 return status; 590 } 591 592 /** 593 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 594 * from the periodic schedule 595 * 596 * @hsotg: The HCD state structure for the DWC OTG controller 597 * @qh: QH for the periodic transfer 598 */ 599 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 600 struct dwc2_qh *qh) 601 { 602 int i; 603 604 list_del_init(&qh->qh_list_entry); 605 606 /* Update claimed usecs per (micro)frame */ 607 hsotg->periodic_usecs -= qh->usecs; 608 609 if (hsotg->core_params->uframe_sched > 0) { 610 for (i = 0; i < 8; i++) { 611 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 612 qh->frame_usecs[i] = 0; 613 } 614 } else { 615 /* Release periodic channel reservation */ 616 hsotg->periodic_channels--; 617 } 618 } 619 620 /** 621 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 622 * schedule if it is not already in the schedule. If the QH is already in 623 * the schedule, no action is taken. 624 * 625 * @hsotg: The HCD state structure for the DWC OTG controller 626 * @qh: The QH to add 627 * 628 * Return: 0 if successful, negative error code otherwise 629 */ 630 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 631 { 632 int status = 0; 633 u32 intr_mask; 634 635 if (dbg_qh(qh)) 636 dev_vdbg(hsotg->dev, "%s()\n", __func__); 637 638 if (!list_empty(&qh->qh_list_entry)) 639 /* QH already in a schedule */ 640 return status; 641 642 /* Add the new QH to the appropriate schedule */ 643 if (dwc2_qh_is_non_per(qh)) { 644 /* Always start in inactive schedule */ 645 list_add_tail(&qh->qh_list_entry, 646 &hsotg->non_periodic_sched_inactive); 647 } else { 648 status = dwc2_schedule_periodic(hsotg, qh); 649 if (status == 0) { 650 if (!hsotg->periodic_qh_count) { 651 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 652 intr_mask |= GINTSTS_SOF; 653 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 654 } 655 hsotg->periodic_qh_count++; 656 } 657 } 658 659 return status; 660 } 661 662 /** 663 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 664 * schedule. Memory is not freed. 665 * 666 * @hsotg: The HCD state structure 667 * @qh: QH to remove from schedule 668 */ 669 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 670 { 671 u32 intr_mask; 672 673 dev_vdbg(hsotg->dev, "%s()\n", __func__); 674 675 if (list_empty(&qh->qh_list_entry)) 676 /* QH is not in a schedule */ 677 return; 678 679 if (dwc2_qh_is_non_per(qh)) { 680 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 681 hsotg->non_periodic_qh_ptr = 682 hsotg->non_periodic_qh_ptr->next; 683 list_del_init(&qh->qh_list_entry); 684 } else { 685 dwc2_deschedule_periodic(hsotg, qh); 686 hsotg->periodic_qh_count--; 687 if (!hsotg->periodic_qh_count) { 688 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 689 intr_mask &= ~GINTSTS_SOF; 690 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 691 } 692 } 693 } 694 695 /* 696 * Schedule the next continuing periodic split transfer 697 */ 698 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 699 struct dwc2_qh *qh, u16 frame_number, 700 int sched_next_periodic_split) 701 { 702 u16 incr; 703 704 if (sched_next_periodic_split) { 705 qh->sched_frame = frame_number; 706 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 707 if (dwc2_frame_num_le(frame_number, incr)) { 708 /* 709 * Allow one frame to elapse after start split 710 * microframe before scheduling complete split, but 711 * DON'T if we are doing the next start split in the 712 * same frame for an ISOC out 713 */ 714 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 715 qh->ep_is_in != 0) { 716 qh->sched_frame = 717 dwc2_frame_num_inc(qh->sched_frame, 1); 718 } 719 } 720 } else { 721 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 722 qh->interval); 723 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 724 qh->sched_frame = frame_number; 725 qh->sched_frame |= 0x7; 726 qh->start_split_frame = qh->sched_frame; 727 } 728 } 729 730 /* 731 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 732 * non-periodic schedule. The QH is added to the inactive non-periodic 733 * schedule if any QTDs are still attached to the QH. 734 * 735 * For periodic QHs, the QH is removed from the periodic queued schedule. If 736 * there are any QTDs still attached to the QH, the QH is added to either the 737 * periodic inactive schedule or the periodic ready schedule and its next 738 * scheduled frame is calculated. The QH is placed in the ready schedule if 739 * the scheduled frame has been reached already. Otherwise it's placed in the 740 * inactive schedule. If there are no QTDs attached to the QH, the QH is 741 * completely removed from the periodic schedule. 742 */ 743 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 744 int sched_next_periodic_split) 745 { 746 if (dbg_qh(qh)) 747 dev_vdbg(hsotg->dev, "%s()\n", __func__); 748 749 if (dwc2_qh_is_non_per(qh)) { 750 dwc2_hcd_qh_unlink(hsotg, qh); 751 if (!list_empty(&qh->qtd_list)) 752 /* Add back to inactive non-periodic schedule */ 753 dwc2_hcd_qh_add(hsotg, qh); 754 } else { 755 u16 frame_number = dwc2_hcd_get_frame_number(hsotg); 756 757 if (qh->do_split) { 758 dwc2_sched_periodic_split(hsotg, qh, frame_number, 759 sched_next_periodic_split); 760 } else { 761 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 762 qh->interval); 763 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 764 qh->sched_frame = frame_number; 765 } 766 767 if (list_empty(&qh->qtd_list)) { 768 dwc2_hcd_qh_unlink(hsotg, qh); 769 } else { 770 /* 771 * Remove from periodic_sched_queued and move to 772 * appropriate queue 773 */ 774 if ((hsotg->core_params->uframe_sched > 0 && 775 dwc2_frame_num_le(qh->sched_frame, frame_number)) 776 || (hsotg->core_params->uframe_sched <= 0 && 777 qh->sched_frame == frame_number)) { 778 list_move(&qh->qh_list_entry, 779 &hsotg->periodic_sched_ready); 780 } else { 781 if (!dwc2_frame_num_le(hsotg->next_sched_frame, 782 qh->sched_frame)) 783 hsotg->next_sched_frame = 784 qh->sched_frame; 785 list_move(&qh->qh_list_entry, 786 &hsotg->periodic_sched_inactive); 787 } 788 } 789 } 790 } 791 792 /** 793 * dwc2_hcd_qtd_init() - Initializes a QTD structure 794 * 795 * @qtd: The QTD to initialize 796 * @urb: The associated URB 797 */ 798 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 799 { 800 qtd->urb = urb; 801 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 802 USB_ENDPOINT_XFER_CONTROL) { 803 /* 804 * The only time the QTD data toggle is used is on the data 805 * phase of control transfers. This phase always starts with 806 * DATA1. 807 */ 808 qtd->data_toggle = DWC2_HC_PID_DATA1; 809 qtd->control_phase = DWC2_CONTROL_SETUP; 810 } 811 812 /* Start split */ 813 qtd->complete_split = 0; 814 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 815 qtd->isoc_split_offset = 0; 816 qtd->in_process = 0; 817 818 /* Store the qtd ptr in the urb to reference the QTD */ 819 urb->qtd = qtd; 820 } 821 822 /** 823 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 824 * 825 * @hsotg: The DWC HCD structure 826 * @qtd: The QTD to add 827 * @qh: Out parameter to return queue head 828 * @atomic_alloc: Flag to do atomic alloc if needed 829 * 830 * Return: 0 if successful, negative error code otherwise 831 * 832 * Finds the correct QH to place the QTD into. If it does not find a QH, it 833 * will create a new QH. If the QH to which the QTD is added is not currently 834 * scheduled, it is placed into the proper schedule based on its EP type. 835 */ 836 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 837 struct dwc2_qh **qh, gfp_t mem_flags) 838 { 839 struct dwc2_hcd_urb *urb = qtd->urb; 840 unsigned long flags; 841 int allocated = 0; 842 int retval; 843 844 /* 845 * Get the QH which holds the QTD-list to insert to. Create QH if it 846 * doesn't exist. 847 */ 848 if (*qh == NULL) { 849 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); 850 if (*qh == NULL) 851 return -ENOMEM; 852 allocated = 1; 853 } 854 855 spin_lock_irqsave(&hsotg->lock, flags); 856 857 retval = dwc2_hcd_qh_add(hsotg, *qh); 858 if (retval) 859 goto fail; 860 861 qtd->qh = *qh; 862 list_add_tail(&qtd->qtd_list_entry, &(*qh)->qtd_list); 863 spin_unlock_irqrestore(&hsotg->lock, flags); 864 865 return 0; 866 867 fail: 868 if (allocated) { 869 struct dwc2_qtd *qtd2, *qtd2_tmp; 870 struct dwc2_qh *qh_tmp = *qh; 871 872 *qh = NULL; 873 dwc2_hcd_qh_unlink(hsotg, qh_tmp); 874 875 /* Free each QTD in the QH's QTD list */ 876 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh_tmp->qtd_list, 877 qtd_list_entry) 878 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); 879 880 spin_unlock_irqrestore(&hsotg->lock, flags); 881 dwc2_hcd_qh_free(hsotg, qh_tmp); 882 } else { 883 spin_unlock_irqrestore(&hsotg->lock, flags); 884 } 885 886 return retval; 887 } 888 889 void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 890 struct dwc2_qtd *qtd, 891 struct dwc2_qh *qh) 892 { 893 struct dwc2_softc *sc = hsotg->hsotg_sc; 894 895 list_del_init(&qtd->qtd_list_entry); 896 pool_cache_put(sc->sc_qtdpool, qtd); 897 } 898 899 #define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6) 900 #define HS_HOST_DELAY 5 /* nanoseconds */ 901 #define FS_LS_HOST_DELAY 1000 /* nanoseconds */ 902 #define HUB_LS_SETUP 333 /* nanoseconds */ 903 904 static u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in, 905 int is_isoc, int bytecount) 906 { 907 unsigned long retval; 908 909 switch (speed) { 910 case USB_SPEED_HIGH: 911 if (is_isoc) 912 retval = 913 ((38 * 8 * 2083) + 914 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 915 HS_HOST_DELAY; 916 else 917 retval = 918 ((55 * 8 * 2083) + 919 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 920 HS_HOST_DELAY; 921 break; 922 case USB_SPEED_FULL: 923 if (is_isoc) { 924 retval = 925 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 926 if (is_in) 927 retval = 7268 + FS_LS_HOST_DELAY + retval; 928 else 929 retval = 6265 + FS_LS_HOST_DELAY + retval; 930 } else { 931 retval = 932 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 933 retval = 9107 + FS_LS_HOST_DELAY + retval; 934 } 935 break; 936 case USB_SPEED_LOW: 937 if (is_in) { 938 retval = 939 (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) / 940 1000; 941 retval = 942 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 943 retval; 944 } else { 945 retval = 946 (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) / 947 1000; 948 retval = 949 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 950 retval; 951 } 952 break; 953 default: 954 dev_warn(hsotg->dev, "Unknown device speed\n"); 955 retval = -1; 956 } 957 958 return NS_TO_US(retval); 959 } 960