1 /* $NetBSD: dwc2_hcd.c,v 1.19 2016/02/24 22:17:54 skrll Exp $ */ 2 3 /* 4 * hcd.c - DesignWare HS OTG Controller host-mode routines 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the core HCD code, and implements the Linux hc_driver 41 * API 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.19 2016/02/24 22:17:54 skrll Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/pool.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <linux/kernel.h> 58 #include <linux/list.h> 59 #include <linux/err.h> 60 #include <linux/workqueue.h> 61 62 #include <dwc2/dwc2.h> 63 #include <dwc2/dwc2var.h> 64 65 #include "dwc2_core.h" 66 #include "dwc2_hcd.h" 67 68 /** 69 * dwc2_dump_channel_info() - Prints the state of a host channel 70 * 71 * @hsotg: Programming view of DWC_otg controller 72 * @chan: Pointer to the channel to dump 73 * 74 * Must be called with interrupt disabled and spinlock held 75 * 76 * NOTE: This function will be removed once the peripheral controller code 77 * is integrated and the driver is stable 78 */ 79 #ifdef VERBOSE_DEBUG 80 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 81 struct dwc2_host_chan *chan) 82 { 83 int num_channels = hsotg->core_params->host_channels; 84 struct dwc2_qh *qh; 85 u32 hcchar; 86 u32 hcsplt; 87 u32 hctsiz; 88 u32 hc_dma; 89 int i; 90 91 if (chan == NULL) 92 return; 93 94 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 95 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 96 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 97 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 98 99 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 100 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 101 hcchar, hcsplt); 102 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 103 hctsiz, hc_dma); 104 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 105 chan->dev_addr, chan->ep_num, chan->ep_is_in); 106 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 107 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 108 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 109 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 110 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 111 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 112 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 113 (unsigned long)chan->xfer_dma); 114 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 115 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 116 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 117 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 118 qh_list_entry) 119 dev_dbg(hsotg->dev, " %p\n", qh); 120 dev_dbg(hsotg->dev, " NP active sched:\n"); 121 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 122 qh_list_entry) 123 dev_dbg(hsotg->dev, " %p\n", qh); 124 dev_dbg(hsotg->dev, " Channels:\n"); 125 for (i = 0; i < num_channels; i++) { 126 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 127 128 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 129 } 130 } 131 #endif /* VERBOSE_DEBUG */ 132 133 /* 134 * Processes all the URBs in a single list of QHs. Completes them with 135 * -ETIMEDOUT and frees the QTD. 136 * 137 * Must be called with interrupt disabled and spinlock held 138 */ 139 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 140 struct list_head *qh_list) 141 { 142 struct dwc2_qh *qh, *qh_tmp; 143 struct dwc2_qtd *qtd, *qtd_tmp; 144 145 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 146 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 147 qtd_list_entry) { 148 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 149 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 150 } 151 } 152 } 153 154 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 155 struct list_head *qh_list) 156 { 157 struct dwc2_qtd *qtd, *qtd_tmp; 158 struct dwc2_qh *qh, *qh_tmp; 159 unsigned long flags; 160 161 if (!qh_list->next) 162 /* The list hasn't been initialized yet */ 163 return; 164 165 spin_lock_irqsave(&hsotg->lock, flags); 166 167 /* Ensure there are no QTDs or URBs left */ 168 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 169 170 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 171 dwc2_hcd_qh_unlink(hsotg, qh); 172 173 /* Free each QTD in the QH's QTD list */ 174 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 175 qtd_list_entry) 176 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 177 178 spin_unlock_irqrestore(&hsotg->lock, flags); 179 dwc2_hcd_qh_free(hsotg, qh); 180 spin_lock_irqsave(&hsotg->lock, flags); 181 } 182 183 spin_unlock_irqrestore(&hsotg->lock, flags); 184 } 185 186 /* 187 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 188 * and periodic schedules. The QTD associated with each URB is removed from 189 * the schedule and freed. This function may be called when a disconnect is 190 * detected or when the HCD is being stopped. 191 * 192 * Must be called with interrupt disabled and spinlock held 193 */ 194 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 195 { 196 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 197 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 198 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 199 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 201 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 202 } 203 204 /** 205 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 206 * 207 * @hsotg: Pointer to struct dwc2_hsotg 208 */ 209 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 210 { 211 u32 hprt0; 212 213 if (hsotg->op_state == OTG_STATE_B_HOST) { 214 /* 215 * Reset the port. During a HNP mode switch the reset 216 * needs to occur within 1ms and have a duration of at 217 * least 50ms. 218 */ 219 hprt0 = dwc2_read_hprt0(hsotg); 220 hprt0 |= HPRT0_RST; 221 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 222 } 223 224 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 225 msecs_to_jiffies(50)); 226 } 227 228 /* Must be called with interrupt disabled and spinlock held */ 229 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 230 { 231 int num_channels = hsotg->core_params->host_channels; 232 struct dwc2_host_chan *channel; 233 u32 hcchar; 234 int i; 235 236 if (hsotg->core_params->dma_enable <= 0) { 237 /* Flush out any channel requests in slave mode */ 238 for (i = 0; i < num_channels; i++) { 239 channel = hsotg->hc_ptr_array[i]; 240 if (!list_empty(&channel->hc_list_entry)) 241 continue; 242 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 243 if (hcchar & HCCHAR_CHENA) { 244 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 245 hcchar |= HCCHAR_CHDIS; 246 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 247 } 248 } 249 } 250 251 for (i = 0; i < num_channels; i++) { 252 channel = hsotg->hc_ptr_array[i]; 253 if (!list_empty(&channel->hc_list_entry)) 254 continue; 255 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 256 if (hcchar & HCCHAR_CHENA) { 257 /* Halt the channel */ 258 hcchar |= HCCHAR_CHDIS; 259 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 260 } 261 262 dwc2_hc_cleanup(hsotg, channel); 263 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 264 /* 265 * Added for Descriptor DMA to prevent channel double cleanup in 266 * release_channel_ddma(), which is called from ep_disable when 267 * device disconnects 268 */ 269 channel->qh = NULL; 270 } 271 /* All channels have been freed, mark them available */ 272 if (hsotg->core_params->uframe_sched > 0) { 273 hsotg->available_host_channels = 274 hsotg->core_params->host_channels; 275 } else { 276 hsotg->non_periodic_channels = 0; 277 hsotg->periodic_channels = 0; 278 } 279 } 280 281 /** 282 * dwc2_hcd_connect() - Handles connect of the HCD 283 * 284 * @hsotg: Pointer to struct dwc2_hsotg 285 * 286 * Must be called with interrupt disabled and spinlock held 287 */ 288 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 289 { 290 if (hsotg->lx_state != DWC2_L0) 291 usb_hcd_resume_root_hub(hsotg->priv); 292 293 hsotg->flags.b.port_connect_status_change = 1; 294 hsotg->flags.b.port_connect_status = 1; 295 } 296 297 /** 298 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 299 * 300 * @hsotg: Pointer to struct dwc2_hsotg 301 * @force: If true, we won't try to reconnect even if we see device connected. 302 * 303 * Must be called with interrupt disabled and spinlock held 304 */ 305 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 306 { 307 u32 intr; 308 u32 hprt0; 309 310 /* Set status flags for the hub driver */ 311 hsotg->flags.b.port_connect_status_change = 1; 312 hsotg->flags.b.port_connect_status = 0; 313 314 /* 315 * Shutdown any transfers in process by clearing the Tx FIFO Empty 316 * interrupt mask and status bits and disabling subsequent host 317 * channel interrupts. 318 */ 319 intr = DWC2_READ_4(hsotg, GINTMSK); 320 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 321 DWC2_WRITE_4(hsotg, GINTMSK, intr); 322 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 323 DWC2_WRITE_4(hsotg, GINTSTS, intr); 324 325 /* 326 * Turn off the vbus power only if the core has transitioned to device 327 * mode. If still in host mode, need to keep power on to detect a 328 * reconnection. 329 */ 330 if (dwc2_is_device_mode(hsotg)) { 331 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 332 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 333 DWC2_WRITE_4(hsotg, HPRT0, 0); 334 } 335 336 dwc2_disable_host_interrupts(hsotg); 337 } 338 339 /* Respond with an error status to all URBs in the schedule */ 340 dwc2_kill_all_urbs(hsotg); 341 342 if (dwc2_is_host_mode(hsotg)) 343 /* Clean up any host channels that were in use */ 344 dwc2_hcd_cleanup_channels(hsotg); 345 346 dwc2_host_disconnect(hsotg); 347 348 dwc2_root_intr(hsotg->hsotg_sc); 349 350 /* 351 * Add an extra check here to see if we're actually connected but 352 * we don't have a detection interrupt pending. This can happen if: 353 * 1. hardware sees connect 354 * 2. hardware sees disconnect 355 * 3. hardware sees connect 356 * 4. dwc2_port_intr() - clears connect interrupt 357 * 5. dwc2_handle_common_intr() - calls here 358 * 359 * Without the extra check here we will end calling disconnect 360 * and won't get any future interrupts to handle the connect. 361 */ 362 if (!force) { 363 hprt0 = DWC2_READ_4(hsotg, HPRT0); 364 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 365 dwc2_hcd_connect(hsotg); 366 } 367 } 368 369 /** 370 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 371 * 372 * @hsotg: Pointer to struct dwc2_hsotg 373 */ 374 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 375 { 376 if (hsotg->bus_suspended) { 377 hsotg->flags.b.port_suspend_change = 1; 378 usb_hcd_resume_root_hub(hsotg->priv); 379 } 380 381 if (hsotg->lx_state == DWC2_L1) 382 hsotg->flags.b.port_l1_change = 1; 383 384 dwc2_root_intr(hsotg->hsotg_sc); 385 } 386 387 /** 388 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 389 * 390 * @hsotg: Pointer to struct dwc2_hsotg 391 * 392 * Must be called with interrupt disabled and spinlock held 393 */ 394 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 395 { 396 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 397 398 /* 399 * The root hub should be disconnected before this function is called. 400 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 401 * and the QH lists (via ..._hcd_endpoint_disable). 402 */ 403 404 /* Turn off all host-specific interrupts */ 405 dwc2_disable_host_interrupts(hsotg); 406 407 /* Turn off the vbus power */ 408 dev_dbg(hsotg->dev, "PortPower off\n"); 409 DWC2_WRITE_4(hsotg, HPRT0, 0); 410 } 411 412 /* Caller must hold driver lock */ 413 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 414 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 415 struct dwc2_qtd *qtd) 416 { 417 u32 intr_mask; 418 int retval; 419 int dev_speed; 420 421 if (!hsotg->flags.b.port_connect_status) { 422 /* No longer connected */ 423 dev_err(hsotg->dev, "Not connected\n"); 424 return -ENODEV; 425 } 426 427 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 428 429 /* Some configurations cannot support LS traffic on a FS root port */ 430 if ((dev_speed == USB_SPEED_LOW) && 431 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 432 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 433 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 434 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 435 436 if (prtspd == HPRT0_SPD_FULL_SPEED) { 437 dev_err(hsotg->dev, 438 "DWC OTG HCD URB Enqueue unsupported\n"); 439 return -ENODEV; 440 } 441 } 442 443 if (!qtd) 444 return -EINVAL; 445 446 memset(qtd, 0, sizeof(*qtd)); 447 448 dwc2_hcd_qtd_init(qtd, urb); 449 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 450 if (retval) { 451 dev_err(hsotg->dev, 452 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 453 retval); 454 return retval; 455 } 456 457 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 458 if (!(intr_mask & GINTSTS_SOF)) { 459 enum dwc2_transaction_type tr_type; 460 461 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 462 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 463 /* 464 * Do not schedule SG transactions until qtd has 465 * URB_GIVEBACK_ASAP set 466 */ 467 return 0; 468 469 tr_type = dwc2_hcd_select_transactions(hsotg); 470 if (tr_type != DWC2_TRANSACTION_NONE) 471 dwc2_hcd_queue_transactions(hsotg, tr_type); 472 } 473 474 return 0; 475 } 476 477 /* Must be called with interrupt disabled and spinlock held */ 478 int 479 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 480 struct dwc2_hcd_urb *urb) 481 { 482 struct dwc2_qh *qh; 483 struct dwc2_qtd *urb_qtd; 484 485 urb_qtd = urb->qtd; 486 if (!urb_qtd) { 487 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 488 return -EINVAL; 489 } 490 491 qh = urb_qtd->qh; 492 if (!qh) { 493 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 494 return -EINVAL; 495 } 496 497 urb->priv = NULL; 498 499 if (urb_qtd->in_process && qh->channel) { 500 #ifdef VERBOSE_DEBUG 501 dwc2_dump_channel_info(hsotg, qh->channel); 502 #endif 503 /* The QTD is in process (it has been assigned to a channel) */ 504 if (hsotg->flags.b.port_connect_status) 505 /* 506 * If still connected (i.e. in host mode), halt the 507 * channel so it can be used for other transfers. If 508 * no longer connected, the host registers can't be 509 * written to halt the channel since the core is in 510 * device mode. 511 */ 512 dwc2_hc_halt(hsotg, qh->channel, 513 DWC2_HC_XFER_URB_DEQUEUE); 514 } 515 516 /* 517 * Free the QTD and clean up the associated QH. Leave the QH in the 518 * schedule if it has any remaining QTDs. 519 */ 520 if (hsotg->core_params->dma_desc_enable <= 0) { 521 u8 in_process = urb_qtd->in_process; 522 523 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 524 if (in_process) { 525 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 526 qh->channel = NULL; 527 } else if (list_empty(&qh->qtd_list)) { 528 dwc2_hcd_qh_unlink(hsotg, qh); 529 } 530 } else { 531 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 532 } 533 534 return 0; 535 } 536 537 538 /* 539 * Initializes dynamic portions of the DWC_otg HCD state 540 * 541 * Must be called with interrupt disabled and spinlock held 542 */ 543 void 544 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 545 { 546 struct dwc2_host_chan *chan, *chan_tmp; 547 int num_channels; 548 int i; 549 550 hsotg->flags.d32 = 0; 551 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 552 553 if (hsotg->core_params->uframe_sched > 0) { 554 hsotg->available_host_channels = 555 hsotg->core_params->host_channels; 556 } else { 557 hsotg->non_periodic_channels = 0; 558 hsotg->periodic_channels = 0; 559 } 560 561 /* 562 * Put all channels in the free channel list and clean up channel 563 * states 564 */ 565 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 566 hc_list_entry) 567 list_del_init(&chan->hc_list_entry); 568 569 num_channels = hsotg->core_params->host_channels; 570 for (i = 0; i < num_channels; i++) { 571 chan = hsotg->hc_ptr_array[i]; 572 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 573 dwc2_hc_cleanup(hsotg, chan); 574 } 575 576 /* Initialize the DWC core for host mode operation */ 577 dwc2_core_host_init(hsotg); 578 } 579 580 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 581 struct dwc2_host_chan *chan, 582 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 583 { 584 int hub_addr, hub_port; 585 586 chan->do_split = 1; 587 chan->xact_pos = qtd->isoc_split_pos; 588 chan->complete_split = qtd->complete_split; 589 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 590 chan->hub_addr = (u8)hub_addr; 591 chan->hub_port = (u8)hub_port; 592 } 593 594 static void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 595 struct dwc2_host_chan *chan, 596 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 597 { 598 if (hsotg->core_params->dma_enable > 0) { 599 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 600 601 /* For non-dword aligned case */ 602 if (hsotg->core_params->dma_desc_enable <= 0 && 603 (chan->xfer_dma & 0x3)) 604 return (u8 *)urb->buf + urb->actual_length; 605 } else { 606 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 607 } 608 609 return NULL; 610 } 611 612 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 613 struct dwc2_host_chan *chan, 614 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 615 { 616 struct dwc2_hcd_iso_packet_desc *frame_desc; 617 void *bufptr = NULL; 618 619 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 620 case USB_ENDPOINT_XFER_CONTROL: 621 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 622 623 switch (qtd->control_phase) { 624 case DWC2_CONTROL_SETUP: 625 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 626 chan->do_ping = 0; 627 chan->ep_is_in = 0; 628 chan->data_pid_start = DWC2_HC_PID_SETUP; 629 if (hsotg->core_params->dma_enable > 0) 630 chan->xfer_dma = urb->setup_dma; 631 else 632 chan->xfer_buf = urb->setup_packet; 633 chan->xfer_len = 8; 634 break; 635 636 case DWC2_CONTROL_DATA: 637 dev_vdbg(hsotg->dev, " Control data transaction\n"); 638 chan->data_pid_start = qtd->data_toggle; 639 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 640 break; 641 642 case DWC2_CONTROL_STATUS: 643 /* 644 * Direction is opposite of data direction or IN if no 645 * data 646 */ 647 dev_vdbg(hsotg->dev, " Control status transaction\n"); 648 if (urb->length == 0) 649 chan->ep_is_in = 1; 650 else 651 chan->ep_is_in = 652 dwc2_hcd_is_pipe_out(&urb->pipe_info); 653 if (chan->ep_is_in) 654 chan->do_ping = 0; 655 chan->data_pid_start = DWC2_HC_PID_DATA1; 656 chan->xfer_len = 0; 657 if (hsotg->core_params->dma_enable > 0) 658 chan->xfer_dma = hsotg->status_buf_dma; 659 else 660 chan->xfer_buf = hsotg->status_buf; 661 break; 662 } 663 break; 664 665 case USB_ENDPOINT_XFER_BULK: 666 chan->ep_type = USB_ENDPOINT_XFER_BULK; 667 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 668 break; 669 670 case USB_ENDPOINT_XFER_INT: 671 chan->ep_type = USB_ENDPOINT_XFER_INT; 672 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 673 break; 674 675 case USB_ENDPOINT_XFER_ISOC: 676 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 677 if (hsotg->core_params->dma_desc_enable > 0) 678 break; 679 680 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 681 frame_desc->status = 0; 682 683 if (hsotg->core_params->dma_enable > 0) { 684 chan->xfer_dma = urb->dma; 685 chan->xfer_dma += frame_desc->offset + 686 qtd->isoc_split_offset; 687 } else { 688 chan->xfer_buf = urb->buf; 689 chan->xfer_buf += frame_desc->offset + 690 qtd->isoc_split_offset; 691 } 692 693 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 694 695 /* For non-dword aligned buffers */ 696 if (hsotg->core_params->dma_enable > 0 && 697 (chan->xfer_dma & 0x3)) 698 bufptr = (u8 *)urb->buf + frame_desc->offset + 699 qtd->isoc_split_offset; 700 701 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 702 if (chan->xfer_len <= 188) 703 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 704 else 705 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 706 } 707 break; 708 } 709 710 return bufptr; 711 } 712 713 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 714 struct dwc2_host_chan *chan, 715 struct dwc2_hcd_urb *urb, void *bufptr) 716 { 717 u32 buf_size; 718 719 if (!qh->dw_align_buf) { 720 int err; 721 722 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 723 buf_size = hsotg->core_params->max_transfer_size; 724 else 725 /* 3072 = 3 max-size Isoc packets */ 726 buf_size = 3072; 727 728 qh->dw_align_buf = NULL; 729 qh->dw_align_buf_dma = 0; 730 err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, buf_size, buf_size, 731 &qh->dw_align_buf_usbdma); 732 if (!err) { 733 usb_dma_t *ud = &qh->dw_align_buf_usbdma; 734 735 qh->dw_align_buf = KERNADDR(ud, 0); 736 qh->dw_align_buf_dma = DMAADDR(ud, 0); 737 } 738 if (!qh->dw_align_buf) 739 return -ENOMEM; 740 qh->dw_align_buf_size = buf_size; 741 } 742 743 if (chan->xfer_len) { 744 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 745 void *usb_urb = urb->priv; 746 747 if (usb_urb) { 748 if (!chan->ep_is_in) { 749 memcpy(qh->dw_align_buf, bufptr, 750 chan->xfer_len); 751 } 752 } else { 753 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 754 } 755 } 756 757 usb_syncmem(&qh->dw_align_buf_usbdma, 0, qh->dw_align_buf_size, 758 chan->ep_is_in ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 759 760 chan->align_buf = qh->dw_align_buf_dma; 761 return 0; 762 } 763 764 /** 765 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 766 * channel and initializes the host channel to perform the transactions. The 767 * host channel is removed from the free list. 768 * 769 * @hsotg: The HCD state structure 770 * @qh: Transactions from the first QTD for this QH are selected and assigned 771 * to a free host channel 772 */ 773 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 774 { 775 struct dwc2_host_chan *chan; 776 struct dwc2_hcd_urb *urb; 777 struct dwc2_qtd *qtd; 778 void *bufptr = NULL; 779 780 if (dbg_qh(qh)) 781 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 782 783 if (list_empty(&qh->qtd_list)) { 784 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 785 return -ENOMEM; 786 } 787 788 if (list_empty(&hsotg->free_hc_list)) { 789 dev_dbg(hsotg->dev, "No free channel to assign\n"); 790 return -ENOMEM; 791 } 792 793 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 794 hc_list_entry); 795 796 /* Remove host channel from free list */ 797 list_del_init(&chan->hc_list_entry); 798 799 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 800 urb = qtd->urb; 801 qh->channel = chan; 802 qtd->in_process = 1; 803 804 /* 805 * Use usb_pipedevice to determine device address. This address is 806 * 0 before the SET_ADDRESS command and the correct address afterward. 807 */ 808 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 809 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 810 chan->speed = qh->dev_speed; 811 chan->max_packet = dwc2_max_packet(qh->maxp); 812 813 chan->xfer_started = 0; 814 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 815 chan->error_state = (qtd->error_count > 0); 816 chan->halt_on_queue = 0; 817 chan->halt_pending = 0; 818 chan->requests = 0; 819 820 /* 821 * The following values may be modified in the transfer type section 822 * below. The xfer_len value may be reduced when the transfer is 823 * started to accommodate the max widths of the XferSize and PktCnt 824 * fields in the HCTSIZn register. 825 */ 826 827 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 828 if (chan->ep_is_in) 829 chan->do_ping = 0; 830 else 831 chan->do_ping = qh->ping_state; 832 833 chan->data_pid_start = qh->data_toggle; 834 chan->multi_count = 1; 835 836 if (urb->actual_length > urb->length && 837 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 838 urb->actual_length = urb->length; 839 840 chan->xfer_len = urb->length - urb->actual_length; 841 chan->xfer_count = 0; 842 843 /* Set the split attributes if required */ 844 if (qh->do_split) 845 dwc2_hc_init_split(hsotg, chan, qtd, urb); 846 else 847 chan->do_split = 0; 848 849 /* Set the transfer attributes */ 850 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 851 852 /* Non DWORD-aligned buffer case */ 853 if (bufptr) { 854 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 855 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 856 dev_err(hsotg->dev, 857 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 858 __func__); 859 /* Add channel back to free list */ 860 chan->align_buf = 0; 861 chan->multi_count = 0; 862 list_add_tail(&chan->hc_list_entry, 863 &hsotg->free_hc_list); 864 qtd->in_process = 0; 865 qh->channel = NULL; 866 return -ENOMEM; 867 } 868 } else { 869 chan->align_buf = 0; 870 } 871 872 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 873 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 874 /* 875 * This value may be modified when the transfer is started 876 * to reflect the actual transfer length 877 */ 878 chan->multi_count = dwc2_hb_mult(qh->maxp); 879 880 if (hsotg->core_params->dma_desc_enable > 0) { 881 chan->desc_list_usbdma = qh->desc_list_usbdma; 882 chan->desc_list_addr = qh->desc_list_dma; 883 chan->desc_list_sz = qh->desc_list_sz; 884 } 885 886 dwc2_hc_init(hsotg, chan); 887 chan->qh = qh; 888 889 return 0; 890 } 891 892 /** 893 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 894 * schedule and assigns them to available host channels. Called from the HCD 895 * interrupt handler functions. 896 * 897 * @hsotg: The HCD state structure 898 * 899 * Return: The types of new transactions that were assigned to host channels 900 */ 901 enum dwc2_transaction_type dwc2_hcd_select_transactions( 902 struct dwc2_hsotg *hsotg) 903 { 904 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 905 struct list_head *qh_ptr; 906 struct dwc2_qh *qh; 907 int num_channels; 908 909 #ifdef DWC2_DEBUG_SOF 910 dev_vdbg(hsotg->dev, " Select Transactions\n"); 911 #endif 912 913 /* Process entries in the periodic ready list */ 914 qh_ptr = hsotg->periodic_sched_ready.next; 915 while (qh_ptr != &hsotg->periodic_sched_ready) { 916 if (list_empty(&hsotg->free_hc_list)) 917 break; 918 if (hsotg->core_params->uframe_sched > 0) { 919 if (hsotg->available_host_channels <= 1) 920 break; 921 hsotg->available_host_channels--; 922 } 923 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 924 if (dwc2_assign_and_init_hc(hsotg, qh)) 925 break; 926 927 /* 928 * Move the QH from the periodic ready schedule to the 929 * periodic assigned schedule 930 */ 931 qh_ptr = qh_ptr->next; 932 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 933 ret_val = DWC2_TRANSACTION_PERIODIC; 934 } 935 936 /* 937 * Process entries in the inactive portion of the non-periodic 938 * schedule. Some free host channels may not be used if they are 939 * reserved for periodic transfers. 940 */ 941 num_channels = hsotg->core_params->host_channels; 942 qh_ptr = hsotg->non_periodic_sched_inactive.next; 943 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 944 if (hsotg->core_params->uframe_sched <= 0 && 945 hsotg->non_periodic_channels >= num_channels - 946 hsotg->periodic_channels) 947 break; 948 if (list_empty(&hsotg->free_hc_list)) 949 break; 950 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 951 952 /* 953 * Check to see if this is a NAK'd retransmit, in which case 954 * ignore for retransmission. We hold off on bulk/control 955 * retransmissions to reduce NAK interrupt overhead for 956 * cheeky devices that just hold off using NAKs. 957 */ 958 if (qh->nak_frame != 0xffff && 959 dwc2_full_frame_num(qh->nak_frame) == 960 dwc2_full_frame_num(dwc2_hcd_get_frame_number(hsotg))) { 961 qh_ptr = qh_ptr->next; 962 continue; 963 } else { 964 qh->nak_frame = 0xffff; 965 } 966 967 if (hsotg->core_params->uframe_sched > 0) { 968 if (hsotg->available_host_channels < 1) 969 break; 970 hsotg->available_host_channels--; 971 } 972 973 if (dwc2_assign_and_init_hc(hsotg, qh)) 974 break; 975 976 /* 977 * Move the QH from the non-periodic inactive schedule to the 978 * non-periodic active schedule 979 */ 980 qh_ptr = qh_ptr->next; 981 list_move(&qh->qh_list_entry, 982 &hsotg->non_periodic_sched_active); 983 984 if (ret_val == DWC2_TRANSACTION_NONE) 985 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 986 else 987 ret_val = DWC2_TRANSACTION_ALL; 988 989 if (hsotg->core_params->uframe_sched <= 0) 990 hsotg->non_periodic_channels++; 991 } 992 993 return ret_val; 994 } 995 996 /** 997 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 998 * a host channel associated with either a periodic or non-periodic transfer 999 * 1000 * @hsotg: The HCD state structure 1001 * @chan: Host channel descriptor associated with either a periodic or 1002 * non-periodic transfer 1003 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 1004 * for periodic transfers or the non-periodic Tx FIFO 1005 * for non-periodic transfers 1006 * 1007 * Return: 1 if a request is queued and more requests may be needed to 1008 * complete the transfer, 0 if no more requests are required for this 1009 * transfer, -1 if there is insufficient space in the Tx FIFO 1010 * 1011 * This function assumes that there is space available in the appropriate 1012 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 1013 * it checks whether space is available in the appropriate Tx FIFO. 1014 * 1015 * Must be called with interrupt disabled and spinlock held 1016 */ 1017 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1018 struct dwc2_host_chan *chan, 1019 u16 fifo_dwords_avail) 1020 { 1021 int retval = 0; 1022 1023 if (hsotg->core_params->dma_enable > 0) { 1024 if (hsotg->core_params->dma_desc_enable > 0) { 1025 if (!chan->xfer_started || 1026 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1027 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1028 chan->qh->ping_state = 0; 1029 } 1030 } else if (!chan->xfer_started) { 1031 dwc2_hc_start_transfer(hsotg, chan); 1032 chan->qh->ping_state = 0; 1033 } 1034 } else if (chan->halt_pending) { 1035 /* Don't queue a request if the channel has been halted */ 1036 } else if (chan->halt_on_queue) { 1037 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1038 } else if (chan->do_ping) { 1039 if (!chan->xfer_started) 1040 dwc2_hc_start_transfer(hsotg, chan); 1041 } else if (!chan->ep_is_in || 1042 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1043 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1044 if (!chan->xfer_started) { 1045 dwc2_hc_start_transfer(hsotg, chan); 1046 retval = 1; 1047 } else { 1048 retval = dwc2_hc_continue_transfer(hsotg, chan); 1049 } 1050 } else { 1051 retval = -1; 1052 } 1053 } else { 1054 if (!chan->xfer_started) { 1055 dwc2_hc_start_transfer(hsotg, chan); 1056 retval = 1; 1057 } else { 1058 retval = dwc2_hc_continue_transfer(hsotg, chan); 1059 } 1060 } 1061 1062 return retval; 1063 } 1064 1065 /* 1066 * Processes periodic channels for the next frame and queues transactions for 1067 * these channels to the DWC_otg controller. After queueing transactions, the 1068 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1069 * to queue as Periodic Tx FIFO or request queue space becomes available. 1070 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1071 * 1072 * Must be called with interrupt disabled and spinlock held 1073 */ 1074 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1075 { 1076 struct list_head *qh_ptr; 1077 struct dwc2_qh *qh; 1078 u32 tx_status; 1079 u32 fspcavail; 1080 u32 gintmsk; 1081 int status; 1082 int no_queue_space = 0; 1083 int no_fifo_space = 0; 1084 u32 qspcavail; 1085 1086 if (dbg_perio()) 1087 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1088 1089 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1090 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1091 TXSTS_QSPCAVAIL_SHIFT; 1092 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1093 TXSTS_FSPCAVAIL_SHIFT; 1094 1095 if (dbg_perio()) { 1096 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1097 qspcavail); 1098 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1099 fspcavail); 1100 } 1101 1102 qh_ptr = hsotg->periodic_sched_assigned.next; 1103 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1104 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1105 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1106 TXSTS_QSPCAVAIL_SHIFT; 1107 if (qspcavail == 0) { 1108 no_queue_space = 1; 1109 break; 1110 } 1111 1112 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1113 if (!qh->channel) { 1114 qh_ptr = qh_ptr->next; 1115 continue; 1116 } 1117 1118 /* Make sure EP's TT buffer is clean before queueing qtds */ 1119 if (qh->tt_buffer_dirty) { 1120 qh_ptr = qh_ptr->next; 1121 continue; 1122 } 1123 1124 /* 1125 * Set a flag if we're queuing high-bandwidth in slave mode. 1126 * The flag prevents any halts to get into the request queue in 1127 * the middle of multiple high-bandwidth packets getting queued. 1128 */ 1129 if (hsotg->core_params->dma_enable <= 0 && 1130 qh->channel->multi_count > 1) 1131 hsotg->queuing_high_bandwidth = 1; 1132 1133 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1134 TXSTS_FSPCAVAIL_SHIFT; 1135 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1136 if (status < 0) { 1137 no_fifo_space = 1; 1138 break; 1139 } 1140 1141 /* 1142 * In Slave mode, stay on the current transfer until there is 1143 * nothing more to do or the high-bandwidth request count is 1144 * reached. In DMA mode, only need to queue one request. The 1145 * controller automatically handles multiple packets for 1146 * high-bandwidth transfers. 1147 */ 1148 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1149 qh->channel->requests == qh->channel->multi_count) { 1150 qh_ptr = qh_ptr->next; 1151 /* 1152 * Move the QH from the periodic assigned schedule to 1153 * the periodic queued schedule 1154 */ 1155 list_move(&qh->qh_list_entry, 1156 &hsotg->periodic_sched_queued); 1157 1158 /* done queuing high bandwidth */ 1159 hsotg->queuing_high_bandwidth = 0; 1160 } 1161 } 1162 1163 if (hsotg->core_params->dma_enable <= 0) { 1164 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1165 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1166 TXSTS_QSPCAVAIL_SHIFT; 1167 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1168 TXSTS_FSPCAVAIL_SHIFT; 1169 if (dbg_perio()) { 1170 dev_vdbg(hsotg->dev, 1171 " P Tx Req Queue Space Avail (after queue): %d\n", 1172 qspcavail); 1173 dev_vdbg(hsotg->dev, 1174 " P Tx FIFO Space Avail (after queue): %d\n", 1175 fspcavail); 1176 } 1177 1178 if (!list_empty(&hsotg->periodic_sched_assigned) || 1179 no_queue_space || no_fifo_space) { 1180 /* 1181 * May need to queue more transactions as the request 1182 * queue or Tx FIFO empties. Enable the periodic Tx 1183 * FIFO empty interrupt. (Always use the half-empty 1184 * level to ensure that new requests are loaded as 1185 * soon as possible.) 1186 */ 1187 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1188 gintmsk |= GINTSTS_PTXFEMP; 1189 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1190 } else { 1191 /* 1192 * Disable the Tx FIFO empty interrupt since there are 1193 * no more transactions that need to be queued right 1194 * now. This function is called from interrupt 1195 * handlers to queue more transactions as transfer 1196 * states change. 1197 */ 1198 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1199 gintmsk &= ~GINTSTS_PTXFEMP; 1200 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1201 } 1202 } 1203 } 1204 1205 /* 1206 * Processes active non-periodic channels and queues transactions for these 1207 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1208 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1209 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1210 * FIFO Empty interrupt is disabled. 1211 * 1212 * Must be called with interrupt disabled and spinlock held 1213 */ 1214 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1215 { 1216 struct list_head *orig_qh_ptr; 1217 struct dwc2_qh *qh; 1218 u32 tx_status; 1219 u32 qspcavail; 1220 u32 fspcavail; 1221 u32 gintmsk; 1222 int status; 1223 int no_queue_space = 0; 1224 int no_fifo_space = 0; 1225 int more_to_do = 0; 1226 1227 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1228 1229 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1230 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1231 TXSTS_QSPCAVAIL_SHIFT; 1232 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1233 TXSTS_FSPCAVAIL_SHIFT; 1234 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1235 qspcavail); 1236 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1237 fspcavail); 1238 1239 /* 1240 * Keep track of the starting point. Skip over the start-of-list 1241 * entry. 1242 */ 1243 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1244 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1245 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1246 1247 /* 1248 * Process once through the active list or until no more space is 1249 * available in the request queue or the Tx FIFO 1250 */ 1251 do { 1252 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1253 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1254 TXSTS_QSPCAVAIL_SHIFT; 1255 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1256 no_queue_space = 1; 1257 break; 1258 } 1259 1260 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1261 qh_list_entry); 1262 if (!qh->channel) 1263 goto next; 1264 1265 /* Make sure EP's TT buffer is clean before queueing qtds */ 1266 if (qh->tt_buffer_dirty) 1267 goto next; 1268 1269 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1270 TXSTS_FSPCAVAIL_SHIFT; 1271 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1272 1273 if (status > 0) { 1274 more_to_do = 1; 1275 } else if (status < 0) { 1276 no_fifo_space = 1; 1277 break; 1278 } 1279 next: 1280 /* Advance to next QH, skipping start-of-list entry */ 1281 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1282 if (hsotg->non_periodic_qh_ptr == 1283 &hsotg->non_periodic_sched_active) 1284 hsotg->non_periodic_qh_ptr = 1285 hsotg->non_periodic_qh_ptr->next; 1286 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1287 1288 if (hsotg->core_params->dma_enable <= 0) { 1289 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1290 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1291 TXSTS_QSPCAVAIL_SHIFT; 1292 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1293 TXSTS_FSPCAVAIL_SHIFT; 1294 dev_vdbg(hsotg->dev, 1295 " NP Tx Req Queue Space Avail (after queue): %d\n", 1296 qspcavail); 1297 dev_vdbg(hsotg->dev, 1298 " NP Tx FIFO Space Avail (after queue): %d\n", 1299 fspcavail); 1300 1301 if (more_to_do || no_queue_space || no_fifo_space) { 1302 /* 1303 * May need to queue more transactions as the request 1304 * queue or Tx FIFO empties. Enable the non-periodic 1305 * Tx FIFO empty interrupt. (Always use the half-empty 1306 * level to ensure that new requests are loaded as 1307 * soon as possible.) 1308 */ 1309 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1310 gintmsk |= GINTSTS_NPTXFEMP; 1311 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1312 } else { 1313 /* 1314 * Disable the Tx FIFO empty interrupt since there are 1315 * no more transactions that need to be queued right 1316 * now. This function is called from interrupt 1317 * handlers to queue more transactions as transfer 1318 * states change. 1319 */ 1320 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1321 gintmsk &= ~GINTSTS_NPTXFEMP; 1322 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1323 } 1324 } 1325 } 1326 1327 /** 1328 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1329 * and queues transactions for these channels to the DWC_otg controller. Called 1330 * from the HCD interrupt handler functions. 1331 * 1332 * @hsotg: The HCD state structure 1333 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1334 * or both) 1335 * 1336 * Must be called with interrupt disabled and spinlock held 1337 */ 1338 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1339 enum dwc2_transaction_type tr_type) 1340 { 1341 #ifdef DWC2_DEBUG_SOF 1342 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1343 #endif 1344 /* Process host channels associated with periodic transfers */ 1345 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1346 tr_type == DWC2_TRANSACTION_ALL) && 1347 !list_empty(&hsotg->periodic_sched_assigned)) 1348 dwc2_process_periodic_channels(hsotg); 1349 1350 /* Process host channels associated with non-periodic transfers */ 1351 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1352 tr_type == DWC2_TRANSACTION_ALL) { 1353 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1354 dwc2_process_non_periodic_channels(hsotg); 1355 } else { 1356 /* 1357 * Ensure NP Tx FIFO empty interrupt is disabled when 1358 * there are no non-periodic transfers to process 1359 */ 1360 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1361 1362 gintmsk &= ~GINTSTS_NPTXFEMP; 1363 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1364 } 1365 } 1366 } 1367 1368 static void dwc2_conn_id_status_change(struct work_struct *work) 1369 { 1370 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1371 wf_otg); 1372 u32 count = 0; 1373 u32 gotgctl; 1374 unsigned long flags; 1375 1376 dev_dbg(hsotg->dev, "%s()\n", __func__); 1377 1378 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1379 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1380 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1381 !!(gotgctl & GOTGCTL_CONID_B)); 1382 1383 /* B-Device connector (Device Mode) */ 1384 if (gotgctl & GOTGCTL_CONID_B) { 1385 /* Wait for switch to device mode */ 1386 dev_dbg(hsotg->dev, "connId B\n"); 1387 while (!dwc2_is_device_mode(hsotg)) { 1388 dev_info(hsotg->dev, 1389 "Waiting for Peripheral Mode, Mode=%s\n", 1390 dwc2_is_host_mode(hsotg) ? "Host" : 1391 "Peripheral"); 1392 usleep_range(20000, 40000); 1393 if (++count > 250) 1394 break; 1395 } 1396 if (count > 250) 1397 dev_err(hsotg->dev, 1398 "Connection id status change timed out\n"); 1399 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1400 dwc2_core_init(hsotg, false); 1401 dwc2_enable_global_interrupts(hsotg); 1402 spin_lock_irqsave(&hsotg->lock, flags); 1403 dwc2_hsotg_core_init_disconnected(hsotg, false); 1404 spin_unlock_irqrestore(&hsotg->lock, flags); 1405 dwc2_hsotg_core_connect(hsotg); 1406 } else { 1407 /* A-Device connector (Host Mode) */ 1408 dev_dbg(hsotg->dev, "connId A\n"); 1409 while (!dwc2_is_host_mode(hsotg)) { 1410 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1411 dwc2_is_host_mode(hsotg) ? 1412 "Host" : "Peripheral"); 1413 usleep_range(20000, 40000); 1414 if (++count > 250) 1415 break; 1416 } 1417 if (count > 250) 1418 dev_err(hsotg->dev, 1419 "Connection id status change timed out\n"); 1420 hsotg->op_state = OTG_STATE_A_HOST; 1421 1422 /* Initialize the Core for Host mode */ 1423 dwc2_core_init(hsotg, false); 1424 dwc2_enable_global_interrupts(hsotg); 1425 dwc2_hcd_start(hsotg); 1426 } 1427 } 1428 1429 void dwc2_wakeup_detected(void *data) 1430 { 1431 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1432 u32 hprt0; 1433 1434 dev_dbg(hsotg->dev, "%s()\n", __func__); 1435 1436 /* 1437 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1438 * so that OPT tests pass with all PHYs.) 1439 */ 1440 hprt0 = dwc2_read_hprt0(hsotg); 1441 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1442 hprt0 &= ~HPRT0_RES; 1443 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1444 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1445 DWC2_READ_4(hsotg, HPRT0)); 1446 1447 dwc2_hcd_rem_wakeup(hsotg); 1448 hsotg->bus_suspended = 0; 1449 1450 /* Change to L0 state */ 1451 hsotg->lx_state = DWC2_L0; 1452 } 1453 1454 /* Must NOT be called with interrupt disabled or spinlock held */ 1455 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1456 { 1457 unsigned long flags; 1458 u32 hprt0; 1459 u32 pcgctl; 1460 u32 gotgctl; 1461 1462 dev_dbg(hsotg->dev, "%s()\n", __func__); 1463 1464 spin_lock_irqsave(&hsotg->lock, flags); 1465 1466 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1467 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1468 gotgctl |= GOTGCTL_HSTSETHNPEN; 1469 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1470 hsotg->op_state = OTG_STATE_A_SUSPEND; 1471 } 1472 1473 hprt0 = dwc2_read_hprt0(hsotg); 1474 hprt0 |= HPRT0_SUSP; 1475 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1476 1477 hsotg->bus_suspended = 1; 1478 1479 /* 1480 * If hibernation is supported, Phy clock will be suspended 1481 * after registers are backuped. 1482 */ 1483 if (!hsotg->core_params->hibernation) { 1484 /* Suspend the Phy Clock */ 1485 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1486 pcgctl |= PCGCTL_STOPPCLK; 1487 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1488 udelay(10); 1489 } 1490 1491 /* For HNP the bus must be suspended for at least 200ms */ 1492 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1493 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1494 pcgctl &= ~PCGCTL_STOPPCLK; 1495 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1496 1497 spin_unlock_irqrestore(&hsotg->lock, flags); 1498 1499 usleep_range(200000, 250000); 1500 } else { 1501 spin_unlock_irqrestore(&hsotg->lock, flags); 1502 } 1503 } 1504 1505 /* Must NOT be called with interrupt disabled or spinlock held */ 1506 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1507 { 1508 unsigned long flags; 1509 u32 hprt0; 1510 u32 pcgctl; 1511 1512 spin_lock_irqsave(&hsotg->lock, flags); 1513 1514 /* 1515 * If hibernation is supported, Phy clock is already resumed 1516 * after registers restore. 1517 */ 1518 if (!hsotg->core_params->hibernation) { 1519 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1520 pcgctl &= ~PCGCTL_STOPPCLK; 1521 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1522 spin_unlock_irqrestore(&hsotg->lock, flags); 1523 usleep_range(20000, 40000); 1524 spin_lock_irqsave(&hsotg->lock, flags); 1525 } 1526 1527 hprt0 = dwc2_read_hprt0(hsotg); 1528 hprt0 |= HPRT0_RES; 1529 hprt0 &= ~HPRT0_SUSP; 1530 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1531 spin_unlock_irqrestore(&hsotg->lock, flags); 1532 1533 msleep(USB_RESUME_TIMEOUT); 1534 1535 spin_lock_irqsave(&hsotg->lock, flags); 1536 hprt0 = dwc2_read_hprt0(hsotg); 1537 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1538 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1539 hsotg->bus_suspended = 0; 1540 spin_unlock_irqrestore(&hsotg->lock, flags); 1541 } 1542 1543 /* Handles hub class-specific requests */ 1544 int 1545 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1546 u16 wvalue, u16 windex, char *buf, u16 wlength) 1547 { 1548 usb_hub_descriptor_t *hub_desc; 1549 usb_port_status_t ps; 1550 int retval = 0; 1551 u32 hprt0; 1552 u32 port_status; 1553 u32 speed; 1554 u32 pcgctl; 1555 1556 switch (typereq) { 1557 case ClearHubFeature: 1558 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1559 1560 switch (wvalue) { 1561 case C_HUB_LOCAL_POWER: 1562 case C_HUB_OVER_CURRENT: 1563 /* Nothing required here */ 1564 break; 1565 1566 default: 1567 retval = -EINVAL; 1568 dev_err(hsotg->dev, 1569 "ClearHubFeature request %1xh unknown\n", 1570 wvalue); 1571 } 1572 break; 1573 1574 case ClearPortFeature: 1575 // if (wvalue != USB_PORT_FEAT_L1) 1576 if (!windex || windex > 1) 1577 goto error; 1578 switch (wvalue) { 1579 case USB_PORT_FEAT_ENABLE: 1580 dev_dbg(hsotg->dev, 1581 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1582 hprt0 = dwc2_read_hprt0(hsotg); 1583 hprt0 |= HPRT0_ENA; 1584 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1585 break; 1586 1587 case USB_PORT_FEAT_SUSPEND: 1588 dev_dbg(hsotg->dev, 1589 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1590 if (hsotg->bus_suspended) 1591 dwc2_port_resume(hsotg); 1592 break; 1593 1594 case USB_PORT_FEAT_POWER: 1595 dev_dbg(hsotg->dev, 1596 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1597 hprt0 = dwc2_read_hprt0(hsotg); 1598 hprt0 &= ~HPRT0_PWR; 1599 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1600 break; 1601 1602 case USB_PORT_FEAT_INDICATOR: 1603 dev_dbg(hsotg->dev, 1604 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1605 /* Port indicator not supported */ 1606 break; 1607 1608 case USB_PORT_FEAT_C_CONNECTION: 1609 /* 1610 * Clears driver's internal Connect Status Change flag 1611 */ 1612 dev_dbg(hsotg->dev, 1613 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1614 hsotg->flags.b.port_connect_status_change = 0; 1615 break; 1616 1617 case USB_PORT_FEAT_C_RESET: 1618 /* Clears driver's internal Port Reset Change flag */ 1619 dev_dbg(hsotg->dev, 1620 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1621 hsotg->flags.b.port_reset_change = 0; 1622 break; 1623 1624 case USB_PORT_FEAT_C_ENABLE: 1625 /* 1626 * Clears the driver's internal Port Enable/Disable 1627 * Change flag 1628 */ 1629 dev_dbg(hsotg->dev, 1630 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1631 hsotg->flags.b.port_enable_change = 0; 1632 break; 1633 1634 case USB_PORT_FEAT_C_SUSPEND: 1635 /* 1636 * Clears the driver's internal Port Suspend Change 1637 * flag, which is set when resume signaling on the host 1638 * port is complete 1639 */ 1640 dev_dbg(hsotg->dev, 1641 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1642 hsotg->flags.b.port_suspend_change = 0; 1643 break; 1644 1645 case USB_PORT_FEAT_C_PORT_L1: 1646 dev_dbg(hsotg->dev, 1647 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1648 hsotg->flags.b.port_l1_change = 0; 1649 break; 1650 1651 case USB_PORT_FEAT_C_OVER_CURRENT: 1652 dev_dbg(hsotg->dev, 1653 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1654 hsotg->flags.b.port_over_current_change = 0; 1655 break; 1656 1657 default: 1658 retval = -EINVAL; 1659 dev_err(hsotg->dev, 1660 "ClearPortFeature request %1xh unknown or unsupported\n", 1661 wvalue); 1662 } 1663 break; 1664 1665 case GetHubDescriptor: 1666 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1667 hub_desc = (usb_hub_descriptor_t *)buf; 1668 hub_desc->bDescLength = 9; 1669 hub_desc->bDescriptorType = USB_DT_HUB; 1670 hub_desc->bNbrPorts = 1; 1671 USETW(hub_desc->wHubCharacteristics, HUB_CHAR_COMMON_LPSM | 1672 HUB_CHAR_INDV_PORT_OCPM); 1673 hub_desc->bPwrOn2PwrGood = 1; 1674 hub_desc->bHubContrCurrent = 0; 1675 hub_desc->DeviceRemovable[0] = 0; 1676 hub_desc->DeviceRemovable[1] = 0xff; 1677 break; 1678 1679 case GetHubStatus: 1680 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1681 memset(buf, 0, 4); 1682 break; 1683 1684 case GetPortStatus: 1685 dev_vdbg(hsotg->dev, 1686 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1687 hsotg->flags.d32); 1688 if (!windex || windex > 1) 1689 goto error; 1690 1691 port_status = 0; 1692 if (hsotg->flags.b.port_connect_status_change) 1693 port_status |= USB_PORT_STAT_C_CONNECTION; 1694 if (hsotg->flags.b.port_enable_change) 1695 port_status |= USB_PORT_STAT_C_ENABLE; 1696 if (hsotg->flags.b.port_suspend_change) 1697 port_status |= USB_PORT_STAT_C_SUSPEND; 1698 if (hsotg->flags.b.port_l1_change) 1699 port_status |= USB_PORT_STAT_C_L1; 1700 if (hsotg->flags.b.port_reset_change) 1701 port_status |= USB_PORT_STAT_C_RESET; 1702 if (hsotg->flags.b.port_over_current_change) { 1703 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1704 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1705 } 1706 USETW(ps.wPortChange, port_status); 1707 1708 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1709 if (!hsotg->flags.b.port_connect_status) { 1710 /* 1711 * The port is disconnected, which means the core is 1712 * either in device mode or it soon will be. Just 1713 * return 0's for the remainder of the port status 1714 * since the port register can't be read if the core 1715 * is in device mode. 1716 */ 1717 USETW(ps.wPortStatus, 0); 1718 memcpy(buf, &ps, sizeof(ps)); 1719 break; 1720 } 1721 1722 port_status = 0; 1723 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1724 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1725 1726 if (hprt0 & HPRT0_CONNSTS) 1727 port_status |= USB_PORT_STAT_CONNECTION; 1728 if (hprt0 & HPRT0_ENA) 1729 port_status |= USB_PORT_STAT_ENABLE; 1730 if (hprt0 & HPRT0_SUSP) 1731 port_status |= USB_PORT_STAT_SUSPEND; 1732 if (hprt0 & HPRT0_OVRCURRACT) 1733 port_status |= USB_PORT_STAT_OVERCURRENT; 1734 if (hprt0 & HPRT0_RST) 1735 port_status |= USB_PORT_STAT_RESET; 1736 if (hprt0 & HPRT0_PWR) 1737 port_status |= USB_PORT_STAT_POWER; 1738 1739 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1740 if (speed == HPRT0_SPD_HIGH_SPEED) 1741 port_status |= USB_PORT_STAT_HIGH_SPEED; 1742 else if (speed == HPRT0_SPD_LOW_SPEED) 1743 port_status |= USB_PORT_STAT_LOW_SPEED; 1744 1745 if (hprt0 & HPRT0_TSTCTL_MASK) 1746 port_status |= USB_PORT_STAT_TEST; 1747 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1748 USETW(ps.wPortStatus, port_status); 1749 1750 if (hsotg->core_params->dma_desc_fs_enable) { 1751 /* 1752 * Enable descriptor DMA only if a full speed 1753 * device is connected. 1754 */ 1755 if (hsotg->new_connection && 1756 ((port_status & 1757 (USB_PORT_STAT_CONNECTION | 1758 USB_PORT_STAT_HIGH_SPEED | 1759 USB_PORT_STAT_LOW_SPEED)) == 1760 USB_PORT_STAT_CONNECTION)) { 1761 u32 hcfg; 1762 1763 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 1764 hsotg->core_params->dma_desc_enable = 1; 1765 hcfg = DWC2_READ_4(hsotg, HCFG); 1766 hcfg |= HCFG_DESCDMA; 1767 DWC2_WRITE_4(hsotg, HCFG, hcfg); 1768 hsotg->new_connection = false; 1769 } 1770 } 1771 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1772 memcpy(buf, &ps, sizeof(ps)); 1773 break; 1774 1775 case SetHubFeature: 1776 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1777 /* No HUB features supported */ 1778 break; 1779 1780 case SetPortFeature: 1781 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1782 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1783 goto error; 1784 1785 if (!hsotg->flags.b.port_connect_status) { 1786 /* 1787 * The port is disconnected, which means the core is 1788 * either in device mode or it soon will be. Just 1789 * return without doing anything since the port 1790 * register can't be written if the core is in device 1791 * mode. 1792 */ 1793 break; 1794 } 1795 1796 switch (wvalue) { 1797 case USB_PORT_FEAT_SUSPEND: 1798 dev_dbg(hsotg->dev, 1799 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1800 if (windex != hsotg->otg_port) 1801 goto error; 1802 dwc2_port_suspend(hsotg, windex); 1803 break; 1804 1805 case USB_PORT_FEAT_POWER: 1806 dev_dbg(hsotg->dev, 1807 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1808 hprt0 = dwc2_read_hprt0(hsotg); 1809 hprt0 |= HPRT0_PWR; 1810 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1811 break; 1812 1813 case USB_PORT_FEAT_RESET: 1814 hprt0 = dwc2_read_hprt0(hsotg); 1815 dev_dbg(hsotg->dev, 1816 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1817 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1818 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1819 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1820 /* ??? Original driver does this */ 1821 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1822 1823 hprt0 = dwc2_read_hprt0(hsotg); 1824 /* Clear suspend bit if resetting from suspend state */ 1825 hprt0 &= ~HPRT0_SUSP; 1826 1827 /* 1828 * When B-Host the Port reset bit is set in the Start 1829 * HCD Callback function, so that the reset is started 1830 * within 1ms of the HNP success interrupt 1831 */ 1832 if (!dwc2_hcd_is_b_host(hsotg)) { 1833 hprt0 |= HPRT0_PWR | HPRT0_RST; 1834 dev_dbg(hsotg->dev, 1835 "In host mode, hprt0=%08x\n", hprt0); 1836 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1837 } 1838 1839 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1840 usleep_range(50000, 70000); 1841 hprt0 &= ~HPRT0_RST; 1842 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1843 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1844 break; 1845 1846 case USB_PORT_FEAT_INDICATOR: 1847 dev_dbg(hsotg->dev, 1848 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1849 /* Not supported */ 1850 break; 1851 1852 case USB_PORT_FEAT_TEST: 1853 hprt0 = dwc2_read_hprt0(hsotg); 1854 dev_dbg(hsotg->dev, 1855 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1856 hprt0 &= ~HPRT0_TSTCTL_MASK; 1857 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1858 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1859 break; 1860 1861 default: 1862 retval = -EINVAL; 1863 dev_err(hsotg->dev, 1864 "SetPortFeature %1xh unknown or unsupported\n", 1865 wvalue); 1866 break; 1867 } 1868 break; 1869 1870 default: 1871 error: 1872 retval = -EINVAL; 1873 dev_dbg(hsotg->dev, 1874 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1875 typereq, windex, wvalue); 1876 break; 1877 } 1878 1879 return retval; 1880 } 1881 1882 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1883 { 1884 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1885 1886 #ifdef DWC2_DEBUG_SOF 1887 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1888 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1889 #endif 1890 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1891 } 1892 1893 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1894 { 1895 return hsotg->op_state == OTG_STATE_B_HOST; 1896 } 1897 1898 struct dwc2_hcd_urb * 1899 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1900 gfp_t mem_flags) 1901 { 1902 struct dwc2_hcd_urb *urb; 1903 u32 size = sizeof(*urb) + iso_desc_count * 1904 sizeof(struct dwc2_hcd_iso_packet_desc); 1905 1906 urb = kmem_zalloc(size, mem_flags); 1907 if (urb) 1908 urb->packet_count = iso_desc_count; 1909 return urb; 1910 } 1911 1912 void 1913 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1914 int iso_desc_count) 1915 { 1916 1917 u32 size = sizeof(*urb) + iso_desc_count * 1918 sizeof(struct dwc2_hcd_iso_packet_desc); 1919 1920 kmem_free(urb, size); 1921 } 1922 1923 void 1924 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1925 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1926 u16 mps) 1927 { 1928 if (dbg_perio() || 1929 ep_type == USB_ENDPOINT_XFER_BULK || 1930 ep_type == USB_ENDPOINT_XFER_CONTROL) 1931 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1932 urb->pipe_info.dev_addr = dev_addr; 1933 urb->pipe_info.ep_num = ep_num; 1934 urb->pipe_info.pipe_type = ep_type; 1935 urb->pipe_info.pipe_dir = ep_dir; 1936 urb->pipe_info.mps = mps; 1937 } 1938 1939 /* 1940 * NOTE: This function will be removed once the peripheral controller code 1941 * is integrated and the driver is stable 1942 */ 1943 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1944 { 1945 #ifdef DWC2_DEBUG 1946 struct dwc2_host_chan *chan; 1947 struct dwc2_hcd_urb *urb; 1948 struct dwc2_qtd *qtd; 1949 int num_channels; 1950 u32 np_tx_status; 1951 u32 p_tx_status; 1952 int i; 1953 1954 num_channels = hsotg->core_params->host_channels; 1955 dev_dbg(hsotg->dev, "\n"); 1956 dev_dbg(hsotg->dev, 1957 "************************************************************\n"); 1958 dev_dbg(hsotg->dev, "HCD State:\n"); 1959 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1960 1961 for (i = 0; i < num_channels; i++) { 1962 chan = hsotg->hc_ptr_array[i]; 1963 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1964 dev_dbg(hsotg->dev, 1965 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1966 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1967 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1968 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1969 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1970 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1971 chan->data_pid_start); 1972 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1973 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1974 chan->xfer_started); 1975 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1976 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1977 (unsigned long)chan->xfer_dma); 1978 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1979 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1980 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1981 chan->halt_on_queue); 1982 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1983 chan->halt_pending); 1984 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1985 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1986 dev_dbg(hsotg->dev, " complete_split: %d\n", 1987 chan->complete_split); 1988 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1989 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1990 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1991 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1992 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1993 1994 if (chan->xfer_started) { 1995 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", 1996 DWC2_READ_4(hsotg, HFNUM)); 1997 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", 1998 DWC2_READ_4(hsotg, HCCHAR(i))); 1999 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", 2000 DWC2_READ_4(hsotg, HCTSIZ(i))); 2001 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", 2002 DWC2_READ_4(hsotg, HCINT(i))); 2003 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", 2004 DWC2_READ_4(hsotg, HCINTMSK(i))); 2005 } 2006 2007 if (!(chan->xfer_started && chan->qh)) 2008 continue; 2009 2010 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 2011 if (!qtd->in_process) 2012 break; 2013 urb = qtd->urb; 2014 dev_dbg(hsotg->dev, " URB Info:\n"); 2015 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2016 qtd, urb); 2017 if (urb) { 2018 dev_dbg(hsotg->dev, 2019 " Dev: %d, EP: %d %s\n", 2020 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2021 dwc2_hcd_get_ep_num(&urb->pipe_info), 2022 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2023 "IN" : "OUT"); 2024 dev_dbg(hsotg->dev, 2025 " Max packet size: %d\n", 2026 dwc2_hcd_get_mps(&urb->pipe_info)); 2027 dev_dbg(hsotg->dev, 2028 " transfer_buffer: %p\n", 2029 urb->buf); 2030 dev_dbg(hsotg->dev, 2031 " transfer_dma: %08lx\n", 2032 (unsigned long)urb->dma); 2033 dev_dbg(hsotg->dev, 2034 " transfer_buffer_length: %d\n", 2035 urb->length); 2036 dev_dbg(hsotg->dev, " actual_length: %d\n", 2037 urb->actual_length); 2038 } 2039 } 2040 } 2041 2042 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2043 hsotg->non_periodic_channels); 2044 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2045 hsotg->periodic_channels); 2046 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2047 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 2048 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2049 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2050 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2051 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2052 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 2053 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2054 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2055 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2056 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2057 dwc2_hcd_dump_frrem(hsotg); 2058 2059 dwc2_dump_global_registers(hsotg); 2060 dwc2_dump_host_registers(hsotg); 2061 dev_dbg(hsotg->dev, 2062 "************************************************************\n"); 2063 dev_dbg(hsotg->dev, "\n"); 2064 #endif 2065 } 2066 2067 /* 2068 * NOTE: This function will be removed once the peripheral controller code 2069 * is integrated and the driver is stable 2070 */ 2071 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2072 { 2073 #ifdef DWC2_DUMP_FRREM 2074 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2075 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2076 hsotg->frrem_samples, hsotg->frrem_accum, 2077 hsotg->frrem_samples > 0 ? 2078 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2079 dev_dbg(hsotg->dev, "\n"); 2080 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2081 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2082 hsotg->hfnum_7_samples, 2083 hsotg->hfnum_7_frrem_accum, 2084 hsotg->hfnum_7_samples > 0 ? 2085 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2086 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2087 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2088 hsotg->hfnum_0_samples, 2089 hsotg->hfnum_0_frrem_accum, 2090 hsotg->hfnum_0_samples > 0 ? 2091 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2092 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2093 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2094 hsotg->hfnum_other_samples, 2095 hsotg->hfnum_other_frrem_accum, 2096 hsotg->hfnum_other_samples > 0 ? 2097 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2098 0); 2099 dev_dbg(hsotg->dev, "\n"); 2100 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2101 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2102 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2103 hsotg->hfnum_7_samples_a > 0 ? 2104 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2105 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2106 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2107 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2108 hsotg->hfnum_0_samples_a > 0 ? 2109 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2110 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2111 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2112 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2113 hsotg->hfnum_other_samples_a > 0 ? 2114 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2115 : 0); 2116 dev_dbg(hsotg->dev, "\n"); 2117 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2118 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2119 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2120 hsotg->hfnum_7_samples_b > 0 ? 2121 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2122 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2123 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2124 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2125 (hsotg->hfnum_0_samples_b > 0) ? 2126 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2127 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2128 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2129 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2130 (hsotg->hfnum_other_samples_b > 0) ? 2131 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2132 : 0); 2133 #endif 2134 } 2135 2136 struct wrapper_priv_data { 2137 struct dwc2_hsotg *hsotg; 2138 }; 2139 2140 2141 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2142 { 2143 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2144 2145 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2146 _dwc2_hcd_start(hsotg); 2147 } 2148 2149 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2150 { 2151 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2152 2153 // hcd->self.is_b_host = 0; 2154 } 2155 2156 /* 2157 * Work queue function for starting the HCD when A-Cable is connected 2158 */ 2159 static void dwc2_hcd_start_func(struct work_struct *work) 2160 { 2161 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2162 start_work.work); 2163 2164 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2165 dwc2_host_start(hsotg); 2166 } 2167 2168 /* 2169 * Reset work queue function 2170 */ 2171 static void dwc2_hcd_reset_func(struct work_struct *work) 2172 { 2173 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2174 reset_work.work); 2175 unsigned long flags; 2176 u32 hprt0; 2177 2178 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2179 2180 spin_lock_irqsave(&hsotg->lock, flags); 2181 2182 hprt0 = dwc2_read_hprt0(hsotg); 2183 hprt0 &= ~HPRT0_RST; 2184 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2185 hsotg->flags.b.port_reset_change = 1; 2186 2187 dwc2_root_intr(hsotg->hsotg_sc); 2188 2189 spin_unlock_irqrestore(&hsotg->lock, flags); 2190 } 2191 2192 /* 2193 * ========================================================================= 2194 * Linux HC Driver Functions 2195 * ========================================================================= 2196 */ 2197 2198 /* 2199 * Initializes the DWC_otg controller and its root hub and prepares it for host 2200 * mode operation. Activates the root port. Returns 0 on success and a negative 2201 * error code on failure. 2202 */ 2203 2204 /* 2205 * Frees secondary storage associated with the dwc2_hsotg structure contained 2206 * in the struct usb_hcd field 2207 */ 2208 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2209 { 2210 u32 ahbcfg; 2211 u32 dctl; 2212 int i; 2213 2214 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2215 2216 /* Free memory for QH/QTD lists */ 2217 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2218 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2219 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2220 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2221 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2222 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2223 2224 /* Free memory for the host channels */ 2225 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2226 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2227 2228 if (chan != NULL) { 2229 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2230 i, chan); 2231 hsotg->hc_ptr_array[i] = NULL; 2232 kmem_free(chan, sizeof(*chan)); 2233 } 2234 } 2235 2236 if (hsotg->core_params->dma_enable > 0) { 2237 if (hsotg->status_buf) { 2238 usb_freemem(&hsotg->hsotg_sc->sc_bus, 2239 &hsotg->status_buf_usbdma); 2240 hsotg->status_buf = NULL; 2241 } 2242 } else { 2243 kmem_free(hsotg->status_buf,DWC2_HCD_STATUS_BUF_SIZE); 2244 hsotg->status_buf = NULL; 2245 } 2246 2247 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2248 2249 /* Disable all interrupts */ 2250 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2251 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2252 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2253 2254 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2255 dctl = DWC2_READ_4(hsotg, DCTL); 2256 dctl |= DCTL_SFTDISCON; 2257 DWC2_WRITE_4(hsotg, DCTL, dctl); 2258 } 2259 2260 if (hsotg->wq_otg) { 2261 if (!cancel_work_sync(&hsotg->wf_otg)) 2262 flush_workqueue(hsotg->wq_otg); 2263 destroy_workqueue(hsotg->wq_otg); 2264 } 2265 2266 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2267 hsotg->core_params = NULL; 2268 callout_destroy(&hsotg->wkp_timer); 2269 } 2270 2271 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2272 { 2273 /* Turn off all host-specific interrupts */ 2274 dwc2_disable_host_interrupts(hsotg); 2275 2276 dwc2_hcd_free(hsotg); 2277 } 2278 2279 /* 2280 * Initializes the HCD. This function allocates memory for and initializes the 2281 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2282 * USB bus with the core and calls the hc_driver->start() function. It returns 2283 * a negative error on failure. 2284 */ 2285 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 2286 { 2287 struct dwc2_host_chan *channel; 2288 int i, num_channels; 2289 int retval; 2290 2291 if (usb_disabled()) 2292 return -ENODEV; 2293 2294 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2295 2296 retval = -ENOMEM; 2297 2298 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG)); 2299 2300 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2301 hsotg->frame_num_array = kmem_zalloc(sizeof(*hsotg->frame_num_array) * 2302 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2303 if (!hsotg->frame_num_array) 2304 goto error1; 2305 hsotg->last_frame_num_array = kmem_zalloc( 2306 sizeof(*hsotg->last_frame_num_array) * 2307 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2308 if (!hsotg->last_frame_num_array) 2309 goto error1; 2310 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2311 #endif 2312 2313 spin_lock_init(&hsotg->lock); 2314 2315 /* 2316 * Disable the global interrupt until all the interrupt handlers are 2317 * installed 2318 */ 2319 dwc2_disable_global_interrupts(hsotg); 2320 2321 /* Initialize the DWC_otg core, and select the Phy type */ 2322 retval = dwc2_core_init(hsotg, true); 2323 if (retval) 2324 goto error2; 2325 2326 /* Create new workqueue and init work */ 2327 retval = -ENOMEM; 2328 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 2329 if (!hsotg->wq_otg) { 2330 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2331 goto error2; 2332 } 2333 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 2334 2335 callout_init(&hsotg->wkp_timer, CALLOUT_MPSAFE); 2336 callout_setfunc(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2337 2338 /* Initialize the non-periodic schedule */ 2339 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2340 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2341 2342 /* Initialize the periodic schedule */ 2343 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2344 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2345 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2346 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2347 2348 /* 2349 * Create a host channel descriptor for each host channel implemented 2350 * in the controller. Initialize the channel descriptor array. 2351 */ 2352 INIT_LIST_HEAD(&hsotg->free_hc_list); 2353 num_channels = hsotg->core_params->host_channels; 2354 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2355 2356 for (i = 0; i < num_channels; i++) { 2357 channel = kmem_zalloc(sizeof(*channel), KM_SLEEP); 2358 if (channel == NULL) 2359 goto error3; 2360 channel->hc_num = i; 2361 hsotg->hc_ptr_array[i] = channel; 2362 } 2363 2364 if (hsotg->core_params->uframe_sched > 0) 2365 dwc2_hcd_init_usecs(hsotg); 2366 2367 /* Initialize hsotg start work */ 2368 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2369 2370 /* Initialize port reset work */ 2371 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2372 2373 /* 2374 * Allocate space for storing data on status transactions. Normally no 2375 * data is sent, but this space acts as a bit bucket. This must be 2376 * done after usb_add_hcd since that function allocates the DMA buffer 2377 * pool. 2378 */ 2379 hsotg->status_buf = NULL; 2380 if (hsotg->core_params->dma_enable > 0) { 2381 retval = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 2382 DWC2_HCD_STATUS_BUF_SIZE, 0, 2383 &hsotg->status_buf_usbdma); 2384 if (!retval) { 2385 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2386 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2387 } 2388 } else 2389 hsotg->status_buf = kmem_zalloc(DWC2_HCD_STATUS_BUF_SIZE, 2390 KM_SLEEP); 2391 2392 if (!hsotg->status_buf) 2393 goto error3; 2394 2395 hsotg->otg_port = 1; 2396 hsotg->frame_list = NULL; 2397 hsotg->frame_list_dma = 0; 2398 hsotg->periodic_qh_count = 0; 2399 2400 /* Initiate lx_state to L3 disconnected state */ 2401 hsotg->lx_state = DWC2_L3; 2402 2403 _dwc2_hcd_start(hsotg); 2404 2405 dwc2_hcd_dump_state(hsotg); 2406 2407 dwc2_enable_global_interrupts(hsotg); 2408 2409 return 0; 2410 2411 error3: 2412 dwc2_hcd_release(hsotg); 2413 error2: 2414 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2415 2416 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2417 kmem_free(hsotg->last_frame_num_array, 2418 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2419 kmem_free(hsotg->frame_num_array, 2420 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2421 #endif 2422 2423 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2424 return retval; 2425 } 2426 2427 /* 2428 * Removes the HCD. 2429 * Frees memory and resources associated with the HCD and deregisters the bus. 2430 */ 2431 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 2432 { 2433 struct usb_hcd *hcd; 2434 2435 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 2436 2437 hcd = dwc2_hsotg_to_hcd(hsotg); 2438 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 2439 2440 if (!hcd) { 2441 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 2442 __func__); 2443 return; 2444 } 2445 hsotg->priv = NULL; 2446 2447 dwc2_hcd_release(hsotg); 2448 2449 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2450 kfree(hsotg->last_frame_num_array); 2451 kfree(hsotg->frame_num_array); 2452 #endif 2453 } 2454