1 /* $NetBSD: dwc2_hcd.c,v 1.9 2013/11/24 12:25:19 skrll Exp $ */ 2 3 /* 4 * hcd.c - DesignWare HS OTG Controller host-mode routines 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the core HCD code, and implements the Linux hc_driver 41 * API 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.9 2013/11/24 12:25:19 skrll Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/pool.h> 51 #include <sys/workqueue.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <linux/kernel.h> 59 #include <linux/list.h> 60 61 #include <dwc2/dwc2.h> 62 #include <dwc2/dwc2var.h> 63 64 #include "dwc2_core.h" 65 #include "dwc2_hcd.h" 66 67 /** 68 * dwc2_dump_channel_info() - Prints the state of a host channel 69 * 70 * @hsotg: Programming view of DWC_otg controller 71 * @chan: Pointer to the channel to dump 72 * 73 * Must be called with interrupt disabled and spinlock held 74 * 75 * NOTE: This function will be removed once the peripheral controller code 76 * is integrated and the driver is stable 77 */ 78 #ifdef VERBOSE_DEBUG 79 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 80 struct dwc2_host_chan *chan) 81 { 82 int num_channels = hsotg->core_params->host_channels; 83 struct dwc2_qh *qh; 84 u32 hcchar; 85 u32 hcsplt; 86 u32 hctsiz; 87 u32 hc_dma; 88 int i; 89 90 if (chan == NULL) 91 return; 92 93 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 94 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 95 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 96 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 97 98 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 99 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 100 hcchar, hcsplt); 101 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 102 hctsiz, hc_dma); 103 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 104 chan->dev_addr, chan->ep_num, chan->ep_is_in); 105 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 106 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 107 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 108 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 109 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 110 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 111 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 112 (unsigned long)chan->xfer_dma); 113 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 114 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 115 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 116 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 117 qh_list_entry) 118 dev_dbg(hsotg->dev, " %p\n", qh); 119 dev_dbg(hsotg->dev, " NP active sched:\n"); 120 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 121 qh_list_entry) 122 dev_dbg(hsotg->dev, " %p\n", qh); 123 dev_dbg(hsotg->dev, " Channels:\n"); 124 for (i = 0; i < num_channels; i++) { 125 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 126 127 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 128 } 129 } 130 #endif /* VERBOSE_DEBUG */ 131 132 /* 133 * Processes all the URBs in a single list of QHs. Completes them with 134 * -ETIMEDOUT and frees the QTD. 135 * 136 * Must be called with interrupt disabled and spinlock held 137 */ 138 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 139 struct list_head *qh_list) 140 { 141 struct dwc2_qh *qh, *qh_tmp; 142 struct dwc2_qtd *qtd, *qtd_tmp; 143 144 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 145 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 146 qtd_list_entry) { 147 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 148 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 149 } 150 } 151 } 152 153 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 154 struct list_head *qh_list) 155 { 156 struct dwc2_qtd *qtd, *qtd_tmp; 157 struct dwc2_qh *qh, *qh_tmp; 158 unsigned long flags; 159 160 if (!qh_list->next) 161 /* The list hasn't been initialized yet */ 162 return; 163 164 spin_lock_irqsave(&hsotg->lock, flags); 165 166 /* Ensure there are no QTDs or URBs left */ 167 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 168 169 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 170 dwc2_hcd_qh_unlink(hsotg, qh); 171 172 /* Free each QTD in the QH's QTD list */ 173 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 174 qtd_list_entry) 175 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 176 177 spin_unlock_irqrestore(&hsotg->lock, flags); 178 dwc2_hcd_qh_free(hsotg, qh); 179 spin_lock_irqsave(&hsotg->lock, flags); 180 } 181 182 spin_unlock_irqrestore(&hsotg->lock, flags); 183 } 184 185 /* 186 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 187 * and periodic schedules. The QTD associated with each URB is removed from 188 * the schedule and freed. This function may be called when a disconnect is 189 * detected or when the HCD is being stopped. 190 * 191 * Must be called with interrupt disabled and spinlock held 192 */ 193 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 194 { 195 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 196 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 197 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 198 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 199 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 201 } 202 203 /** 204 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 205 * 206 * @hsotg: Pointer to struct dwc2_hsotg 207 */ 208 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 209 { 210 u32 hprt0; 211 212 if (hsotg->op_state == OTG_STATE_B_HOST) { 213 /* 214 * Reset the port. During a HNP mode switch the reset 215 * needs to occur within 1ms and have a duration of at 216 * least 50ms. 217 */ 218 hprt0 = dwc2_read_hprt0(hsotg); 219 hprt0 |= HPRT0_RST; 220 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 221 } 222 223 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 224 msecs_to_jiffies(50)); 225 } 226 227 /* Must be called with interrupt disabled and spinlock held */ 228 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 229 { 230 int num_channels = hsotg->core_params->host_channels; 231 struct dwc2_host_chan *channel; 232 u32 hcchar; 233 int i; 234 235 if (hsotg->core_params->dma_enable <= 0) { 236 /* Flush out any channel requests in slave mode */ 237 for (i = 0; i < num_channels; i++) { 238 channel = hsotg->hc_ptr_array[i]; 239 if (!list_empty(&channel->hc_list_entry)) 240 continue; 241 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 242 if (hcchar & HCCHAR_CHENA) { 243 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 244 hcchar |= HCCHAR_CHDIS; 245 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 246 } 247 } 248 } 249 250 for (i = 0; i < num_channels; i++) { 251 channel = hsotg->hc_ptr_array[i]; 252 if (!list_empty(&channel->hc_list_entry)) 253 continue; 254 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 255 if (hcchar & HCCHAR_CHENA) { 256 /* Halt the channel */ 257 hcchar |= HCCHAR_CHDIS; 258 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 259 } 260 261 dwc2_hc_cleanup(hsotg, channel); 262 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 263 /* 264 * Added for Descriptor DMA to prevent channel double cleanup in 265 * release_channel_ddma(), which is called from ep_disable when 266 * device disconnects 267 */ 268 channel->qh = NULL; 269 } 270 } 271 272 /** 273 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 274 * 275 * @hsotg: Pointer to struct dwc2_hsotg 276 * 277 * Must be called with interrupt disabled and spinlock held 278 */ 279 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 280 { 281 u32 intr; 282 283 /* Set status flags for the hub driver */ 284 hsotg->flags.b.port_connect_status_change = 1; 285 hsotg->flags.b.port_connect_status = 0; 286 287 /* 288 * Shutdown any transfers in process by clearing the Tx FIFO Empty 289 * interrupt mask and status bits and disabling subsequent host 290 * channel interrupts. 291 */ 292 intr = DWC2_READ_4(hsotg, GINTMSK); 293 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 294 DWC2_WRITE_4(hsotg, GINTMSK, intr); 295 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 296 DWC2_WRITE_4(hsotg, GINTSTS, intr); 297 298 /* 299 * Turn off the vbus power only if the core has transitioned to device 300 * mode. If still in host mode, need to keep power on to detect a 301 * reconnection. 302 */ 303 if (dwc2_is_device_mode(hsotg)) { 304 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 305 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 306 DWC2_WRITE_4(hsotg, HPRT0, 0); 307 } 308 309 dwc2_disable_host_interrupts(hsotg); 310 } 311 312 /* Respond with an error status to all URBs in the schedule */ 313 dwc2_kill_all_urbs(hsotg); 314 315 if (dwc2_is_host_mode(hsotg)) 316 /* Clean up any host channels that were in use */ 317 dwc2_hcd_cleanup_channels(hsotg); 318 319 dwc2_host_disconnect(hsotg); 320 321 dwc2_root_intr(hsotg->hsotg_sc); 322 } 323 324 /** 325 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 326 * 327 * @hsotg: Pointer to struct dwc2_hsotg 328 */ 329 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 330 { 331 if (hsotg->lx_state == DWC2_L2) 332 hsotg->flags.b.port_suspend_change = 1; 333 else 334 hsotg->flags.b.port_l1_change = 1; 335 336 dwc2_root_intr(hsotg->hsotg_sc); 337 } 338 339 /** 340 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 341 * 342 * @hsotg: Pointer to struct dwc2_hsotg 343 * 344 * Must be called with interrupt disabled and spinlock held 345 */ 346 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 347 { 348 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 349 350 /* 351 * The root hub should be disconnected before this function is called. 352 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 353 * and the QH lists (via ..._hcd_endpoint_disable). 354 */ 355 356 /* Turn off all host-specific interrupts */ 357 dwc2_disable_host_interrupts(hsotg); 358 359 /* Turn off the vbus power */ 360 dev_dbg(hsotg->dev, "PortPower off\n"); 361 DWC2_WRITE_4(hsotg, HPRT0, 0); 362 } 363 364 int 365 dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 366 void **ep_handle, gfp_t mem_flags) 367 { 368 struct dwc2_softc *sc = hsotg->hsotg_sc; 369 struct dwc2_qtd *qtd; 370 unsigned long flags; 371 u32 intr_mask; 372 int retval; 373 int dev_speed; 374 375 if (!hsotg->flags.b.port_connect_status) { 376 /* No longer connected */ 377 dev_err(hsotg->dev, "Not connected\n"); 378 return -ENODEV; 379 } 380 381 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 382 383 /* Some core configurations cannot support LS traffic on a FS root port */ 384 if ((dev_speed == USB_SPEED_LOW) && 385 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 386 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 387 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 388 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 389 390 if (prtspd == HPRT0_SPD_FULL_SPEED) { 391 return -ENODEV; 392 } 393 } 394 395 qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT); 396 if (!qtd) 397 return -ENOMEM; 398 399 memset(qtd, 0, sizeof(*qtd)); 400 401 dwc2_hcd_qtd_init(qtd, urb); 402 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 403 mem_flags); 404 if (retval < 0) { 405 dev_err(hsotg->dev, 406 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 407 retval); 408 pool_cache_put(sc->sc_qtdpool, qtd); 409 return retval; 410 } 411 412 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 413 if (!(intr_mask & GINTSTS_SOF) && retval == 0) { 414 enum dwc2_transaction_type tr_type; 415 416 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 417 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 418 /* 419 * Do not schedule SG transactions until qtd has 420 * URB_GIVEBACK_ASAP set 421 */ 422 return 0; 423 424 spin_lock_irqsave(&hsotg->lock, flags); 425 tr_type = dwc2_hcd_select_transactions(hsotg); 426 if (tr_type != DWC2_TRANSACTION_NONE) 427 dwc2_hcd_queue_transactions(hsotg, tr_type); 428 spin_unlock_irqrestore(&hsotg->lock, flags); 429 } 430 431 return retval; 432 } 433 434 /* Must be called with interrupt disabled and spinlock held */ 435 int 436 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 437 struct dwc2_hcd_urb *urb) 438 { 439 struct dwc2_qh *qh; 440 struct dwc2_qtd *urb_qtd; 441 442 urb_qtd = urb->qtd; 443 if (!urb_qtd) { 444 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 445 return -EINVAL; 446 } 447 448 qh = urb_qtd->qh; 449 if (!qh) { 450 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 451 return -EINVAL; 452 } 453 454 urb->priv = NULL; 455 456 if (urb_qtd->in_process && qh->channel) { 457 #ifdef VERBOSE_DEBUG 458 dwc2_dump_channel_info(hsotg, qh->channel); 459 #endif 460 /* The QTD is in process (it has been assigned to a channel) */ 461 if (hsotg->flags.b.port_connect_status) 462 /* 463 * If still connected (i.e. in host mode), halt the 464 * channel so it can be used for other transfers. If 465 * no longer connected, the host registers can't be 466 * written to halt the channel since the core is in 467 * device mode. 468 */ 469 dwc2_hc_halt(hsotg, qh->channel, 470 DWC2_HC_XFER_URB_DEQUEUE); 471 } 472 473 /* 474 * Free the QTD and clean up the associated QH. Leave the QH in the 475 * schedule if it has any remaining QTDs. 476 */ 477 if (hsotg->core_params->dma_desc_enable <= 0) { 478 u8 in_process = urb_qtd->in_process; 479 480 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 481 if (in_process) { 482 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 483 qh->channel = NULL; 484 } else if (list_empty(&qh->qtd_list)) { 485 dwc2_hcd_qh_unlink(hsotg, qh); 486 } 487 } else { 488 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 489 } 490 491 return 0; 492 } 493 494 495 /* 496 * Initializes dynamic portions of the DWC_otg HCD state 497 * 498 * Must be called with interrupt disabled and spinlock held 499 */ 500 void 501 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 502 { 503 struct dwc2_host_chan *chan, *chan_tmp; 504 int num_channels; 505 int i; 506 507 hsotg->flags.d32 = 0; 508 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 509 510 if (hsotg->core_params->uframe_sched > 0) { 511 hsotg->available_host_channels = 512 hsotg->core_params->host_channels; 513 } else { 514 hsotg->non_periodic_channels = 0; 515 hsotg->periodic_channels = 0; 516 } 517 518 /* 519 * Put all channels in the free channel list and clean up channel 520 * states 521 */ 522 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 523 hc_list_entry) 524 list_del_init(&chan->hc_list_entry); 525 526 num_channels = hsotg->core_params->host_channels; 527 for (i = 0; i < num_channels; i++) { 528 chan = hsotg->hc_ptr_array[i]; 529 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 530 dwc2_hc_cleanup(hsotg, chan); 531 } 532 533 /* Initialize the DWC core for host mode operation */ 534 dwc2_core_host_init(hsotg); 535 } 536 537 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 538 struct dwc2_host_chan *chan, 539 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 540 { 541 int hub_addr, hub_port; 542 543 chan->do_split = 1; 544 chan->xact_pos = qtd->isoc_split_pos; 545 chan->complete_split = qtd->complete_split; 546 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 547 chan->hub_addr = (u8)hub_addr; 548 chan->hub_port = (u8)hub_port; 549 } 550 551 static void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 552 struct dwc2_host_chan *chan, 553 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 554 { 555 if (hsotg->core_params->dma_enable > 0) { 556 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 557 558 /* For non-dword aligned case */ 559 if (hsotg->core_params->dma_desc_enable <= 0 && 560 (chan->xfer_dma & 0x3)) 561 return (u8 *)urb->buf + urb->actual_length; 562 } else { 563 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 564 } 565 566 return NULL; 567 } 568 569 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 570 struct dwc2_host_chan *chan, 571 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 572 { 573 struct dwc2_hcd_iso_packet_desc *frame_desc; 574 void *bufptr = NULL; 575 576 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 577 case USB_ENDPOINT_XFER_CONTROL: 578 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 579 580 switch (qtd->control_phase) { 581 case DWC2_CONTROL_SETUP: 582 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 583 chan->do_ping = 0; 584 chan->ep_is_in = 0; 585 chan->data_pid_start = DWC2_HC_PID_SETUP; 586 if (hsotg->core_params->dma_enable > 0) 587 chan->xfer_dma = urb->setup_dma; 588 else 589 chan->xfer_buf = urb->setup_packet; 590 chan->xfer_len = 8; 591 break; 592 593 case DWC2_CONTROL_DATA: 594 dev_vdbg(hsotg->dev, " Control data transaction\n"); 595 chan->data_pid_start = qtd->data_toggle; 596 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 597 break; 598 599 case DWC2_CONTROL_STATUS: 600 /* 601 * Direction is opposite of data direction or IN if no 602 * data 603 */ 604 dev_vdbg(hsotg->dev, " Control status transaction\n"); 605 if (urb->length == 0) 606 chan->ep_is_in = 1; 607 else 608 chan->ep_is_in = 609 dwc2_hcd_is_pipe_out(&urb->pipe_info); 610 if (chan->ep_is_in) 611 chan->do_ping = 0; 612 chan->data_pid_start = DWC2_HC_PID_DATA1; 613 chan->xfer_len = 0; 614 if (hsotg->core_params->dma_enable > 0) 615 chan->xfer_dma = hsotg->status_buf_dma; 616 else 617 chan->xfer_buf = hsotg->status_buf; 618 break; 619 } 620 break; 621 622 case USB_ENDPOINT_XFER_BULK: 623 chan->ep_type = USB_ENDPOINT_XFER_BULK; 624 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 625 break; 626 627 case USB_ENDPOINT_XFER_INT: 628 chan->ep_type = USB_ENDPOINT_XFER_INT; 629 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 630 break; 631 632 case USB_ENDPOINT_XFER_ISOC: 633 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 634 if (hsotg->core_params->dma_desc_enable > 0) 635 break; 636 637 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 638 frame_desc->status = 0; 639 640 if (hsotg->core_params->dma_enable > 0) { 641 chan->xfer_dma = urb->dma; 642 chan->xfer_dma += frame_desc->offset + 643 qtd->isoc_split_offset; 644 } else { 645 chan->xfer_buf = urb->buf; 646 chan->xfer_buf += frame_desc->offset + 647 qtd->isoc_split_offset; 648 } 649 650 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 651 652 /* For non-dword aligned buffers */ 653 if (hsotg->core_params->dma_enable > 0 && 654 (chan->xfer_dma & 0x3)) 655 bufptr = (u8 *)urb->buf + frame_desc->offset + 656 qtd->isoc_split_offset; 657 658 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 659 if (chan->xfer_len <= 188) 660 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 661 else 662 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 663 } 664 break; 665 } 666 667 return bufptr; 668 } 669 670 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 671 struct dwc2_host_chan *chan, void *bufptr) 672 { 673 u32 buf_size; 674 675 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 676 buf_size = hsotg->core_params->max_transfer_size; 677 else 678 buf_size = 4096; 679 680 if (!qh->dw_align_buf) { 681 int err; 682 683 qh->dw_align_buf = NULL; 684 qh->dw_align_buf_dma = 0; 685 err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, buf_size, buf_size, 686 &qh->dw_align_buf_usbdma); 687 if (!err) { 688 usb_dma_t *ud = &qh->dw_align_buf_usbdma; 689 690 qh->dw_align_buf = KERNADDR(ud, 0); 691 qh->dw_align_buf_dma = DMAADDR(ud, 0); 692 } 693 if (!qh->dw_align_buf) 694 return -ENOMEM; 695 } 696 697 if (!chan->ep_is_in && chan->xfer_len) { 698 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 699 BUS_DMASYNC_POSTWRITE); 700 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len); 701 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 702 BUS_DMASYNC_PREWRITE); 703 } 704 705 chan->align_buf = qh->dw_align_buf_dma; 706 return 0; 707 } 708 709 /** 710 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 711 * channel and initializes the host channel to perform the transactions. The 712 * host channel is removed from the free list. 713 * 714 * @hsotg: The HCD state structure 715 * @qh: Transactions from the first QTD for this QH are selected and assigned 716 * to a free host channel 717 */ 718 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 719 { 720 struct dwc2_host_chan *chan; 721 struct dwc2_hcd_urb *urb; 722 struct dwc2_qtd *qtd; 723 void *bufptr = NULL; 724 725 if (dbg_qh(qh)) 726 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 727 728 if (list_empty(&qh->qtd_list)) { 729 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 730 return -ENOMEM; 731 } 732 733 if (list_empty(&hsotg->free_hc_list)) { 734 dev_dbg(hsotg->dev, "No free channel to assign\n"); 735 return -ENOMEM; 736 } 737 738 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 739 hc_list_entry); 740 741 /* Remove host channel from free list */ 742 list_del_init(&chan->hc_list_entry); 743 744 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 745 urb = qtd->urb; 746 qh->channel = chan; 747 qtd->in_process = 1; 748 749 /* 750 * Use usb_pipedevice to determine device address. This address is 751 * 0 before the SET_ADDRESS command and the correct address afterward. 752 */ 753 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 754 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 755 chan->speed = qh->dev_speed; 756 chan->max_packet = dwc2_max_packet(qh->maxp); 757 758 chan->xfer_started = 0; 759 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 760 chan->error_state = (qtd->error_count > 0); 761 chan->halt_on_queue = 0; 762 chan->halt_pending = 0; 763 chan->requests = 0; 764 765 /* 766 * The following values may be modified in the transfer type section 767 * below. The xfer_len value may be reduced when the transfer is 768 * started to accommodate the max widths of the XferSize and PktCnt 769 * fields in the HCTSIZn register. 770 */ 771 772 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 773 if (chan->ep_is_in) 774 chan->do_ping = 0; 775 else 776 chan->do_ping = qh->ping_state; 777 778 chan->data_pid_start = qh->data_toggle; 779 chan->multi_count = 1; 780 781 if (urb->actual_length > urb->length && 782 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 783 urb->actual_length = urb->length; 784 785 chan->xfer_len = urb->length - urb->actual_length; 786 chan->xfer_count = 0; 787 788 /* Set the split attributes if required */ 789 if (qh->do_split) 790 dwc2_hc_init_split(hsotg, chan, qtd, urb); 791 else 792 chan->do_split = 0; 793 794 /* Set the transfer attributes */ 795 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 796 797 /* Non DWORD-aligned buffer case */ 798 if (bufptr) { 799 dev_vdbg(hsotg->dev, "Non-aligned buffer%p\n", bufptr); 800 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) { 801 dev_err(hsotg->dev, 802 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 803 __func__); 804 /* Add channel back to free list */ 805 chan->align_buf = 0; 806 chan->multi_count = 0; 807 list_add_tail(&chan->hc_list_entry, 808 &hsotg->free_hc_list); 809 qtd->in_process = 0; 810 qh->channel = NULL; 811 return -ENOMEM; 812 } 813 } else { 814 chan->align_buf = 0; 815 } 816 817 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 818 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 819 /* 820 * This value may be modified when the transfer is started 821 * to reflect the actual transfer length 822 */ 823 chan->multi_count = dwc2_hb_mult(qh->maxp); 824 825 if (hsotg->core_params->dma_desc_enable > 0) 826 chan->desc_list_addr = qh->desc_list_dma; 827 828 dwc2_hc_init(hsotg, chan); 829 chan->qh = qh; 830 831 return 0; 832 } 833 834 /** 835 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 836 * schedule and assigns them to available host channels. Called from the HCD 837 * interrupt handler functions. 838 * 839 * @hsotg: The HCD state structure 840 * 841 * Return: The types of new transactions that were assigned to host channels 842 */ 843 enum dwc2_transaction_type dwc2_hcd_select_transactions( 844 struct dwc2_hsotg *hsotg) 845 { 846 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 847 struct list_head *qh_ptr; 848 struct dwc2_qh *qh; 849 int num_channels; 850 851 #ifdef DWC2_DEBUG_SOF 852 dev_vdbg(hsotg->dev, " Select Transactions\n"); 853 #endif 854 855 /* Process entries in the periodic ready list */ 856 qh_ptr = hsotg->periodic_sched_ready.next; 857 while (qh_ptr != &hsotg->periodic_sched_ready) { 858 if (list_empty(&hsotg->free_hc_list)) 859 break; 860 if (hsotg->core_params->uframe_sched > 0) { 861 if (hsotg->available_host_channels <= 1) 862 break; 863 hsotg->available_host_channels--; 864 } 865 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 866 if (dwc2_assign_and_init_hc(hsotg, qh)) 867 break; 868 869 /* 870 * Move the QH from the periodic ready schedule to the 871 * periodic assigned schedule 872 */ 873 qh_ptr = qh_ptr->next; 874 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 875 ret_val = DWC2_TRANSACTION_PERIODIC; 876 } 877 878 /* 879 * Process entries in the inactive portion of the non-periodic 880 * schedule. Some free host channels may not be used if they are 881 * reserved for periodic transfers. 882 */ 883 num_channels = hsotg->core_params->host_channels; 884 qh_ptr = hsotg->non_periodic_sched_inactive.next; 885 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 886 if (hsotg->core_params->uframe_sched <= 0 && 887 hsotg->non_periodic_channels >= num_channels - 888 hsotg->periodic_channels) 889 break; 890 if (list_empty(&hsotg->free_hc_list)) 891 break; 892 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 893 if (hsotg->core_params->uframe_sched > 0) { 894 if (hsotg->available_host_channels < 1) 895 break; 896 hsotg->available_host_channels--; 897 } 898 899 if (dwc2_assign_and_init_hc(hsotg, qh)) 900 break; 901 902 /* 903 * Move the QH from the non-periodic inactive schedule to the 904 * non-periodic active schedule 905 */ 906 qh_ptr = qh_ptr->next; 907 list_move(&qh->qh_list_entry, 908 &hsotg->non_periodic_sched_active); 909 910 if (ret_val == DWC2_TRANSACTION_NONE) 911 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 912 else 913 ret_val = DWC2_TRANSACTION_ALL; 914 915 if (hsotg->core_params->uframe_sched <= 0) 916 hsotg->non_periodic_channels++; 917 } 918 919 return ret_val; 920 } 921 922 /** 923 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 924 * a host channel associated with either a periodic or non-periodic transfer 925 * 926 * @hsotg: The HCD state structure 927 * @chan: Host channel descriptor associated with either a periodic or 928 * non-periodic transfer 929 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 930 * for periodic transfers or the non-periodic Tx FIFO 931 * for non-periodic transfers 932 * 933 * Return: 1 if a request is queued and more requests may be needed to 934 * complete the transfer, 0 if no more requests are required for this 935 * transfer, -1 if there is insufficient space in the Tx FIFO 936 * 937 * This function assumes that there is space available in the appropriate 938 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 939 * it checks whether space is available in the appropriate Tx FIFO. 940 * 941 * Must be called with interrupt disabled and spinlock held 942 */ 943 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 944 struct dwc2_host_chan *chan, 945 u16 fifo_dwords_avail) 946 { 947 int retval = 0; 948 949 if (hsotg->core_params->dma_enable > 0) { 950 if (hsotg->core_params->dma_desc_enable > 0) { 951 if (!chan->xfer_started || 952 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 953 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 954 chan->qh->ping_state = 0; 955 } 956 } else if (!chan->xfer_started) { 957 dwc2_hc_start_transfer(hsotg, chan); 958 chan->qh->ping_state = 0; 959 } 960 } else if (chan->halt_pending) { 961 /* Don't queue a request if the channel has been halted */ 962 } else if (chan->halt_on_queue) { 963 dwc2_hc_halt(hsotg, chan, chan->halt_status); 964 } else if (chan->do_ping) { 965 if (!chan->xfer_started) 966 dwc2_hc_start_transfer(hsotg, chan); 967 } else if (!chan->ep_is_in || 968 chan->data_pid_start == DWC2_HC_PID_SETUP) { 969 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 970 if (!chan->xfer_started) { 971 dwc2_hc_start_transfer(hsotg, chan); 972 retval = 1; 973 } else { 974 retval = dwc2_hc_continue_transfer(hsotg, chan); 975 } 976 } else { 977 retval = -1; 978 } 979 } else { 980 if (!chan->xfer_started) { 981 dwc2_hc_start_transfer(hsotg, chan); 982 retval = 1; 983 } else { 984 retval = dwc2_hc_continue_transfer(hsotg, chan); 985 } 986 } 987 988 return retval; 989 } 990 991 /* 992 * Processes periodic channels for the next frame and queues transactions for 993 * these channels to the DWC_otg controller. After queueing transactions, the 994 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 995 * to queue as Periodic Tx FIFO or request queue space becomes available. 996 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 997 * 998 * Must be called with interrupt disabled and spinlock held 999 */ 1000 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1001 { 1002 struct list_head *qh_ptr; 1003 struct dwc2_qh *qh; 1004 u32 tx_status; 1005 u32 fspcavail; 1006 u32 gintmsk; 1007 int status; 1008 int no_queue_space = 0; 1009 int no_fifo_space = 0; 1010 u32 qspcavail; 1011 1012 if (dbg_perio()) 1013 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1014 1015 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1016 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1017 TXSTS_QSPCAVAIL_SHIFT; 1018 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1019 TXSTS_FSPCAVAIL_SHIFT; 1020 1021 if (dbg_perio()) { 1022 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1023 qspcavail); 1024 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1025 fspcavail); 1026 } 1027 1028 qh_ptr = hsotg->periodic_sched_assigned.next; 1029 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1030 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1031 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1032 TXSTS_QSPCAVAIL_SHIFT; 1033 if (qspcavail == 0) { 1034 no_queue_space = 1; 1035 break; 1036 } 1037 1038 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1039 if (!qh->channel) { 1040 qh_ptr = qh_ptr->next; 1041 continue; 1042 } 1043 1044 /* Make sure EP's TT buffer is clean before queueing qtds */ 1045 if (qh->tt_buffer_dirty) { 1046 qh_ptr = qh_ptr->next; 1047 continue; 1048 } 1049 1050 /* 1051 * Set a flag if we're queuing high-bandwidth in slave mode. 1052 * The flag prevents any halts to get into the request queue in 1053 * the middle of multiple high-bandwidth packets getting queued. 1054 */ 1055 if (hsotg->core_params->dma_enable <= 0 && 1056 qh->channel->multi_count > 1) 1057 hsotg->queuing_high_bandwidth = 1; 1058 1059 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1060 TXSTS_FSPCAVAIL_SHIFT; 1061 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1062 if (status < 0) { 1063 no_fifo_space = 1; 1064 break; 1065 } 1066 1067 /* 1068 * In Slave mode, stay on the current transfer until there is 1069 * nothing more to do or the high-bandwidth request count is 1070 * reached. In DMA mode, only need to queue one request. The 1071 * controller automatically handles multiple packets for 1072 * high-bandwidth transfers. 1073 */ 1074 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1075 qh->channel->requests == qh->channel->multi_count) { 1076 qh_ptr = qh_ptr->next; 1077 /* 1078 * Move the QH from the periodic assigned schedule to 1079 * the periodic queued schedule 1080 */ 1081 list_move(&qh->qh_list_entry, 1082 &hsotg->periodic_sched_queued); 1083 1084 /* done queuing high bandwidth */ 1085 hsotg->queuing_high_bandwidth = 0; 1086 } 1087 } 1088 1089 if (hsotg->core_params->dma_enable <= 0) { 1090 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1091 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1092 TXSTS_QSPCAVAIL_SHIFT; 1093 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1094 TXSTS_FSPCAVAIL_SHIFT; 1095 if (dbg_perio()) { 1096 dev_vdbg(hsotg->dev, 1097 " P Tx Req Queue Space Avail (after queue): %d\n", 1098 qspcavail); 1099 dev_vdbg(hsotg->dev, 1100 " P Tx FIFO Space Avail (after queue): %d\n", 1101 fspcavail); 1102 } 1103 1104 if (!list_empty(&hsotg->periodic_sched_assigned) || 1105 no_queue_space || no_fifo_space) { 1106 /* 1107 * May need to queue more transactions as the request 1108 * queue or Tx FIFO empties. Enable the periodic Tx 1109 * FIFO empty interrupt. (Always use the half-empty 1110 * level to ensure that new requests are loaded as 1111 * soon as possible.) 1112 */ 1113 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1114 gintmsk |= GINTSTS_PTXFEMP; 1115 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1116 } else { 1117 /* 1118 * Disable the Tx FIFO empty interrupt since there are 1119 * no more transactions that need to be queued right 1120 * now. This function is called from interrupt 1121 * handlers to queue more transactions as transfer 1122 * states change. 1123 */ 1124 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1125 gintmsk &= ~GINTSTS_PTXFEMP; 1126 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1127 } 1128 } 1129 } 1130 1131 /* 1132 * Processes active non-periodic channels and queues transactions for these 1133 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1134 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1135 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1136 * FIFO Empty interrupt is disabled. 1137 * 1138 * Must be called with interrupt disabled and spinlock held 1139 */ 1140 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1141 { 1142 struct list_head *orig_qh_ptr; 1143 struct dwc2_qh *qh; 1144 u32 tx_status; 1145 u32 qspcavail; 1146 u32 fspcavail; 1147 u32 gintmsk; 1148 int status; 1149 int no_queue_space = 0; 1150 int no_fifo_space = 0; 1151 int more_to_do = 0; 1152 1153 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1154 1155 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1156 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1157 TXSTS_QSPCAVAIL_SHIFT; 1158 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1159 TXSTS_FSPCAVAIL_SHIFT; 1160 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1161 qspcavail); 1162 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1163 fspcavail); 1164 1165 /* 1166 * Keep track of the starting point. Skip over the start-of-list 1167 * entry. 1168 */ 1169 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1170 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1171 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1172 1173 /* 1174 * Process once through the active list or until no more space is 1175 * available in the request queue or the Tx FIFO 1176 */ 1177 do { 1178 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1179 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1180 TXSTS_QSPCAVAIL_SHIFT; 1181 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1182 no_queue_space = 1; 1183 break; 1184 } 1185 1186 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1187 qh_list_entry); 1188 if (!qh->channel) 1189 goto next; 1190 1191 /* Make sure EP's TT buffer is clean before queueing qtds */ 1192 if (qh->tt_buffer_dirty) 1193 goto next; 1194 1195 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1196 TXSTS_FSPCAVAIL_SHIFT; 1197 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1198 1199 if (status > 0) { 1200 more_to_do = 1; 1201 } else if (status < 0) { 1202 no_fifo_space = 1; 1203 break; 1204 } 1205 next: 1206 /* Advance to next QH, skipping start-of-list entry */ 1207 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1208 if (hsotg->non_periodic_qh_ptr == 1209 &hsotg->non_periodic_sched_active) 1210 hsotg->non_periodic_qh_ptr = 1211 hsotg->non_periodic_qh_ptr->next; 1212 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1213 1214 if (hsotg->core_params->dma_enable <= 0) { 1215 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1216 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1217 TXSTS_QSPCAVAIL_SHIFT; 1218 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1219 TXSTS_FSPCAVAIL_SHIFT; 1220 dev_vdbg(hsotg->dev, 1221 " NP Tx Req Queue Space Avail (after queue): %d\n", 1222 qspcavail); 1223 dev_vdbg(hsotg->dev, 1224 " NP Tx FIFO Space Avail (after queue): %d\n", 1225 fspcavail); 1226 1227 if (more_to_do || no_queue_space || no_fifo_space) { 1228 /* 1229 * May need to queue more transactions as the request 1230 * queue or Tx FIFO empties. Enable the non-periodic 1231 * Tx FIFO empty interrupt. (Always use the half-empty 1232 * level to ensure that new requests are loaded as 1233 * soon as possible.) 1234 */ 1235 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1236 gintmsk |= GINTSTS_NPTXFEMP; 1237 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1238 } else { 1239 /* 1240 * Disable the Tx FIFO empty interrupt since there are 1241 * no more transactions that need to be queued right 1242 * now. This function is called from interrupt 1243 * handlers to queue more transactions as transfer 1244 * states change. 1245 */ 1246 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1247 gintmsk &= ~GINTSTS_NPTXFEMP; 1248 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1249 } 1250 } 1251 } 1252 1253 /** 1254 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1255 * and queues transactions for these channels to the DWC_otg controller. Called 1256 * from the HCD interrupt handler functions. 1257 * 1258 * @hsotg: The HCD state structure 1259 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1260 * or both) 1261 * 1262 * Must be called with interrupt disabled and spinlock held 1263 */ 1264 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1265 enum dwc2_transaction_type tr_type) 1266 { 1267 #ifdef DWC2_DEBUG_SOF 1268 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1269 #endif 1270 /* Process host channels associated with periodic transfers */ 1271 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1272 tr_type == DWC2_TRANSACTION_ALL) && 1273 !list_empty(&hsotg->periodic_sched_assigned)) 1274 dwc2_process_periodic_channels(hsotg); 1275 1276 /* Process host channels associated with non-periodic transfers */ 1277 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1278 tr_type == DWC2_TRANSACTION_ALL) { 1279 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1280 dwc2_process_non_periodic_channels(hsotg); 1281 } else { 1282 /* 1283 * Ensure NP Tx FIFO empty interrupt is disabled when 1284 * there are no non-periodic transfers to process 1285 */ 1286 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1287 1288 gintmsk &= ~GINTSTS_NPTXFEMP; 1289 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1290 } 1291 } 1292 } 1293 1294 void 1295 dwc2_conn_id_status_change(struct work *work) 1296 { 1297 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1298 wf_otg); 1299 u32 count = 0; 1300 u32 gotgctl; 1301 1302 dev_dbg(hsotg->dev, "%s()\n", __func__); 1303 1304 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1305 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1306 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1307 !!(gotgctl & GOTGCTL_CONID_B)); 1308 1309 /* B-Device connector (Device Mode) */ 1310 if (gotgctl & GOTGCTL_CONID_B) { 1311 /* Wait for switch to device mode */ 1312 dev_dbg(hsotg->dev, "connId B\n"); 1313 while (!dwc2_is_device_mode(hsotg)) { 1314 dev_info(hsotg->dev, 1315 "Waiting for Peripheral Mode, Mode=%s\n", 1316 dwc2_is_host_mode(hsotg) ? "Host" : 1317 "Peripheral"); 1318 usleep_range(20000, 40000); 1319 if (++count > 250) 1320 break; 1321 } 1322 if (count > 250) 1323 dev_err(hsotg->dev, 1324 "Connection id status change timed out\n"); 1325 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1326 dwc2_core_init(hsotg, false); 1327 dwc2_enable_global_interrupts(hsotg); 1328 } else { 1329 /* A-Device connector (Host Mode) */ 1330 dev_dbg(hsotg->dev, "connId A\n"); 1331 while (!dwc2_is_host_mode(hsotg)) { 1332 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1333 dwc2_is_host_mode(hsotg) ? 1334 "Host" : "Peripheral"); 1335 usleep_range(20000, 40000); 1336 if (++count > 250) 1337 break; 1338 } 1339 if (count > 250) 1340 dev_err(hsotg->dev, 1341 "Connection id status change timed out\n"); 1342 hsotg->op_state = OTG_STATE_A_HOST; 1343 1344 /* Initialize the Core for Host mode */ 1345 dwc2_core_init(hsotg, false); 1346 dwc2_enable_global_interrupts(hsotg); 1347 dwc2_hcd_start(hsotg); 1348 } 1349 } 1350 1351 void dwc2_wakeup_detected(void * data) 1352 { 1353 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1354 u32 hprt0; 1355 1356 dev_dbg(hsotg->dev, "%s()\n", __func__); 1357 1358 /* 1359 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1360 * so that OPT tests pass with all PHYs.) 1361 */ 1362 hprt0 = dwc2_read_hprt0(hsotg); 1363 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1364 hprt0 &= ~HPRT0_RES; 1365 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1366 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1367 DWC2_READ_4(hsotg, HPRT0)); 1368 1369 dwc2_hcd_rem_wakeup(hsotg); 1370 1371 /* Change to L0 state */ 1372 hsotg->lx_state = DWC2_L0; 1373 } 1374 1375 /* Must NOT be called with interrupt disabled or spinlock held */ 1376 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1377 { 1378 unsigned long flags; 1379 u32 hprt0; 1380 u32 pcgctl; 1381 u32 gotgctl; 1382 1383 dev_dbg(hsotg->dev, "%s()\n", __func__); 1384 1385 spin_lock_irqsave(&hsotg->lock, flags); 1386 1387 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1388 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1389 gotgctl |= GOTGCTL_HSTSETHNPEN; 1390 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1391 hsotg->op_state = OTG_STATE_A_SUSPEND; 1392 } 1393 1394 hprt0 = dwc2_read_hprt0(hsotg); 1395 hprt0 |= HPRT0_SUSP; 1396 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1397 1398 /* Update lx_state */ 1399 hsotg->lx_state = DWC2_L2; 1400 1401 /* Suspend the Phy Clock */ 1402 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1403 pcgctl |= PCGCTL_STOPPCLK; 1404 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1405 udelay(10); 1406 1407 /* For HNP the bus must be suspended for at least 200ms */ 1408 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1409 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1410 pcgctl &= ~PCGCTL_STOPPCLK; 1411 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1412 1413 spin_unlock_irqrestore(&hsotg->lock, flags); 1414 1415 usleep_range(200000, 250000); 1416 } else { 1417 spin_unlock_irqrestore(&hsotg->lock, flags); 1418 } 1419 } 1420 1421 /* Handles hub class-specific requests */ 1422 int 1423 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1424 u16 wvalue, u16 windex, char *buf, u16 wlength) 1425 { 1426 usb_hub_descriptor_t *hub_desc; 1427 usb_port_status_t ps; 1428 int retval = 0; 1429 u32 hprt0; 1430 u32 port_status; 1431 u32 speed; 1432 u32 pcgctl; 1433 1434 switch (typereq) { 1435 case ClearHubFeature: 1436 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1437 1438 switch (wvalue) { 1439 case C_HUB_LOCAL_POWER: 1440 case C_HUB_OVER_CURRENT: 1441 /* Nothing required here */ 1442 break; 1443 1444 default: 1445 retval = -EINVAL; 1446 dev_err(hsotg->dev, 1447 "ClearHubFeature request %1xh unknown\n", 1448 wvalue); 1449 } 1450 break; 1451 1452 case ClearPortFeature: 1453 // if (wvalue != USB_PORT_FEAT_L1) 1454 if (!windex || windex > 1) 1455 goto error; 1456 switch (wvalue) { 1457 case USB_PORT_FEAT_ENABLE: 1458 dev_dbg(hsotg->dev, 1459 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1460 hprt0 = dwc2_read_hprt0(hsotg); 1461 hprt0 |= HPRT0_ENA; 1462 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1463 break; 1464 1465 case USB_PORT_FEAT_SUSPEND: 1466 dev_dbg(hsotg->dev, 1467 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1468 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1469 usleep_range(20000, 40000); 1470 1471 hprt0 = dwc2_read_hprt0(hsotg); 1472 hprt0 |= HPRT0_RES; 1473 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1474 hprt0 &= ~HPRT0_SUSP; 1475 usleep_range(100000, 150000); 1476 1477 hprt0 &= ~HPRT0_RES; 1478 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1479 break; 1480 1481 case USB_PORT_FEAT_POWER: 1482 dev_dbg(hsotg->dev, 1483 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1484 hprt0 = dwc2_read_hprt0(hsotg); 1485 hprt0 &= ~HPRT0_PWR; 1486 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1487 break; 1488 1489 case USB_PORT_FEAT_INDICATOR: 1490 dev_dbg(hsotg->dev, 1491 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1492 /* Port indicator not supported */ 1493 break; 1494 1495 case USB_PORT_FEAT_C_CONNECTION: 1496 /* 1497 * Clears driver's internal Connect Status Change flag 1498 */ 1499 dev_dbg(hsotg->dev, 1500 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1501 hsotg->flags.b.port_connect_status_change = 0; 1502 break; 1503 1504 case USB_PORT_FEAT_C_RESET: 1505 /* Clears driver's internal Port Reset Change flag */ 1506 dev_dbg(hsotg->dev, 1507 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1508 hsotg->flags.b.port_reset_change = 0; 1509 break; 1510 1511 case USB_PORT_FEAT_C_ENABLE: 1512 /* 1513 * Clears the driver's internal Port Enable/Disable 1514 * Change flag 1515 */ 1516 dev_dbg(hsotg->dev, 1517 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1518 hsotg->flags.b.port_enable_change = 0; 1519 break; 1520 1521 case USB_PORT_FEAT_C_SUSPEND: 1522 /* 1523 * Clears the driver's internal Port Suspend Change 1524 * flag, which is set when resume signaling on the host 1525 * port is complete 1526 */ 1527 dev_dbg(hsotg->dev, 1528 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1529 hsotg->flags.b.port_suspend_change = 0; 1530 break; 1531 1532 case USB_PORT_FEAT_C_PORT_L1: 1533 dev_dbg(hsotg->dev, 1534 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1535 hsotg->flags.b.port_l1_change = 0; 1536 break; 1537 1538 case USB_PORT_FEAT_C_OVER_CURRENT: 1539 dev_dbg(hsotg->dev, 1540 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1541 hsotg->flags.b.port_over_current_change = 0; 1542 break; 1543 1544 default: 1545 retval = -EINVAL; 1546 dev_err(hsotg->dev, 1547 "ClearPortFeature request %1xh unknown or unsupported\n", 1548 wvalue); 1549 } 1550 break; 1551 1552 case GetHubDescriptor: 1553 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1554 hub_desc = (usb_hub_descriptor_t *)buf; 1555 hub_desc->bDescLength = 9; 1556 hub_desc->bDescriptorType = 0x29; 1557 hub_desc->bNbrPorts = 1; 1558 USETW(hub_desc->wHubCharacteristics, 0x08); 1559 hub_desc->bPwrOn2PwrGood = 1; 1560 hub_desc->bHubContrCurrent = 0; 1561 hub_desc->DeviceRemovable[0] = 0; 1562 hub_desc->DeviceRemovable[1] = 0xff; 1563 break; 1564 1565 case GetHubStatus: 1566 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1567 memset(buf, 0, 4); 1568 break; 1569 1570 case GetPortStatus: 1571 dev_vdbg(hsotg->dev, 1572 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1573 hsotg->flags.d32); 1574 if (!windex || windex > 1) 1575 goto error; 1576 1577 port_status = 0; 1578 if (hsotg->flags.b.port_connect_status_change) 1579 port_status |= USB_PORT_STAT_C_CONNECTION; 1580 if (hsotg->flags.b.port_enable_change) 1581 port_status |= USB_PORT_STAT_C_ENABLE; 1582 if (hsotg->flags.b.port_suspend_change) 1583 port_status |= USB_PORT_STAT_C_SUSPEND; 1584 if (hsotg->flags.b.port_l1_change) 1585 port_status |= USB_PORT_STAT_C_L1; 1586 if (hsotg->flags.b.port_reset_change) 1587 port_status |= USB_PORT_STAT_C_RESET; 1588 if (hsotg->flags.b.port_over_current_change) { 1589 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1590 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1591 } 1592 USETW(ps.wPortChange, port_status); 1593 1594 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1595 if (!hsotg->flags.b.port_connect_status) { 1596 /* 1597 * The port is disconnected, which means the core is 1598 * either in device mode or it soon will be. Just 1599 * return 0's for the remainder of the port status 1600 * since the port register can't be read if the core 1601 * is in device mode. 1602 */ 1603 USETW(ps.wPortStatus, 0); 1604 memcpy(buf, &ps, sizeof(ps)); 1605 break; 1606 } 1607 1608 port_status = 0; 1609 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1610 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1611 1612 if (hprt0 & HPRT0_CONNSTS) 1613 port_status |= USB_PORT_STAT_CONNECTION; 1614 if (hprt0 & HPRT0_ENA) 1615 port_status |= USB_PORT_STAT_ENABLE; 1616 if (hprt0 & HPRT0_SUSP) 1617 port_status |= USB_PORT_STAT_SUSPEND; 1618 if (hprt0 & HPRT0_OVRCURRACT) 1619 port_status |= USB_PORT_STAT_OVERCURRENT; 1620 if (hprt0 & HPRT0_RST) 1621 port_status |= USB_PORT_STAT_RESET; 1622 if (hprt0 & HPRT0_PWR) 1623 port_status |= USB_PORT_STAT_POWER; 1624 1625 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1626 if (speed == HPRT0_SPD_HIGH_SPEED) 1627 port_status |= USB_PORT_STAT_HIGH_SPEED; 1628 else if (speed == HPRT0_SPD_LOW_SPEED) 1629 port_status |= USB_PORT_STAT_LOW_SPEED; 1630 1631 if (hprt0 & HPRT0_TSTCTL_MASK) 1632 port_status |= USB_PORT_STAT_TEST; 1633 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1634 USETW(ps.wPortStatus, port_status); 1635 1636 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1637 memcpy(buf, &ps, sizeof(ps)); 1638 break; 1639 1640 case SetHubFeature: 1641 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1642 /* No HUB features supported */ 1643 break; 1644 1645 case SetPortFeature: 1646 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1647 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1648 goto error; 1649 1650 if (!hsotg->flags.b.port_connect_status) { 1651 /* 1652 * The port is disconnected, which means the core is 1653 * either in device mode or it soon will be. Just 1654 * return without doing anything since the port 1655 * register can't be written if the core is in device 1656 * mode. 1657 */ 1658 break; 1659 } 1660 1661 switch (wvalue) { 1662 case USB_PORT_FEAT_SUSPEND: 1663 dev_dbg(hsotg->dev, 1664 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1665 if (windex != hsotg->otg_port) 1666 goto error; 1667 dwc2_port_suspend(hsotg, windex); 1668 break; 1669 1670 case USB_PORT_FEAT_POWER: 1671 dev_dbg(hsotg->dev, 1672 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1673 hprt0 = dwc2_read_hprt0(hsotg); 1674 hprt0 |= HPRT0_PWR; 1675 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1676 break; 1677 1678 case USB_PORT_FEAT_RESET: 1679 hprt0 = dwc2_read_hprt0(hsotg); 1680 dev_dbg(hsotg->dev, 1681 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1682 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1683 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1684 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1685 /* ??? Original driver does this */ 1686 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1687 1688 hprt0 = dwc2_read_hprt0(hsotg); 1689 /* Clear suspend bit if resetting from suspend state */ 1690 hprt0 &= ~HPRT0_SUSP; 1691 1692 /* 1693 * When B-Host the Port reset bit is set in the Start 1694 * HCD Callback function, so that the reset is started 1695 * within 1ms of the HNP success interrupt 1696 */ 1697 if (!dwc2_hcd_is_b_host(hsotg)) { 1698 hprt0 |= HPRT0_PWR | HPRT0_RST; 1699 dev_dbg(hsotg->dev, 1700 "In host mode, hprt0=%08x\n", hprt0); 1701 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1702 } 1703 1704 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1705 usleep_range(50000, 70000); 1706 hprt0 &= ~HPRT0_RST; 1707 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1708 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1709 break; 1710 1711 case USB_PORT_FEAT_INDICATOR: 1712 dev_dbg(hsotg->dev, 1713 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1714 /* Not supported */ 1715 break; 1716 1717 default: 1718 retval = -EINVAL; 1719 dev_err(hsotg->dev, 1720 "SetPortFeature %1xh unknown or unsupported\n", 1721 wvalue); 1722 break; 1723 } 1724 break; 1725 1726 default: 1727 error: 1728 retval = -EINVAL; 1729 dev_dbg(hsotg->dev, 1730 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1731 typereq, windex, wvalue); 1732 break; 1733 } 1734 1735 return retval; 1736 } 1737 1738 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1739 { 1740 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1741 1742 #ifdef DWC2_DEBUG_SOF 1743 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1744 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1745 #endif 1746 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1747 } 1748 1749 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1750 { 1751 return (hsotg->op_state == OTG_STATE_B_HOST); 1752 } 1753 1754 struct dwc2_hcd_urb * 1755 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1756 gfp_t mem_flags) 1757 { 1758 struct dwc2_hcd_urb *urb; 1759 u32 size = sizeof(*urb) + iso_desc_count * 1760 sizeof(struct dwc2_hcd_iso_packet_desc); 1761 1762 urb = kmem_zalloc(size, mem_flags); 1763 if (urb) 1764 urb->packet_count = iso_desc_count; 1765 return urb; 1766 } 1767 1768 void 1769 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1770 int iso_desc_count) 1771 { 1772 1773 u32 size = sizeof(*urb) + iso_desc_count * 1774 sizeof(struct dwc2_hcd_iso_packet_desc); 1775 1776 kmem_free(urb, size); 1777 } 1778 1779 void 1780 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1781 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1782 u16 mps) 1783 { 1784 if (dbg_perio() || 1785 ep_type == USB_ENDPOINT_XFER_BULK || 1786 ep_type == USB_ENDPOINT_XFER_CONTROL) 1787 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1788 urb->pipe_info.dev_addr = dev_addr; 1789 urb->pipe_info.ep_num = ep_num; 1790 urb->pipe_info.pipe_type = ep_type; 1791 urb->pipe_info.pipe_dir = ep_dir; 1792 urb->pipe_info.mps = mps; 1793 } 1794 1795 /* 1796 * NOTE: This function will be removed once the peripheral controller code 1797 * is integrated and the driver is stable 1798 */ 1799 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1800 { 1801 #ifdef DEBUG 1802 struct dwc2_host_chan *chan; 1803 struct dwc2_hcd_urb *urb; 1804 struct dwc2_qtd *qtd; 1805 int num_channels; 1806 u32 np_tx_status; 1807 u32 p_tx_status; 1808 int i; 1809 1810 num_channels = hsotg->core_params->host_channels; 1811 dev_dbg(hsotg->dev, "\n"); 1812 dev_dbg(hsotg->dev, 1813 "************************************************************\n"); 1814 dev_dbg(hsotg->dev, "HCD State:\n"); 1815 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1816 1817 for (i = 0; i < num_channels; i++) { 1818 chan = hsotg->hc_ptr_array[i]; 1819 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1820 dev_dbg(hsotg->dev, 1821 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1822 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1823 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1824 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1825 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1826 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1827 chan->data_pid_start); 1828 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1829 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1830 chan->xfer_started); 1831 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1832 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1833 (unsigned long)chan->xfer_dma); 1834 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1835 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1836 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1837 chan->halt_on_queue); 1838 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1839 chan->halt_pending); 1840 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1841 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1842 dev_dbg(hsotg->dev, " complete_split: %d\n", 1843 chan->complete_split); 1844 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1845 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1846 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1847 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1848 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1849 1850 if (chan->xfer_started) { 1851 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1852 1853 hfnum = DWC2_READ_4(hsotg, HFNUM); 1854 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 1855 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(i)); 1856 hcint = DWC2_READ_4(hsotg, HCINT(i)); 1857 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(i)); 1858 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1859 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1860 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1861 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1862 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1863 } 1864 1865 if (!(chan->xfer_started && chan->qh)) 1866 continue; 1867 1868 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1869 if (!qtd->in_process) 1870 break; 1871 urb = qtd->urb; 1872 dev_dbg(hsotg->dev, " URB Info:\n"); 1873 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1874 qtd, urb); 1875 if (urb) { 1876 dev_dbg(hsotg->dev, 1877 " Dev: %d, EP: %d %s\n", 1878 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1879 dwc2_hcd_get_ep_num(&urb->pipe_info), 1880 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1881 "IN" : "OUT"); 1882 dev_dbg(hsotg->dev, 1883 " Max packet size: %d\n", 1884 dwc2_hcd_get_mps(&urb->pipe_info)); 1885 dev_dbg(hsotg->dev, 1886 " transfer_buffer: %p\n", 1887 urb->buf); 1888 dev_dbg(hsotg->dev, 1889 " transfer_dma: %08lx\n", 1890 (unsigned long)urb->dma); 1891 dev_dbg(hsotg->dev, 1892 " transfer_buffer_length: %d\n", 1893 urb->length); 1894 dev_dbg(hsotg->dev, " actual_length: %d\n", 1895 urb->actual_length); 1896 } 1897 } 1898 } 1899 1900 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1901 hsotg->non_periodic_channels); 1902 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1903 hsotg->periodic_channels); 1904 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1905 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1906 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1907 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1908 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1909 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1910 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1911 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1912 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1913 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1914 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1915 dwc2_hcd_dump_frrem(hsotg); 1916 1917 dwc2_dump_global_registers(hsotg); 1918 dwc2_dump_host_registers(hsotg); 1919 dev_dbg(hsotg->dev, 1920 "************************************************************\n"); 1921 dev_dbg(hsotg->dev, "\n"); 1922 #endif 1923 } 1924 1925 /* 1926 * NOTE: This function will be removed once the peripheral controller code 1927 * is integrated and the driver is stable 1928 */ 1929 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 1930 { 1931 #ifdef DWC2_DUMP_FRREM 1932 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 1933 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1934 hsotg->frrem_samples, hsotg->frrem_accum, 1935 hsotg->frrem_samples > 0 ? 1936 hsotg->frrem_accum / hsotg->frrem_samples : 0); 1937 dev_dbg(hsotg->dev, "\n"); 1938 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 1939 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1940 hsotg->hfnum_7_samples, 1941 hsotg->hfnum_7_frrem_accum, 1942 hsotg->hfnum_7_samples > 0 ? 1943 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 1944 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 1945 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1946 hsotg->hfnum_0_samples, 1947 hsotg->hfnum_0_frrem_accum, 1948 hsotg->hfnum_0_samples > 0 ? 1949 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 1950 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 1951 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1952 hsotg->hfnum_other_samples, 1953 hsotg->hfnum_other_frrem_accum, 1954 hsotg->hfnum_other_samples > 0 ? 1955 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 1956 0); 1957 dev_dbg(hsotg->dev, "\n"); 1958 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 1959 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1960 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 1961 hsotg->hfnum_7_samples_a > 0 ? 1962 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 1963 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 1964 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1965 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 1966 hsotg->hfnum_0_samples_a > 0 ? 1967 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 1968 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 1969 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1970 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 1971 hsotg->hfnum_other_samples_a > 0 ? 1972 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 1973 : 0); 1974 dev_dbg(hsotg->dev, "\n"); 1975 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 1976 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1977 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 1978 hsotg->hfnum_7_samples_b > 0 ? 1979 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 1980 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 1981 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1982 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 1983 (hsotg->hfnum_0_samples_b > 0) ? 1984 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 1985 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 1986 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1987 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 1988 (hsotg->hfnum_other_samples_b > 0) ? 1989 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 1990 : 0); 1991 #endif 1992 } 1993 1994 struct wrapper_priv_data { 1995 struct dwc2_hsotg *hsotg; 1996 }; 1997 1998 1999 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2000 { 2001 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2002 2003 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2004 _dwc2_hcd_start(hsotg); 2005 } 2006 2007 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2008 { 2009 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2010 2011 // hcd->self.is_b_host = 0; 2012 } 2013 2014 2015 /* 2016 * Work queue function for starting the HCD when A-Cable is connected 2017 */ 2018 void 2019 dwc2_hcd_start_func(struct work *work) 2020 { 2021 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2022 start_work.work); 2023 2024 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2025 dwc2_host_start(hsotg); 2026 } 2027 2028 /* 2029 * Reset work queue function 2030 */ 2031 void 2032 dwc2_hcd_reset_func(struct work *work) 2033 { 2034 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2035 reset_work.work); 2036 u32 hprt0; 2037 2038 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2039 hprt0 = dwc2_read_hprt0(hsotg); 2040 hprt0 &= ~HPRT0_RST; 2041 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2042 hsotg->flags.b.port_reset_change = 1; 2043 2044 dwc2_root_intr(hsotg->hsotg_sc); 2045 } 2046 2047 /* 2048 * ========================================================================= 2049 * Linux HC Driver Functions 2050 * ========================================================================= 2051 */ 2052 2053 /* 2054 * Initializes the DWC_otg controller and its root hub and prepares it for host 2055 * mode operation. Activates the root port. Returns 0 on success and a negative 2056 * error code on failure. 2057 */ 2058 2059 2060 /* 2061 * Frees secondary storage associated with the dwc2_hsotg structure contained 2062 * in the struct usb_hcd field 2063 */ 2064 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2065 { 2066 u32 ahbcfg; 2067 u32 dctl; 2068 int i; 2069 2070 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2071 2072 /* Free memory for QH/QTD lists */ 2073 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2074 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2075 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2076 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2077 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2078 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2079 2080 /* Free memory for the host channels */ 2081 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2082 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2083 2084 if (chan != NULL) { 2085 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2086 i, chan); 2087 hsotg->hc_ptr_array[i] = NULL; 2088 kmem_free(chan, sizeof(*chan)); 2089 } 2090 } 2091 2092 if (hsotg->core_params->dma_enable > 0) { 2093 if (hsotg->status_buf) { 2094 usb_freemem(&hsotg->hsotg_sc->sc_bus, 2095 &hsotg->status_buf_usbdma); 2096 hsotg->status_buf = NULL; 2097 } 2098 } else { 2099 kmem_free(hsotg->status_buf,DWC2_HCD_STATUS_BUF_SIZE); 2100 hsotg->status_buf = NULL; 2101 } 2102 2103 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2104 2105 /* Disable all interrupts */ 2106 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2107 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2108 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2109 2110 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2111 dctl = DWC2_READ_4(hsotg, DCTL); 2112 dctl |= DCTL_SFTDISCON; 2113 DWC2_WRITE_4(hsotg, DCTL, dctl); 2114 } 2115 2116 if (hsotg->wq_otg) { 2117 workqueue_destroy(hsotg->wq_otg); 2118 } 2119 2120 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2121 hsotg->core_params = NULL; 2122 callout_destroy(&hsotg->wkp_timer); 2123 } 2124 2125 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2126 { 2127 /* Turn off all host-specific interrupts */ 2128 dwc2_disable_host_interrupts(hsotg); 2129 2130 dwc2_hcd_free(hsotg); 2131 } 2132 2133 /* 2134 * Sets all parameters to the given value. 2135 * 2136 * Assumes that the dwc2_core_params struct contains only integers. 2137 */ 2138 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2139 { 2140 int *p = (int *)params; 2141 size_t size = sizeof(*params) / sizeof(*p); 2142 int i; 2143 2144 for (i = 0; i < size; i++) 2145 p[i] = value; 2146 } 2147 2148 /* 2149 * Initializes the HCD. This function allocates memory for and initializes the 2150 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2151 * USB bus with the core and calls the hc_driver->start() function. It returns 2152 * a negative error on failure. 2153 */ 2154 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, 2155 const struct dwc2_core_params *params) 2156 { 2157 struct dwc2_host_chan *channel; 2158 u32 hcfg; 2159 int i, num_channels; 2160 int err, retval; 2161 2162 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2163 2164 /* Detect config values from hardware */ 2165 retval = dwc2_get_hwparams(hsotg); 2166 2167 if (retval) 2168 return retval; 2169 2170 retval = -ENOMEM; 2171 2172 hcfg = DWC2_READ_4(hsotg, HCFG); 2173 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 2174 2175 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2176 hsotg->frame_num_array = kmem_zalloc(sizeof(*hsotg->frame_num_array) * 2177 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2178 if (!hsotg->frame_num_array) 2179 goto error1; 2180 hsotg->last_frame_num_array = kmem_zalloc( 2181 sizeof(*hsotg->last_frame_num_array) * 2182 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2183 if (!hsotg->last_frame_num_array) 2184 goto error1; 2185 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2186 #endif 2187 2188 hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP); 2189 if (!hsotg->core_params) 2190 goto error1; 2191 2192 dwc2_set_all_params(hsotg->core_params, -1); 2193 2194 /* Validate parameter values */ 2195 dwc2_set_parameters(hsotg, params); 2196 2197 spin_lock_init(&hsotg->lock); 2198 2199 /* 2200 * Disable the global interrupt until all the interrupt handlers are 2201 * installed 2202 */ 2203 dwc2_disable_global_interrupts(hsotg); 2204 2205 /* Initialize the DWC_otg core, and select the Phy type */ 2206 retval = dwc2_core_init(hsotg, true); 2207 if (retval) 2208 goto error2; 2209 2210 /* Create new workqueue and init work */ 2211 retval = -ENOMEM; 2212 err = workqueue_create(&hsotg->wq_otg, "dwc2", dwc2_worker, hsotg, 2213 PRI_BIO, IPL_USB, WQ_MPSAFE); 2214 2215 retval = -err; 2216 if (err) { 2217 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2218 goto error2; 2219 } 2220 2221 callout_init(&hsotg->wkp_timer, CALLOUT_MPSAFE); 2222 callout_setfunc(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2223 2224 /* Initialize the non-periodic schedule */ 2225 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2226 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2227 2228 /* Initialize the periodic schedule */ 2229 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2230 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2231 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2232 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2233 2234 /* 2235 * Create a host channel descriptor for each host channel implemented 2236 * in the controller. Initialize the channel descriptor array. 2237 */ 2238 INIT_LIST_HEAD(&hsotg->free_hc_list); 2239 num_channels = hsotg->core_params->host_channels; 2240 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2241 2242 for (i = 0; i < num_channels; i++) { 2243 channel = kmem_zalloc(sizeof(*channel), KM_SLEEP); 2244 if (channel == NULL) 2245 goto error3; 2246 channel->hc_num = i; 2247 hsotg->hc_ptr_array[i] = channel; 2248 } 2249 2250 if (hsotg->core_params->uframe_sched > 0) 2251 dwc2_hcd_init_usecs(hsotg); 2252 2253 /* Initialize hsotg start work */ 2254 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2255 2256 /* Initialize port reset work */ 2257 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2258 2259 /* 2260 * Allocate space for storing data on status transactions. Normally no 2261 * data is sent, but this space acts as a bit bucket. This must be 2262 * done after usb_add_hcd since that function allocates the DMA buffer 2263 * pool. 2264 */ 2265 hsotg->status_buf = NULL; 2266 if (hsotg->core_params->dma_enable > 0) { 2267 retval = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 2268 DWC2_HCD_STATUS_BUF_SIZE, 0, 2269 &hsotg->status_buf_usbdma); 2270 if (!retval) { 2271 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2272 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2273 } 2274 } else 2275 hsotg->status_buf = kmem_zalloc(DWC2_HCD_STATUS_BUF_SIZE, 2276 KM_SLEEP); 2277 2278 if (!hsotg->status_buf) 2279 goto error3; 2280 2281 hsotg->otg_port = 1; 2282 hsotg->frame_list = NULL; 2283 hsotg->frame_list_dma = 0; 2284 hsotg->periodic_qh_count = 0; 2285 2286 /* Initiate lx_state to L3 disconnected state */ 2287 hsotg->lx_state = DWC2_L3; 2288 2289 _dwc2_hcd_start(hsotg); 2290 2291 dwc2_hcd_dump_state(hsotg); 2292 2293 dwc2_enable_global_interrupts(hsotg); 2294 2295 return 0; 2296 2297 error3: 2298 dwc2_hcd_release(hsotg); 2299 error2: 2300 error1: 2301 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2302 2303 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2304 kmem_free(hsotg->last_frame_num_array, 2305 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2306 kmem_free(hsotg->frame_num_array, 2307 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2308 #endif 2309 2310 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2311 return retval; 2312 } 2313