1 /* $NetBSD: dwc2_hcd.c,v 1.12 2014/04/03 06:34:58 skrll Exp $ */ 2 3 /* 4 * hcd.c - DesignWare HS OTG Controller host-mode routines 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the core HCD code, and implements the Linux hc_driver 41 * API 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.12 2014/04/03 06:34:58 skrll Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/pool.h> 51 #include <sys/workqueue.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <linux/kernel.h> 59 #include <linux/list.h> 60 61 #include <dwc2/dwc2.h> 62 #include <dwc2/dwc2var.h> 63 64 #include "dwc2_core.h" 65 #include "dwc2_hcd.h" 66 67 /** 68 * dwc2_dump_channel_info() - Prints the state of a host channel 69 * 70 * @hsotg: Programming view of DWC_otg controller 71 * @chan: Pointer to the channel to dump 72 * 73 * Must be called with interrupt disabled and spinlock held 74 * 75 * NOTE: This function will be removed once the peripheral controller code 76 * is integrated and the driver is stable 77 */ 78 #ifdef VERBOSE_DEBUG 79 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 80 struct dwc2_host_chan *chan) 81 { 82 int num_channels = hsotg->core_params->host_channels; 83 struct dwc2_qh *qh; 84 u32 hcchar; 85 u32 hcsplt; 86 u32 hctsiz; 87 u32 hc_dma; 88 int i; 89 90 if (chan == NULL) 91 return; 92 93 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 94 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 95 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 96 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 97 98 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 99 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 100 hcchar, hcsplt); 101 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 102 hctsiz, hc_dma); 103 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 104 chan->dev_addr, chan->ep_num, chan->ep_is_in); 105 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 106 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 107 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 108 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 109 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 110 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 111 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 112 (unsigned long)chan->xfer_dma); 113 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 114 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 115 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 116 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 117 qh_list_entry) 118 dev_dbg(hsotg->dev, " %p\n", qh); 119 dev_dbg(hsotg->dev, " NP active sched:\n"); 120 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 121 qh_list_entry) 122 dev_dbg(hsotg->dev, " %p\n", qh); 123 dev_dbg(hsotg->dev, " Channels:\n"); 124 for (i = 0; i < num_channels; i++) { 125 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 126 127 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 128 } 129 } 130 #endif /* VERBOSE_DEBUG */ 131 132 /* 133 * Processes all the URBs in a single list of QHs. Completes them with 134 * -ETIMEDOUT and frees the QTD. 135 * 136 * Must be called with interrupt disabled and spinlock held 137 */ 138 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 139 struct list_head *qh_list) 140 { 141 struct dwc2_qh *qh, *qh_tmp; 142 struct dwc2_qtd *qtd, *qtd_tmp; 143 144 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 145 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 146 qtd_list_entry) { 147 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 148 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 149 } 150 } 151 } 152 153 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 154 struct list_head *qh_list) 155 { 156 struct dwc2_qtd *qtd, *qtd_tmp; 157 struct dwc2_qh *qh, *qh_tmp; 158 unsigned long flags; 159 160 if (!qh_list->next) 161 /* The list hasn't been initialized yet */ 162 return; 163 164 spin_lock_irqsave(&hsotg->lock, flags); 165 166 /* Ensure there are no QTDs or URBs left */ 167 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 168 169 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 170 dwc2_hcd_qh_unlink(hsotg, qh); 171 172 /* Free each QTD in the QH's QTD list */ 173 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 174 qtd_list_entry) 175 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 176 177 spin_unlock_irqrestore(&hsotg->lock, flags); 178 dwc2_hcd_qh_free(hsotg, qh); 179 spin_lock_irqsave(&hsotg->lock, flags); 180 } 181 182 spin_unlock_irqrestore(&hsotg->lock, flags); 183 } 184 185 /* 186 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 187 * and periodic schedules. The QTD associated with each URB is removed from 188 * the schedule and freed. This function may be called when a disconnect is 189 * detected or when the HCD is being stopped. 190 * 191 * Must be called with interrupt disabled and spinlock held 192 */ 193 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 194 { 195 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 196 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 197 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 198 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 199 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 201 } 202 203 /** 204 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 205 * 206 * @hsotg: Pointer to struct dwc2_hsotg 207 */ 208 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 209 { 210 u32 hprt0; 211 212 if (hsotg->op_state == OTG_STATE_B_HOST) { 213 /* 214 * Reset the port. During a HNP mode switch the reset 215 * needs to occur within 1ms and have a duration of at 216 * least 50ms. 217 */ 218 hprt0 = dwc2_read_hprt0(hsotg); 219 hprt0 |= HPRT0_RST; 220 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 221 } 222 223 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 224 msecs_to_jiffies(50)); 225 } 226 227 /* Must be called with interrupt disabled and spinlock held */ 228 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 229 { 230 int num_channels = hsotg->core_params->host_channels; 231 struct dwc2_host_chan *channel; 232 u32 hcchar; 233 int i; 234 235 if (hsotg->core_params->dma_enable <= 0) { 236 /* Flush out any channel requests in slave mode */ 237 for (i = 0; i < num_channels; i++) { 238 channel = hsotg->hc_ptr_array[i]; 239 if (!list_empty(&channel->hc_list_entry)) 240 continue; 241 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 242 if (hcchar & HCCHAR_CHENA) { 243 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 244 hcchar |= HCCHAR_CHDIS; 245 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 246 } 247 } 248 } 249 250 for (i = 0; i < num_channels; i++) { 251 channel = hsotg->hc_ptr_array[i]; 252 if (!list_empty(&channel->hc_list_entry)) 253 continue; 254 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 255 if (hcchar & HCCHAR_CHENA) { 256 /* Halt the channel */ 257 hcchar |= HCCHAR_CHDIS; 258 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 259 } 260 261 dwc2_hc_cleanup(hsotg, channel); 262 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 263 /* 264 * Added for Descriptor DMA to prevent channel double cleanup in 265 * release_channel_ddma(), which is called from ep_disable when 266 * device disconnects 267 */ 268 channel->qh = NULL; 269 } 270 } 271 272 /** 273 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 274 * 275 * @hsotg: Pointer to struct dwc2_hsotg 276 * 277 * Must be called with interrupt disabled and spinlock held 278 */ 279 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 280 { 281 u32 intr; 282 283 /* Set status flags for the hub driver */ 284 hsotg->flags.b.port_connect_status_change = 1; 285 hsotg->flags.b.port_connect_status = 0; 286 287 /* 288 * Shutdown any transfers in process by clearing the Tx FIFO Empty 289 * interrupt mask and status bits and disabling subsequent host 290 * channel interrupts. 291 */ 292 intr = DWC2_READ_4(hsotg, GINTMSK); 293 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 294 DWC2_WRITE_4(hsotg, GINTMSK, intr); 295 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 296 DWC2_WRITE_4(hsotg, GINTSTS, intr); 297 298 /* 299 * Turn off the vbus power only if the core has transitioned to device 300 * mode. If still in host mode, need to keep power on to detect a 301 * reconnection. 302 */ 303 if (dwc2_is_device_mode(hsotg)) { 304 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 305 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 306 DWC2_WRITE_4(hsotg, HPRT0, 0); 307 } 308 309 dwc2_disable_host_interrupts(hsotg); 310 } 311 312 /* Respond with an error status to all URBs in the schedule */ 313 dwc2_kill_all_urbs(hsotg); 314 315 if (dwc2_is_host_mode(hsotg)) 316 /* Clean up any host channels that were in use */ 317 dwc2_hcd_cleanup_channels(hsotg); 318 319 dwc2_host_disconnect(hsotg); 320 321 dwc2_root_intr(hsotg->hsotg_sc); 322 } 323 324 /** 325 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 326 * 327 * @hsotg: Pointer to struct dwc2_hsotg 328 */ 329 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 330 { 331 if (hsotg->lx_state == DWC2_L2) 332 hsotg->flags.b.port_suspend_change = 1; 333 else 334 hsotg->flags.b.port_l1_change = 1; 335 336 dwc2_root_intr(hsotg->hsotg_sc); 337 } 338 339 /** 340 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 341 * 342 * @hsotg: Pointer to struct dwc2_hsotg 343 * 344 * Must be called with interrupt disabled and spinlock held 345 */ 346 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 347 { 348 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 349 350 /* 351 * The root hub should be disconnected before this function is called. 352 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 353 * and the QH lists (via ..._hcd_endpoint_disable). 354 */ 355 356 /* Turn off all host-specific interrupts */ 357 dwc2_disable_host_interrupts(hsotg); 358 359 /* Turn off the vbus power */ 360 dev_dbg(hsotg->dev, "PortPower off\n"); 361 DWC2_WRITE_4(hsotg, HPRT0, 0); 362 } 363 364 int 365 dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 366 void **ep_handle, gfp_t mem_flags) 367 { 368 struct dwc2_softc *sc = hsotg->hsotg_sc; 369 struct dwc2_qtd *qtd; 370 u32 intr_mask; 371 int retval; 372 int dev_speed; 373 374 if (!hsotg->flags.b.port_connect_status) { 375 /* No longer connected */ 376 dev_err(hsotg->dev, "Not connected\n"); 377 return -ENODEV; 378 } 379 380 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 381 382 /* Some core configurations cannot support LS traffic on a FS root port */ 383 if ((dev_speed == USB_SPEED_LOW) && 384 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 385 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 386 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 387 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 388 389 if (prtspd == HPRT0_SPD_FULL_SPEED) { 390 return -ENODEV; 391 } 392 } 393 394 qtd = pool_cache_get(sc->sc_qtdpool, PR_NOWAIT); 395 if (!qtd) 396 return -ENOMEM; 397 398 memset(qtd, 0, sizeof(*qtd)); 399 400 dwc2_hcd_qtd_init(qtd, urb); 401 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 402 mem_flags); 403 if (retval) { 404 dev_err(hsotg->dev, 405 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 406 retval); 407 pool_cache_put(sc->sc_qtdpool, qtd); 408 return retval; 409 } 410 411 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 412 if (!(intr_mask & GINTSTS_SOF)) { 413 enum dwc2_transaction_type tr_type; 414 415 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 416 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 417 /* 418 * Do not schedule SG transactions until qtd has 419 * URB_GIVEBACK_ASAP set 420 */ 421 return 0; 422 423 tr_type = dwc2_hcd_select_transactions(hsotg); 424 if (tr_type != DWC2_TRANSACTION_NONE) 425 dwc2_hcd_queue_transactions(hsotg, tr_type); 426 } 427 428 return 0; 429 } 430 431 /* Must be called with interrupt disabled and spinlock held */ 432 int 433 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 434 struct dwc2_hcd_urb *urb) 435 { 436 struct dwc2_qh *qh; 437 struct dwc2_qtd *urb_qtd; 438 439 urb_qtd = urb->qtd; 440 if (!urb_qtd) { 441 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 442 return -EINVAL; 443 } 444 445 qh = urb_qtd->qh; 446 if (!qh) { 447 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 448 return -EINVAL; 449 } 450 451 urb->priv = NULL; 452 453 if (urb_qtd->in_process && qh->channel) { 454 #ifdef VERBOSE_DEBUG 455 dwc2_dump_channel_info(hsotg, qh->channel); 456 #endif 457 /* The QTD is in process (it has been assigned to a channel) */ 458 if (hsotg->flags.b.port_connect_status) 459 /* 460 * If still connected (i.e. in host mode), halt the 461 * channel so it can be used for other transfers. If 462 * no longer connected, the host registers can't be 463 * written to halt the channel since the core is in 464 * device mode. 465 */ 466 dwc2_hc_halt(hsotg, qh->channel, 467 DWC2_HC_XFER_URB_DEQUEUE); 468 } 469 470 /* 471 * Free the QTD and clean up the associated QH. Leave the QH in the 472 * schedule if it has any remaining QTDs. 473 */ 474 if (hsotg->core_params->dma_desc_enable <= 0) { 475 u8 in_process = urb_qtd->in_process; 476 477 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 478 if (in_process) { 479 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 480 qh->channel = NULL; 481 } else if (list_empty(&qh->qtd_list)) { 482 dwc2_hcd_qh_unlink(hsotg, qh); 483 } 484 } else { 485 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 486 } 487 488 return 0; 489 } 490 491 492 /* 493 * Initializes dynamic portions of the DWC_otg HCD state 494 * 495 * Must be called with interrupt disabled and spinlock held 496 */ 497 void 498 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 499 { 500 struct dwc2_host_chan *chan, *chan_tmp; 501 int num_channels; 502 int i; 503 504 hsotg->flags.d32 = 0; 505 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 506 507 if (hsotg->core_params->uframe_sched > 0) { 508 hsotg->available_host_channels = 509 hsotg->core_params->host_channels; 510 } else { 511 hsotg->non_periodic_channels = 0; 512 hsotg->periodic_channels = 0; 513 } 514 515 /* 516 * Put all channels in the free channel list and clean up channel 517 * states 518 */ 519 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 520 hc_list_entry) 521 list_del_init(&chan->hc_list_entry); 522 523 num_channels = hsotg->core_params->host_channels; 524 for (i = 0; i < num_channels; i++) { 525 chan = hsotg->hc_ptr_array[i]; 526 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 527 dwc2_hc_cleanup(hsotg, chan); 528 } 529 530 /* Initialize the DWC core for host mode operation */ 531 dwc2_core_host_init(hsotg); 532 } 533 534 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 535 struct dwc2_host_chan *chan, 536 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 537 { 538 int hub_addr, hub_port; 539 540 chan->do_split = 1; 541 chan->xact_pos = qtd->isoc_split_pos; 542 chan->complete_split = qtd->complete_split; 543 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 544 chan->hub_addr = (u8)hub_addr; 545 chan->hub_port = (u8)hub_port; 546 } 547 548 static void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 549 struct dwc2_host_chan *chan, 550 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 551 { 552 if (hsotg->core_params->dma_enable > 0) { 553 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 554 555 /* For non-dword aligned case */ 556 if (hsotg->core_params->dma_desc_enable <= 0 && 557 (chan->xfer_dma & 0x3)) 558 return (u8 *)urb->buf + urb->actual_length; 559 } else { 560 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 561 } 562 563 return NULL; 564 } 565 566 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 567 struct dwc2_host_chan *chan, 568 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 569 { 570 struct dwc2_hcd_iso_packet_desc *frame_desc; 571 void *bufptr = NULL; 572 573 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 574 case USB_ENDPOINT_XFER_CONTROL: 575 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 576 577 switch (qtd->control_phase) { 578 case DWC2_CONTROL_SETUP: 579 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 580 chan->do_ping = 0; 581 chan->ep_is_in = 0; 582 chan->data_pid_start = DWC2_HC_PID_SETUP; 583 if (hsotg->core_params->dma_enable > 0) 584 chan->xfer_dma = urb->setup_dma; 585 else 586 chan->xfer_buf = urb->setup_packet; 587 chan->xfer_len = 8; 588 break; 589 590 case DWC2_CONTROL_DATA: 591 dev_vdbg(hsotg->dev, " Control data transaction\n"); 592 chan->data_pid_start = qtd->data_toggle; 593 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 594 break; 595 596 case DWC2_CONTROL_STATUS: 597 /* 598 * Direction is opposite of data direction or IN if no 599 * data 600 */ 601 dev_vdbg(hsotg->dev, " Control status transaction\n"); 602 if (urb->length == 0) 603 chan->ep_is_in = 1; 604 else 605 chan->ep_is_in = 606 dwc2_hcd_is_pipe_out(&urb->pipe_info); 607 if (chan->ep_is_in) 608 chan->do_ping = 0; 609 chan->data_pid_start = DWC2_HC_PID_DATA1; 610 chan->xfer_len = 0; 611 if (hsotg->core_params->dma_enable > 0) 612 chan->xfer_dma = hsotg->status_buf_dma; 613 else 614 chan->xfer_buf = hsotg->status_buf; 615 break; 616 } 617 break; 618 619 case USB_ENDPOINT_XFER_BULK: 620 chan->ep_type = USB_ENDPOINT_XFER_BULK; 621 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 622 break; 623 624 case USB_ENDPOINT_XFER_INT: 625 chan->ep_type = USB_ENDPOINT_XFER_INT; 626 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 627 break; 628 629 case USB_ENDPOINT_XFER_ISOC: 630 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 631 if (hsotg->core_params->dma_desc_enable > 0) 632 break; 633 634 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 635 frame_desc->status = 0; 636 637 if (hsotg->core_params->dma_enable > 0) { 638 chan->xfer_dma = urb->dma; 639 chan->xfer_dma += frame_desc->offset + 640 qtd->isoc_split_offset; 641 } else { 642 chan->xfer_buf = urb->buf; 643 chan->xfer_buf += frame_desc->offset + 644 qtd->isoc_split_offset; 645 } 646 647 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 648 649 /* For non-dword aligned buffers */ 650 if (hsotg->core_params->dma_enable > 0 && 651 (chan->xfer_dma & 0x3)) 652 bufptr = (u8 *)urb->buf + frame_desc->offset + 653 qtd->isoc_split_offset; 654 655 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 656 if (chan->xfer_len <= 188) 657 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 658 else 659 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 660 } 661 break; 662 } 663 664 return bufptr; 665 } 666 667 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 668 struct dwc2_host_chan *chan, void *bufptr) 669 { 670 u32 buf_size; 671 672 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 673 buf_size = hsotg->core_params->max_transfer_size; 674 else 675 buf_size = 4096; 676 677 if (!qh->dw_align_buf) { 678 int err; 679 680 qh->dw_align_buf = NULL; 681 qh->dw_align_buf_dma = 0; 682 err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, buf_size, buf_size, 683 &qh->dw_align_buf_usbdma); 684 if (!err) { 685 usb_dma_t *ud = &qh->dw_align_buf_usbdma; 686 687 qh->dw_align_buf = KERNADDR(ud, 0); 688 qh->dw_align_buf_dma = DMAADDR(ud, 0); 689 } 690 if (!qh->dw_align_buf) 691 return -ENOMEM; 692 } 693 694 if (!chan->ep_is_in && chan->xfer_len) { 695 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 696 BUS_DMASYNC_POSTWRITE); 697 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len); 698 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 699 BUS_DMASYNC_PREWRITE); 700 } 701 702 chan->align_buf = qh->dw_align_buf_dma; 703 return 0; 704 } 705 706 /** 707 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 708 * channel and initializes the host channel to perform the transactions. The 709 * host channel is removed from the free list. 710 * 711 * @hsotg: The HCD state structure 712 * @qh: Transactions from the first QTD for this QH are selected and assigned 713 * to a free host channel 714 */ 715 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 716 { 717 struct dwc2_host_chan *chan; 718 struct dwc2_hcd_urb *urb; 719 struct dwc2_qtd *qtd; 720 void *bufptr = NULL; 721 722 if (dbg_qh(qh)) 723 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 724 725 if (list_empty(&qh->qtd_list)) { 726 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 727 return -ENOMEM; 728 } 729 730 if (list_empty(&hsotg->free_hc_list)) { 731 dev_dbg(hsotg->dev, "No free channel to assign\n"); 732 return -ENOMEM; 733 } 734 735 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 736 hc_list_entry); 737 738 /* Remove host channel from free list */ 739 list_del_init(&chan->hc_list_entry); 740 741 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 742 urb = qtd->urb; 743 qh->channel = chan; 744 qtd->in_process = 1; 745 746 /* 747 * Use usb_pipedevice to determine device address. This address is 748 * 0 before the SET_ADDRESS command and the correct address afterward. 749 */ 750 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 751 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 752 chan->speed = qh->dev_speed; 753 chan->max_packet = dwc2_max_packet(qh->maxp); 754 755 chan->xfer_started = 0; 756 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 757 chan->error_state = (qtd->error_count > 0); 758 chan->halt_on_queue = 0; 759 chan->halt_pending = 0; 760 chan->requests = 0; 761 762 /* 763 * The following values may be modified in the transfer type section 764 * below. The xfer_len value may be reduced when the transfer is 765 * started to accommodate the max widths of the XferSize and PktCnt 766 * fields in the HCTSIZn register. 767 */ 768 769 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 770 if (chan->ep_is_in) 771 chan->do_ping = 0; 772 else 773 chan->do_ping = qh->ping_state; 774 775 chan->data_pid_start = qh->data_toggle; 776 chan->multi_count = 1; 777 778 if (urb->actual_length > urb->length && 779 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 780 urb->actual_length = urb->length; 781 782 chan->xfer_len = urb->length - urb->actual_length; 783 chan->xfer_count = 0; 784 785 /* Set the split attributes if required */ 786 if (qh->do_split) 787 dwc2_hc_init_split(hsotg, chan, qtd, urb); 788 else 789 chan->do_split = 0; 790 791 /* Set the transfer attributes */ 792 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 793 794 /* Non DWORD-aligned buffer case */ 795 if (bufptr) { 796 dev_vdbg(hsotg->dev, "Non-aligned buffer%p\n", bufptr); 797 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) { 798 dev_err(hsotg->dev, 799 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 800 __func__); 801 /* Add channel back to free list */ 802 chan->align_buf = 0; 803 chan->multi_count = 0; 804 list_add_tail(&chan->hc_list_entry, 805 &hsotg->free_hc_list); 806 qtd->in_process = 0; 807 qh->channel = NULL; 808 return -ENOMEM; 809 } 810 } else { 811 chan->align_buf = 0; 812 } 813 814 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 815 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 816 /* 817 * This value may be modified when the transfer is started 818 * to reflect the actual transfer length 819 */ 820 chan->multi_count = dwc2_hb_mult(qh->maxp); 821 822 if (hsotg->core_params->dma_desc_enable > 0) 823 chan->desc_list_addr = qh->desc_list_dma; 824 825 dwc2_hc_init(hsotg, chan); 826 chan->qh = qh; 827 828 return 0; 829 } 830 831 /** 832 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 833 * schedule and assigns them to available host channels. Called from the HCD 834 * interrupt handler functions. 835 * 836 * @hsotg: The HCD state structure 837 * 838 * Return: The types of new transactions that were assigned to host channels 839 */ 840 enum dwc2_transaction_type dwc2_hcd_select_transactions( 841 struct dwc2_hsotg *hsotg) 842 { 843 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 844 struct list_head *qh_ptr; 845 struct dwc2_qh *qh; 846 int num_channels; 847 848 #ifdef DWC2_DEBUG_SOF 849 dev_vdbg(hsotg->dev, " Select Transactions\n"); 850 #endif 851 852 /* Process entries in the periodic ready list */ 853 qh_ptr = hsotg->periodic_sched_ready.next; 854 while (qh_ptr != &hsotg->periodic_sched_ready) { 855 if (list_empty(&hsotg->free_hc_list)) 856 break; 857 if (hsotg->core_params->uframe_sched > 0) { 858 if (hsotg->available_host_channels <= 1) 859 break; 860 hsotg->available_host_channels--; 861 } 862 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 863 if (dwc2_assign_and_init_hc(hsotg, qh)) 864 break; 865 866 /* 867 * Move the QH from the periodic ready schedule to the 868 * periodic assigned schedule 869 */ 870 qh_ptr = qh_ptr->next; 871 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 872 ret_val = DWC2_TRANSACTION_PERIODIC; 873 } 874 875 /* 876 * Process entries in the inactive portion of the non-periodic 877 * schedule. Some free host channels may not be used if they are 878 * reserved for periodic transfers. 879 */ 880 num_channels = hsotg->core_params->host_channels; 881 qh_ptr = hsotg->non_periodic_sched_inactive.next; 882 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 883 if (hsotg->core_params->uframe_sched <= 0 && 884 hsotg->non_periodic_channels >= num_channels - 885 hsotg->periodic_channels) 886 break; 887 if (list_empty(&hsotg->free_hc_list)) 888 break; 889 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 890 if (hsotg->core_params->uframe_sched > 0) { 891 if (hsotg->available_host_channels < 1) 892 break; 893 hsotg->available_host_channels--; 894 } 895 896 if (dwc2_assign_and_init_hc(hsotg, qh)) 897 break; 898 899 /* 900 * Move the QH from the non-periodic inactive schedule to the 901 * non-periodic active schedule 902 */ 903 qh_ptr = qh_ptr->next; 904 list_move(&qh->qh_list_entry, 905 &hsotg->non_periodic_sched_active); 906 907 if (ret_val == DWC2_TRANSACTION_NONE) 908 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 909 else 910 ret_val = DWC2_TRANSACTION_ALL; 911 912 if (hsotg->core_params->uframe_sched <= 0) 913 hsotg->non_periodic_channels++; 914 } 915 916 return ret_val; 917 } 918 919 /** 920 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 921 * a host channel associated with either a periodic or non-periodic transfer 922 * 923 * @hsotg: The HCD state structure 924 * @chan: Host channel descriptor associated with either a periodic or 925 * non-periodic transfer 926 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 927 * for periodic transfers or the non-periodic Tx FIFO 928 * for non-periodic transfers 929 * 930 * Return: 1 if a request is queued and more requests may be needed to 931 * complete the transfer, 0 if no more requests are required for this 932 * transfer, -1 if there is insufficient space in the Tx FIFO 933 * 934 * This function assumes that there is space available in the appropriate 935 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 936 * it checks whether space is available in the appropriate Tx FIFO. 937 * 938 * Must be called with interrupt disabled and spinlock held 939 */ 940 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 941 struct dwc2_host_chan *chan, 942 u16 fifo_dwords_avail) 943 { 944 int retval = 0; 945 946 if (hsotg->core_params->dma_enable > 0) { 947 if (hsotg->core_params->dma_desc_enable > 0) { 948 if (!chan->xfer_started || 949 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 950 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 951 chan->qh->ping_state = 0; 952 } 953 } else if (!chan->xfer_started) { 954 dwc2_hc_start_transfer(hsotg, chan); 955 chan->qh->ping_state = 0; 956 } 957 } else if (chan->halt_pending) { 958 /* Don't queue a request if the channel has been halted */ 959 } else if (chan->halt_on_queue) { 960 dwc2_hc_halt(hsotg, chan, chan->halt_status); 961 } else if (chan->do_ping) { 962 if (!chan->xfer_started) 963 dwc2_hc_start_transfer(hsotg, chan); 964 } else if (!chan->ep_is_in || 965 chan->data_pid_start == DWC2_HC_PID_SETUP) { 966 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 967 if (!chan->xfer_started) { 968 dwc2_hc_start_transfer(hsotg, chan); 969 retval = 1; 970 } else { 971 retval = dwc2_hc_continue_transfer(hsotg, chan); 972 } 973 } else { 974 retval = -1; 975 } 976 } else { 977 if (!chan->xfer_started) { 978 dwc2_hc_start_transfer(hsotg, chan); 979 retval = 1; 980 } else { 981 retval = dwc2_hc_continue_transfer(hsotg, chan); 982 } 983 } 984 985 return retval; 986 } 987 988 /* 989 * Processes periodic channels for the next frame and queues transactions for 990 * these channels to the DWC_otg controller. After queueing transactions, the 991 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 992 * to queue as Periodic Tx FIFO or request queue space becomes available. 993 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 994 * 995 * Must be called with interrupt disabled and spinlock held 996 */ 997 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 998 { 999 struct list_head *qh_ptr; 1000 struct dwc2_qh *qh; 1001 u32 tx_status; 1002 u32 fspcavail; 1003 u32 gintmsk; 1004 int status; 1005 int no_queue_space = 0; 1006 int no_fifo_space = 0; 1007 u32 qspcavail; 1008 1009 if (dbg_perio()) 1010 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1011 1012 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1013 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1014 TXSTS_QSPCAVAIL_SHIFT; 1015 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1016 TXSTS_FSPCAVAIL_SHIFT; 1017 1018 if (dbg_perio()) { 1019 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1020 qspcavail); 1021 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1022 fspcavail); 1023 } 1024 1025 qh_ptr = hsotg->periodic_sched_assigned.next; 1026 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1027 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1028 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1029 TXSTS_QSPCAVAIL_SHIFT; 1030 if (qspcavail == 0) { 1031 no_queue_space = 1; 1032 break; 1033 } 1034 1035 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1036 if (!qh->channel) { 1037 qh_ptr = qh_ptr->next; 1038 continue; 1039 } 1040 1041 /* Make sure EP's TT buffer is clean before queueing qtds */ 1042 if (qh->tt_buffer_dirty) { 1043 qh_ptr = qh_ptr->next; 1044 continue; 1045 } 1046 1047 /* 1048 * Set a flag if we're queuing high-bandwidth in slave mode. 1049 * The flag prevents any halts to get into the request queue in 1050 * the middle of multiple high-bandwidth packets getting queued. 1051 */ 1052 if (hsotg->core_params->dma_enable <= 0 && 1053 qh->channel->multi_count > 1) 1054 hsotg->queuing_high_bandwidth = 1; 1055 1056 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1057 TXSTS_FSPCAVAIL_SHIFT; 1058 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1059 if (status < 0) { 1060 no_fifo_space = 1; 1061 break; 1062 } 1063 1064 /* 1065 * In Slave mode, stay on the current transfer until there is 1066 * nothing more to do or the high-bandwidth request count is 1067 * reached. In DMA mode, only need to queue one request. The 1068 * controller automatically handles multiple packets for 1069 * high-bandwidth transfers. 1070 */ 1071 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1072 qh->channel->requests == qh->channel->multi_count) { 1073 qh_ptr = qh_ptr->next; 1074 /* 1075 * Move the QH from the periodic assigned schedule to 1076 * the periodic queued schedule 1077 */ 1078 list_move(&qh->qh_list_entry, 1079 &hsotg->periodic_sched_queued); 1080 1081 /* done queuing high bandwidth */ 1082 hsotg->queuing_high_bandwidth = 0; 1083 } 1084 } 1085 1086 if (hsotg->core_params->dma_enable <= 0) { 1087 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1088 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1089 TXSTS_QSPCAVAIL_SHIFT; 1090 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1091 TXSTS_FSPCAVAIL_SHIFT; 1092 if (dbg_perio()) { 1093 dev_vdbg(hsotg->dev, 1094 " P Tx Req Queue Space Avail (after queue): %d\n", 1095 qspcavail); 1096 dev_vdbg(hsotg->dev, 1097 " P Tx FIFO Space Avail (after queue): %d\n", 1098 fspcavail); 1099 } 1100 1101 if (!list_empty(&hsotg->periodic_sched_assigned) || 1102 no_queue_space || no_fifo_space) { 1103 /* 1104 * May need to queue more transactions as the request 1105 * queue or Tx FIFO empties. Enable the periodic Tx 1106 * FIFO empty interrupt. (Always use the half-empty 1107 * level to ensure that new requests are loaded as 1108 * soon as possible.) 1109 */ 1110 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1111 gintmsk |= GINTSTS_PTXFEMP; 1112 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1113 } else { 1114 /* 1115 * Disable the Tx FIFO empty interrupt since there are 1116 * no more transactions that need to be queued right 1117 * now. This function is called from interrupt 1118 * handlers to queue more transactions as transfer 1119 * states change. 1120 */ 1121 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1122 gintmsk &= ~GINTSTS_PTXFEMP; 1123 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1124 } 1125 } 1126 } 1127 1128 /* 1129 * Processes active non-periodic channels and queues transactions for these 1130 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1131 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1132 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1133 * FIFO Empty interrupt is disabled. 1134 * 1135 * Must be called with interrupt disabled and spinlock held 1136 */ 1137 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1138 { 1139 struct list_head *orig_qh_ptr; 1140 struct dwc2_qh *qh; 1141 u32 tx_status; 1142 u32 qspcavail; 1143 u32 fspcavail; 1144 u32 gintmsk; 1145 int status; 1146 int no_queue_space = 0; 1147 int no_fifo_space = 0; 1148 int more_to_do = 0; 1149 1150 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1151 1152 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1153 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1154 TXSTS_QSPCAVAIL_SHIFT; 1155 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1156 TXSTS_FSPCAVAIL_SHIFT; 1157 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1158 qspcavail); 1159 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1160 fspcavail); 1161 1162 /* 1163 * Keep track of the starting point. Skip over the start-of-list 1164 * entry. 1165 */ 1166 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1167 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1168 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1169 1170 /* 1171 * Process once through the active list or until no more space is 1172 * available in the request queue or the Tx FIFO 1173 */ 1174 do { 1175 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1176 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1177 TXSTS_QSPCAVAIL_SHIFT; 1178 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1179 no_queue_space = 1; 1180 break; 1181 } 1182 1183 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1184 qh_list_entry); 1185 if (!qh->channel) 1186 goto next; 1187 1188 /* Make sure EP's TT buffer is clean before queueing qtds */ 1189 if (qh->tt_buffer_dirty) 1190 goto next; 1191 1192 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1193 TXSTS_FSPCAVAIL_SHIFT; 1194 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1195 1196 if (status > 0) { 1197 more_to_do = 1; 1198 } else if (status < 0) { 1199 no_fifo_space = 1; 1200 break; 1201 } 1202 next: 1203 /* Advance to next QH, skipping start-of-list entry */ 1204 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1205 if (hsotg->non_periodic_qh_ptr == 1206 &hsotg->non_periodic_sched_active) 1207 hsotg->non_periodic_qh_ptr = 1208 hsotg->non_periodic_qh_ptr->next; 1209 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1210 1211 if (hsotg->core_params->dma_enable <= 0) { 1212 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1213 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1214 TXSTS_QSPCAVAIL_SHIFT; 1215 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1216 TXSTS_FSPCAVAIL_SHIFT; 1217 dev_vdbg(hsotg->dev, 1218 " NP Tx Req Queue Space Avail (after queue): %d\n", 1219 qspcavail); 1220 dev_vdbg(hsotg->dev, 1221 " NP Tx FIFO Space Avail (after queue): %d\n", 1222 fspcavail); 1223 1224 if (more_to_do || no_queue_space || no_fifo_space) { 1225 /* 1226 * May need to queue more transactions as the request 1227 * queue or Tx FIFO empties. Enable the non-periodic 1228 * Tx FIFO empty interrupt. (Always use the half-empty 1229 * level to ensure that new requests are loaded as 1230 * soon as possible.) 1231 */ 1232 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1233 gintmsk |= GINTSTS_NPTXFEMP; 1234 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1235 } else { 1236 /* 1237 * Disable the Tx FIFO empty interrupt since there are 1238 * no more transactions that need to be queued right 1239 * now. This function is called from interrupt 1240 * handlers to queue more transactions as transfer 1241 * states change. 1242 */ 1243 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1244 gintmsk &= ~GINTSTS_NPTXFEMP; 1245 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1246 } 1247 } 1248 } 1249 1250 /** 1251 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1252 * and queues transactions for these channels to the DWC_otg controller. Called 1253 * from the HCD interrupt handler functions. 1254 * 1255 * @hsotg: The HCD state structure 1256 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1257 * or both) 1258 * 1259 * Must be called with interrupt disabled and spinlock held 1260 */ 1261 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1262 enum dwc2_transaction_type tr_type) 1263 { 1264 #ifdef DWC2_DEBUG_SOF 1265 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1266 #endif 1267 /* Process host channels associated with periodic transfers */ 1268 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1269 tr_type == DWC2_TRANSACTION_ALL) && 1270 !list_empty(&hsotg->periodic_sched_assigned)) 1271 dwc2_process_periodic_channels(hsotg); 1272 1273 /* Process host channels associated with non-periodic transfers */ 1274 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1275 tr_type == DWC2_TRANSACTION_ALL) { 1276 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1277 dwc2_process_non_periodic_channels(hsotg); 1278 } else { 1279 /* 1280 * Ensure NP Tx FIFO empty interrupt is disabled when 1281 * there are no non-periodic transfers to process 1282 */ 1283 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1284 1285 gintmsk &= ~GINTSTS_NPTXFEMP; 1286 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1287 } 1288 } 1289 } 1290 1291 void 1292 dwc2_conn_id_status_change(struct work *work) 1293 { 1294 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1295 wf_otg); 1296 u32 count = 0; 1297 u32 gotgctl; 1298 1299 dev_dbg(hsotg->dev, "%s()\n", __func__); 1300 1301 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1302 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1303 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1304 !!(gotgctl & GOTGCTL_CONID_B)); 1305 1306 /* B-Device connector (Device Mode) */ 1307 if (gotgctl & GOTGCTL_CONID_B) { 1308 /* Wait for switch to device mode */ 1309 dev_dbg(hsotg->dev, "connId B\n"); 1310 while (!dwc2_is_device_mode(hsotg)) { 1311 dev_info(hsotg->dev, 1312 "Waiting for Peripheral Mode, Mode=%s\n", 1313 dwc2_is_host_mode(hsotg) ? "Host" : 1314 "Peripheral"); 1315 usleep_range(20000, 40000); 1316 if (++count > 250) 1317 break; 1318 } 1319 if (count > 250) 1320 dev_err(hsotg->dev, 1321 "Connection id status change timed out\n"); 1322 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1323 dwc2_core_init(hsotg, false); 1324 dwc2_enable_global_interrupts(hsotg); 1325 } else { 1326 /* A-Device connector (Host Mode) */ 1327 dev_dbg(hsotg->dev, "connId A\n"); 1328 while (!dwc2_is_host_mode(hsotg)) { 1329 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1330 dwc2_is_host_mode(hsotg) ? 1331 "Host" : "Peripheral"); 1332 usleep_range(20000, 40000); 1333 if (++count > 250) 1334 break; 1335 } 1336 if (count > 250) 1337 dev_err(hsotg->dev, 1338 "Connection id status change timed out\n"); 1339 hsotg->op_state = OTG_STATE_A_HOST; 1340 1341 /* Initialize the Core for Host mode */ 1342 dwc2_core_init(hsotg, false); 1343 dwc2_enable_global_interrupts(hsotg); 1344 dwc2_hcd_start(hsotg); 1345 } 1346 } 1347 1348 void dwc2_wakeup_detected(void * data) 1349 { 1350 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1351 u32 hprt0; 1352 1353 dev_dbg(hsotg->dev, "%s()\n", __func__); 1354 1355 /* 1356 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1357 * so that OPT tests pass with all PHYs.) 1358 */ 1359 hprt0 = dwc2_read_hprt0(hsotg); 1360 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1361 hprt0 &= ~HPRT0_RES; 1362 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1363 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1364 DWC2_READ_4(hsotg, HPRT0)); 1365 1366 dwc2_hcd_rem_wakeup(hsotg); 1367 1368 /* Change to L0 state */ 1369 hsotg->lx_state = DWC2_L0; 1370 } 1371 1372 /* Must NOT be called with interrupt disabled or spinlock held */ 1373 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1374 { 1375 unsigned long flags; 1376 u32 hprt0; 1377 u32 pcgctl; 1378 u32 gotgctl; 1379 1380 dev_dbg(hsotg->dev, "%s()\n", __func__); 1381 1382 spin_lock_irqsave(&hsotg->lock, flags); 1383 1384 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1385 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1386 gotgctl |= GOTGCTL_HSTSETHNPEN; 1387 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1388 hsotg->op_state = OTG_STATE_A_SUSPEND; 1389 } 1390 1391 hprt0 = dwc2_read_hprt0(hsotg); 1392 hprt0 |= HPRT0_SUSP; 1393 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1394 1395 /* Update lx_state */ 1396 hsotg->lx_state = DWC2_L2; 1397 1398 /* Suspend the Phy Clock */ 1399 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1400 pcgctl |= PCGCTL_STOPPCLK; 1401 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1402 udelay(10); 1403 1404 /* For HNP the bus must be suspended for at least 200ms */ 1405 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1406 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1407 pcgctl &= ~PCGCTL_STOPPCLK; 1408 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1409 1410 spin_unlock_irqrestore(&hsotg->lock, flags); 1411 1412 usleep_range(200000, 250000); 1413 } else { 1414 spin_unlock_irqrestore(&hsotg->lock, flags); 1415 } 1416 } 1417 1418 /* Handles hub class-specific requests */ 1419 int 1420 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1421 u16 wvalue, u16 windex, char *buf, u16 wlength) 1422 { 1423 usb_hub_descriptor_t *hub_desc; 1424 usb_port_status_t ps; 1425 int retval = 0; 1426 u32 hprt0; 1427 u32 port_status; 1428 u32 speed; 1429 u32 pcgctl; 1430 1431 switch (typereq) { 1432 case ClearHubFeature: 1433 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1434 1435 switch (wvalue) { 1436 case C_HUB_LOCAL_POWER: 1437 case C_HUB_OVER_CURRENT: 1438 /* Nothing required here */ 1439 break; 1440 1441 default: 1442 retval = -EINVAL; 1443 dev_err(hsotg->dev, 1444 "ClearHubFeature request %1xh unknown\n", 1445 wvalue); 1446 } 1447 break; 1448 1449 case ClearPortFeature: 1450 // if (wvalue != USB_PORT_FEAT_L1) 1451 if (!windex || windex > 1) 1452 goto error; 1453 switch (wvalue) { 1454 case USB_PORT_FEAT_ENABLE: 1455 dev_dbg(hsotg->dev, 1456 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1457 hprt0 = dwc2_read_hprt0(hsotg); 1458 hprt0 |= HPRT0_ENA; 1459 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1460 break; 1461 1462 case USB_PORT_FEAT_SUSPEND: 1463 dev_dbg(hsotg->dev, 1464 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1465 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1466 usleep_range(20000, 40000); 1467 1468 hprt0 = dwc2_read_hprt0(hsotg); 1469 hprt0 |= HPRT0_RES; 1470 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1471 hprt0 &= ~HPRT0_SUSP; 1472 usleep_range(100000, 150000); 1473 1474 hprt0 &= ~HPRT0_RES; 1475 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1476 break; 1477 1478 case USB_PORT_FEAT_POWER: 1479 dev_dbg(hsotg->dev, 1480 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1481 hprt0 = dwc2_read_hprt0(hsotg); 1482 hprt0 &= ~HPRT0_PWR; 1483 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1484 break; 1485 1486 case USB_PORT_FEAT_INDICATOR: 1487 dev_dbg(hsotg->dev, 1488 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1489 /* Port indicator not supported */ 1490 break; 1491 1492 case USB_PORT_FEAT_C_CONNECTION: 1493 /* 1494 * Clears driver's internal Connect Status Change flag 1495 */ 1496 dev_dbg(hsotg->dev, 1497 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1498 hsotg->flags.b.port_connect_status_change = 0; 1499 break; 1500 1501 case USB_PORT_FEAT_C_RESET: 1502 /* Clears driver's internal Port Reset Change flag */ 1503 dev_dbg(hsotg->dev, 1504 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1505 hsotg->flags.b.port_reset_change = 0; 1506 break; 1507 1508 case USB_PORT_FEAT_C_ENABLE: 1509 /* 1510 * Clears the driver's internal Port Enable/Disable 1511 * Change flag 1512 */ 1513 dev_dbg(hsotg->dev, 1514 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1515 hsotg->flags.b.port_enable_change = 0; 1516 break; 1517 1518 case USB_PORT_FEAT_C_SUSPEND: 1519 /* 1520 * Clears the driver's internal Port Suspend Change 1521 * flag, which is set when resume signaling on the host 1522 * port is complete 1523 */ 1524 dev_dbg(hsotg->dev, 1525 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1526 hsotg->flags.b.port_suspend_change = 0; 1527 break; 1528 1529 case USB_PORT_FEAT_C_PORT_L1: 1530 dev_dbg(hsotg->dev, 1531 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1532 hsotg->flags.b.port_l1_change = 0; 1533 break; 1534 1535 case USB_PORT_FEAT_C_OVER_CURRENT: 1536 dev_dbg(hsotg->dev, 1537 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1538 hsotg->flags.b.port_over_current_change = 0; 1539 break; 1540 1541 default: 1542 retval = -EINVAL; 1543 dev_err(hsotg->dev, 1544 "ClearPortFeature request %1xh unknown or unsupported\n", 1545 wvalue); 1546 } 1547 break; 1548 1549 case GetHubDescriptor: 1550 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1551 hub_desc = (usb_hub_descriptor_t *)buf; 1552 hub_desc->bDescLength = 9; 1553 hub_desc->bDescriptorType = 0x29; 1554 hub_desc->bNbrPorts = 1; 1555 USETW(hub_desc->wHubCharacteristics, 0x08); 1556 hub_desc->bPwrOn2PwrGood = 1; 1557 hub_desc->bHubContrCurrent = 0; 1558 hub_desc->DeviceRemovable[0] = 0; 1559 hub_desc->DeviceRemovable[1] = 0xff; 1560 break; 1561 1562 case GetHubStatus: 1563 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1564 memset(buf, 0, 4); 1565 break; 1566 1567 case GetPortStatus: 1568 dev_vdbg(hsotg->dev, 1569 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1570 hsotg->flags.d32); 1571 if (!windex || windex > 1) 1572 goto error; 1573 1574 port_status = 0; 1575 if (hsotg->flags.b.port_connect_status_change) 1576 port_status |= USB_PORT_STAT_C_CONNECTION; 1577 if (hsotg->flags.b.port_enable_change) 1578 port_status |= USB_PORT_STAT_C_ENABLE; 1579 if (hsotg->flags.b.port_suspend_change) 1580 port_status |= USB_PORT_STAT_C_SUSPEND; 1581 if (hsotg->flags.b.port_l1_change) 1582 port_status |= USB_PORT_STAT_C_L1; 1583 if (hsotg->flags.b.port_reset_change) 1584 port_status |= USB_PORT_STAT_C_RESET; 1585 if (hsotg->flags.b.port_over_current_change) { 1586 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1587 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1588 } 1589 USETW(ps.wPortChange, port_status); 1590 1591 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1592 if (!hsotg->flags.b.port_connect_status) { 1593 /* 1594 * The port is disconnected, which means the core is 1595 * either in device mode or it soon will be. Just 1596 * return 0's for the remainder of the port status 1597 * since the port register can't be read if the core 1598 * is in device mode. 1599 */ 1600 USETW(ps.wPortStatus, 0); 1601 memcpy(buf, &ps, sizeof(ps)); 1602 break; 1603 } 1604 1605 port_status = 0; 1606 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1607 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1608 1609 if (hprt0 & HPRT0_CONNSTS) 1610 port_status |= USB_PORT_STAT_CONNECTION; 1611 if (hprt0 & HPRT0_ENA) 1612 port_status |= USB_PORT_STAT_ENABLE; 1613 if (hprt0 & HPRT0_SUSP) 1614 port_status |= USB_PORT_STAT_SUSPEND; 1615 if (hprt0 & HPRT0_OVRCURRACT) 1616 port_status |= USB_PORT_STAT_OVERCURRENT; 1617 if (hprt0 & HPRT0_RST) 1618 port_status |= USB_PORT_STAT_RESET; 1619 if (hprt0 & HPRT0_PWR) 1620 port_status |= USB_PORT_STAT_POWER; 1621 1622 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1623 if (speed == HPRT0_SPD_HIGH_SPEED) 1624 port_status |= USB_PORT_STAT_HIGH_SPEED; 1625 else if (speed == HPRT0_SPD_LOW_SPEED) 1626 port_status |= USB_PORT_STAT_LOW_SPEED; 1627 1628 if (hprt0 & HPRT0_TSTCTL_MASK) 1629 port_status |= USB_PORT_STAT_TEST; 1630 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1631 USETW(ps.wPortStatus, port_status); 1632 1633 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1634 memcpy(buf, &ps, sizeof(ps)); 1635 break; 1636 1637 case SetHubFeature: 1638 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1639 /* No HUB features supported */ 1640 break; 1641 1642 case SetPortFeature: 1643 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1644 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1645 goto error; 1646 1647 if (!hsotg->flags.b.port_connect_status) { 1648 /* 1649 * The port is disconnected, which means the core is 1650 * either in device mode or it soon will be. Just 1651 * return without doing anything since the port 1652 * register can't be written if the core is in device 1653 * mode. 1654 */ 1655 break; 1656 } 1657 1658 switch (wvalue) { 1659 case USB_PORT_FEAT_SUSPEND: 1660 dev_dbg(hsotg->dev, 1661 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1662 if (windex != hsotg->otg_port) 1663 goto error; 1664 dwc2_port_suspend(hsotg, windex); 1665 break; 1666 1667 case USB_PORT_FEAT_POWER: 1668 dev_dbg(hsotg->dev, 1669 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1670 hprt0 = dwc2_read_hprt0(hsotg); 1671 hprt0 |= HPRT0_PWR; 1672 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1673 break; 1674 1675 case USB_PORT_FEAT_RESET: 1676 hprt0 = dwc2_read_hprt0(hsotg); 1677 dev_dbg(hsotg->dev, 1678 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1679 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1680 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1681 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1682 /* ??? Original driver does this */ 1683 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1684 1685 hprt0 = dwc2_read_hprt0(hsotg); 1686 /* Clear suspend bit if resetting from suspend state */ 1687 hprt0 &= ~HPRT0_SUSP; 1688 1689 /* 1690 * When B-Host the Port reset bit is set in the Start 1691 * HCD Callback function, so that the reset is started 1692 * within 1ms of the HNP success interrupt 1693 */ 1694 if (!dwc2_hcd_is_b_host(hsotg)) { 1695 hprt0 |= HPRT0_PWR | HPRT0_RST; 1696 dev_dbg(hsotg->dev, 1697 "In host mode, hprt0=%08x\n", hprt0); 1698 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1699 } 1700 1701 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1702 usleep_range(50000, 70000); 1703 hprt0 &= ~HPRT0_RST; 1704 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1705 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1706 break; 1707 1708 case USB_PORT_FEAT_INDICATOR: 1709 dev_dbg(hsotg->dev, 1710 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1711 /* Not supported */ 1712 break; 1713 1714 default: 1715 retval = -EINVAL; 1716 dev_err(hsotg->dev, 1717 "SetPortFeature %1xh unknown or unsupported\n", 1718 wvalue); 1719 break; 1720 } 1721 break; 1722 1723 default: 1724 error: 1725 retval = -EINVAL; 1726 dev_dbg(hsotg->dev, 1727 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1728 typereq, windex, wvalue); 1729 break; 1730 } 1731 1732 return retval; 1733 } 1734 1735 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1736 { 1737 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1738 1739 #ifdef DWC2_DEBUG_SOF 1740 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1741 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1742 #endif 1743 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1744 } 1745 1746 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1747 { 1748 return hsotg->op_state == OTG_STATE_B_HOST; 1749 } 1750 1751 struct dwc2_hcd_urb * 1752 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1753 gfp_t mem_flags) 1754 { 1755 struct dwc2_hcd_urb *urb; 1756 u32 size = sizeof(*urb) + iso_desc_count * 1757 sizeof(struct dwc2_hcd_iso_packet_desc); 1758 1759 urb = kmem_zalloc(size, mem_flags); 1760 if (urb) 1761 urb->packet_count = iso_desc_count; 1762 return urb; 1763 } 1764 1765 void 1766 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1767 int iso_desc_count) 1768 { 1769 1770 u32 size = sizeof(*urb) + iso_desc_count * 1771 sizeof(struct dwc2_hcd_iso_packet_desc); 1772 1773 kmem_free(urb, size); 1774 } 1775 1776 void 1777 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1778 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1779 u16 mps) 1780 { 1781 if (dbg_perio() || 1782 ep_type == USB_ENDPOINT_XFER_BULK || 1783 ep_type == USB_ENDPOINT_XFER_CONTROL) 1784 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1785 urb->pipe_info.dev_addr = dev_addr; 1786 urb->pipe_info.ep_num = ep_num; 1787 urb->pipe_info.pipe_type = ep_type; 1788 urb->pipe_info.pipe_dir = ep_dir; 1789 urb->pipe_info.mps = mps; 1790 } 1791 1792 /* 1793 * NOTE: This function will be removed once the peripheral controller code 1794 * is integrated and the driver is stable 1795 */ 1796 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1797 { 1798 #ifdef DWC2_DEBUG 1799 struct dwc2_host_chan *chan; 1800 struct dwc2_hcd_urb *urb; 1801 struct dwc2_qtd *qtd; 1802 int num_channels; 1803 u32 np_tx_status; 1804 u32 p_tx_status; 1805 int i; 1806 1807 num_channels = hsotg->core_params->host_channels; 1808 dev_dbg(hsotg->dev, "\n"); 1809 dev_dbg(hsotg->dev, 1810 "************************************************************\n"); 1811 dev_dbg(hsotg->dev, "HCD State:\n"); 1812 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1813 1814 for (i = 0; i < num_channels; i++) { 1815 chan = hsotg->hc_ptr_array[i]; 1816 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1817 dev_dbg(hsotg->dev, 1818 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1819 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1820 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1821 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1822 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1823 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1824 chan->data_pid_start); 1825 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1826 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1827 chan->xfer_started); 1828 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1829 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1830 (unsigned long)chan->xfer_dma); 1831 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1832 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1833 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1834 chan->halt_on_queue); 1835 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1836 chan->halt_pending); 1837 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1838 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1839 dev_dbg(hsotg->dev, " complete_split: %d\n", 1840 chan->complete_split); 1841 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1842 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1843 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1844 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1845 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1846 1847 if (chan->xfer_started) { 1848 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", 1849 DWC2_READ_4(hsotg, HFNUM)); 1850 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", 1851 DWC2_READ_4(hsotg, HCCHAR(i))); 1852 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", 1853 DWC2_READ_4(hsotg, HCTSIZ(i))); 1854 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", 1855 DWC2_READ_4(hsotg, HCINT(i))); 1856 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", 1857 DWC2_READ_4(hsotg, HCINTMSK(i))); 1858 } 1859 1860 if (!(chan->xfer_started && chan->qh)) 1861 continue; 1862 1863 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1864 if (!qtd->in_process) 1865 break; 1866 urb = qtd->urb; 1867 dev_dbg(hsotg->dev, " URB Info:\n"); 1868 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1869 qtd, urb); 1870 if (urb) { 1871 dev_dbg(hsotg->dev, 1872 " Dev: %d, EP: %d %s\n", 1873 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1874 dwc2_hcd_get_ep_num(&urb->pipe_info), 1875 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1876 "IN" : "OUT"); 1877 dev_dbg(hsotg->dev, 1878 " Max packet size: %d\n", 1879 dwc2_hcd_get_mps(&urb->pipe_info)); 1880 dev_dbg(hsotg->dev, 1881 " transfer_buffer: %p\n", 1882 urb->buf); 1883 dev_dbg(hsotg->dev, 1884 " transfer_dma: %08lx\n", 1885 (unsigned long)urb->dma); 1886 dev_dbg(hsotg->dev, 1887 " transfer_buffer_length: %d\n", 1888 urb->length); 1889 dev_dbg(hsotg->dev, " actual_length: %d\n", 1890 urb->actual_length); 1891 } 1892 } 1893 } 1894 1895 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1896 hsotg->non_periodic_channels); 1897 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1898 hsotg->periodic_channels); 1899 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1900 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1901 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1902 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1903 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1904 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1905 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1906 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1907 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1908 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1909 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1910 dwc2_hcd_dump_frrem(hsotg); 1911 1912 dwc2_dump_global_registers(hsotg); 1913 dwc2_dump_host_registers(hsotg); 1914 dev_dbg(hsotg->dev, 1915 "************************************************************\n"); 1916 dev_dbg(hsotg->dev, "\n"); 1917 #endif 1918 } 1919 1920 /* 1921 * NOTE: This function will be removed once the peripheral controller code 1922 * is integrated and the driver is stable 1923 */ 1924 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 1925 { 1926 #ifdef DWC2_DUMP_FRREM 1927 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 1928 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1929 hsotg->frrem_samples, hsotg->frrem_accum, 1930 hsotg->frrem_samples > 0 ? 1931 hsotg->frrem_accum / hsotg->frrem_samples : 0); 1932 dev_dbg(hsotg->dev, "\n"); 1933 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 1934 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1935 hsotg->hfnum_7_samples, 1936 hsotg->hfnum_7_frrem_accum, 1937 hsotg->hfnum_7_samples > 0 ? 1938 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 1939 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 1940 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1941 hsotg->hfnum_0_samples, 1942 hsotg->hfnum_0_frrem_accum, 1943 hsotg->hfnum_0_samples > 0 ? 1944 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 1945 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 1946 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1947 hsotg->hfnum_other_samples, 1948 hsotg->hfnum_other_frrem_accum, 1949 hsotg->hfnum_other_samples > 0 ? 1950 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 1951 0); 1952 dev_dbg(hsotg->dev, "\n"); 1953 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 1954 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1955 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 1956 hsotg->hfnum_7_samples_a > 0 ? 1957 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 1958 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 1959 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1960 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 1961 hsotg->hfnum_0_samples_a > 0 ? 1962 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 1963 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 1964 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1965 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 1966 hsotg->hfnum_other_samples_a > 0 ? 1967 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 1968 : 0); 1969 dev_dbg(hsotg->dev, "\n"); 1970 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 1971 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1972 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 1973 hsotg->hfnum_7_samples_b > 0 ? 1974 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 1975 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 1976 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1977 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 1978 (hsotg->hfnum_0_samples_b > 0) ? 1979 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 1980 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 1981 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1982 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 1983 (hsotg->hfnum_other_samples_b > 0) ? 1984 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 1985 : 0); 1986 #endif 1987 } 1988 1989 struct wrapper_priv_data { 1990 struct dwc2_hsotg *hsotg; 1991 }; 1992 1993 1994 void dwc2_host_start(struct dwc2_hsotg *hsotg) 1995 { 1996 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1997 1998 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 1999 _dwc2_hcd_start(hsotg); 2000 } 2001 2002 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2003 { 2004 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2005 2006 // hcd->self.is_b_host = 0; 2007 } 2008 2009 2010 /* 2011 * Work queue function for starting the HCD when A-Cable is connected 2012 */ 2013 void 2014 dwc2_hcd_start_func(struct work *work) 2015 { 2016 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2017 start_work.work); 2018 2019 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2020 dwc2_host_start(hsotg); 2021 } 2022 2023 /* 2024 * Reset work queue function 2025 */ 2026 void 2027 dwc2_hcd_reset_func(struct work *work) 2028 { 2029 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2030 reset_work.work); 2031 u32 hprt0; 2032 2033 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2034 hprt0 = dwc2_read_hprt0(hsotg); 2035 hprt0 &= ~HPRT0_RST; 2036 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2037 hsotg->flags.b.port_reset_change = 1; 2038 2039 dwc2_root_intr(hsotg->hsotg_sc); 2040 } 2041 2042 /* 2043 * ========================================================================= 2044 * Linux HC Driver Functions 2045 * ========================================================================= 2046 */ 2047 2048 /* 2049 * Initializes the DWC_otg controller and its root hub and prepares it for host 2050 * mode operation. Activates the root port. Returns 0 on success and a negative 2051 * error code on failure. 2052 */ 2053 2054 2055 /* 2056 * Frees secondary storage associated with the dwc2_hsotg structure contained 2057 * in the struct usb_hcd field 2058 */ 2059 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2060 { 2061 u32 ahbcfg; 2062 u32 dctl; 2063 int i; 2064 2065 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2066 2067 /* Free memory for QH/QTD lists */ 2068 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2069 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2070 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2071 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2072 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2073 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2074 2075 /* Free memory for the host channels */ 2076 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2077 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2078 2079 if (chan != NULL) { 2080 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2081 i, chan); 2082 hsotg->hc_ptr_array[i] = NULL; 2083 kmem_free(chan, sizeof(*chan)); 2084 } 2085 } 2086 2087 if (hsotg->core_params->dma_enable > 0) { 2088 if (hsotg->status_buf) { 2089 usb_freemem(&hsotg->hsotg_sc->sc_bus, 2090 &hsotg->status_buf_usbdma); 2091 hsotg->status_buf = NULL; 2092 } 2093 } else { 2094 kmem_free(hsotg->status_buf,DWC2_HCD_STATUS_BUF_SIZE); 2095 hsotg->status_buf = NULL; 2096 } 2097 2098 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2099 2100 /* Disable all interrupts */ 2101 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2102 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2103 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2104 2105 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2106 dctl = DWC2_READ_4(hsotg, DCTL); 2107 dctl |= DCTL_SFTDISCON; 2108 DWC2_WRITE_4(hsotg, DCTL, dctl); 2109 } 2110 2111 if (hsotg->wq_otg) { 2112 workqueue_destroy(hsotg->wq_otg); 2113 } 2114 2115 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2116 hsotg->core_params = NULL; 2117 callout_destroy(&hsotg->wkp_timer); 2118 } 2119 2120 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2121 { 2122 /* Turn off all host-specific interrupts */ 2123 dwc2_disable_host_interrupts(hsotg); 2124 2125 dwc2_hcd_free(hsotg); 2126 } 2127 2128 /* 2129 * Sets all parameters to the given value. 2130 * 2131 * Assumes that the dwc2_core_params struct contains only integers. 2132 */ 2133 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2134 { 2135 int *p = (int *)params; 2136 size_t size = sizeof(*params) / sizeof(*p); 2137 int i; 2138 2139 for (i = 0; i < size; i++) 2140 p[i] = value; 2141 } 2142 2143 /* 2144 * Initializes the HCD. This function allocates memory for and initializes the 2145 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2146 * USB bus with the core and calls the hc_driver->start() function. It returns 2147 * a negative error on failure. 2148 */ 2149 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, 2150 const struct dwc2_core_params *params) 2151 { 2152 struct dwc2_host_chan *channel; 2153 int i, num_channels; 2154 int err, retval; 2155 2156 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2157 2158 /* Detect config values from hardware */ 2159 retval = dwc2_get_hwparams(hsotg); 2160 2161 if (retval) 2162 return retval; 2163 2164 retval = -ENOMEM; 2165 2166 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG)); 2167 2168 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2169 hsotg->frame_num_array = kmem_zalloc(sizeof(*hsotg->frame_num_array) * 2170 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2171 if (!hsotg->frame_num_array) 2172 goto error1; 2173 hsotg->last_frame_num_array = kmem_zalloc( 2174 sizeof(*hsotg->last_frame_num_array) * 2175 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2176 if (!hsotg->last_frame_num_array) 2177 goto error1; 2178 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2179 #endif 2180 2181 hsotg->core_params = kmem_zalloc(sizeof(*hsotg->core_params), KM_SLEEP); 2182 if (!hsotg->core_params) 2183 goto error1; 2184 2185 dwc2_set_all_params(hsotg->core_params, -1); 2186 2187 /* Validate parameter values */ 2188 dwc2_set_parameters(hsotg, params); 2189 2190 spin_lock_init(&hsotg->lock); 2191 2192 /* 2193 * Disable the global interrupt until all the interrupt handlers are 2194 * installed 2195 */ 2196 dwc2_disable_global_interrupts(hsotg); 2197 2198 /* Initialize the DWC_otg core, and select the Phy type */ 2199 retval = dwc2_core_init(hsotg, true); 2200 if (retval) 2201 goto error2; 2202 2203 /* Create new workqueue and init work */ 2204 retval = -ENOMEM; 2205 err = workqueue_create(&hsotg->wq_otg, "dwc2", dwc2_worker, hsotg, 2206 PRI_BIO, IPL_USB, WQ_MPSAFE); 2207 2208 retval = -err; 2209 if (err) { 2210 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2211 goto error2; 2212 } 2213 2214 callout_init(&hsotg->wkp_timer, CALLOUT_MPSAFE); 2215 callout_setfunc(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2216 2217 /* Initialize the non-periodic schedule */ 2218 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2219 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2220 2221 /* Initialize the periodic schedule */ 2222 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2223 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2224 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2225 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2226 2227 /* 2228 * Create a host channel descriptor for each host channel implemented 2229 * in the controller. Initialize the channel descriptor array. 2230 */ 2231 INIT_LIST_HEAD(&hsotg->free_hc_list); 2232 num_channels = hsotg->core_params->host_channels; 2233 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2234 2235 for (i = 0; i < num_channels; i++) { 2236 channel = kmem_zalloc(sizeof(*channel), KM_SLEEP); 2237 if (channel == NULL) 2238 goto error3; 2239 channel->hc_num = i; 2240 hsotg->hc_ptr_array[i] = channel; 2241 } 2242 2243 if (hsotg->core_params->uframe_sched > 0) 2244 dwc2_hcd_init_usecs(hsotg); 2245 2246 /* Initialize hsotg start work */ 2247 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2248 2249 /* Initialize port reset work */ 2250 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2251 2252 /* 2253 * Allocate space for storing data on status transactions. Normally no 2254 * data is sent, but this space acts as a bit bucket. This must be 2255 * done after usb_add_hcd since that function allocates the DMA buffer 2256 * pool. 2257 */ 2258 hsotg->status_buf = NULL; 2259 if (hsotg->core_params->dma_enable > 0) { 2260 retval = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 2261 DWC2_HCD_STATUS_BUF_SIZE, 0, 2262 &hsotg->status_buf_usbdma); 2263 if (!retval) { 2264 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2265 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2266 } 2267 } else 2268 hsotg->status_buf = kmem_zalloc(DWC2_HCD_STATUS_BUF_SIZE, 2269 KM_SLEEP); 2270 2271 if (!hsotg->status_buf) 2272 goto error3; 2273 2274 hsotg->otg_port = 1; 2275 hsotg->frame_list = NULL; 2276 hsotg->frame_list_dma = 0; 2277 hsotg->periodic_qh_count = 0; 2278 2279 /* Initiate lx_state to L3 disconnected state */ 2280 hsotg->lx_state = DWC2_L3; 2281 2282 _dwc2_hcd_start(hsotg); 2283 2284 dwc2_hcd_dump_state(hsotg); 2285 2286 dwc2_enable_global_interrupts(hsotg); 2287 2288 return 0; 2289 2290 error3: 2291 dwc2_hcd_release(hsotg); 2292 error2: 2293 error1: 2294 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2295 2296 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2297 kmem_free(hsotg->last_frame_num_array, 2298 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2299 kmem_free(hsotg->frame_num_array, 2300 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2301 #endif 2302 2303 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2304 return retval; 2305 } 2306