1 /* $NetBSD: dwc2_coreintr.c,v 1.9 2015/08/30 12:59:59 skrll Exp $ */ 2 3 /* 4 * core_intr.c - DesignWare HS OTG Controller common interrupt handling 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the common interrupt handlers 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: dwc2_coreintr.c,v 1.9 2015/08/30 12:59:59 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/kernel.h> 48 #include <sys/mutex.h> 49 #include <sys/pool.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <linux/kernel.h> 59 #include <linux/list.h> 60 #include <linux/err.h> 61 62 #include <dwc2/dwc2.h> 63 #include <dwc2/dwc2var.h> 64 65 #include "dwc2_core.h" 66 #include "dwc2_hcd.h" 67 68 #ifdef DWC2_DEBUG 69 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) 70 { 71 switch (hsotg->op_state) { 72 case OTG_STATE_A_HOST: 73 return "a_host"; 74 case OTG_STATE_A_SUSPEND: 75 return "a_suspend"; 76 case OTG_STATE_A_PERIPHERAL: 77 return "a_peripheral"; 78 case OTG_STATE_B_PERIPHERAL: 79 return "b_peripheral"; 80 case OTG_STATE_B_HOST: 81 return "b_host"; 82 default: 83 return "unknown"; 84 } 85 } 86 #endif 87 88 /** 89 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. 90 * When the PRTINT interrupt fires, there are certain status bits in the Host 91 * Port that needs to get cleared. 92 * 93 * @hsotg: Programming view of DWC_otg controller 94 */ 95 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 96 { 97 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 98 99 if (hprt0 & HPRT0_ENACHG) { 100 hprt0 &= ~HPRT0_ENA; 101 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 102 } 103 104 /* Clear interrupt */ 105 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_PRTINT); 106 } 107 108 /** 109 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message 110 * 111 * @hsotg: Programming view of DWC_otg controller 112 */ 113 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 114 { 115 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 116 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 117 118 /* Clear interrupt */ 119 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_MODEMIS); 120 } 121 122 /** 123 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG 124 * Interrupt Register (GOTGINT) to determine what interrupt has occurred. 125 * 126 * @hsotg: Programming view of DWC_otg controller 127 */ 128 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) 129 { 130 u32 gotgint; 131 u32 gotgctl; 132 u32 gintmsk; 133 134 gotgint = DWC2_READ_4(hsotg, GOTGINT); 135 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 136 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 137 dwc2_op_state_str(hsotg)); 138 139 if (gotgint & GOTGINT_SES_END_DET) { 140 dev_dbg(hsotg->dev, 141 " ++OTG Interrupt: Session End Detected++ (%s)\n", 142 dwc2_op_state_str(hsotg)); 143 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 144 145 if (dwc2_is_device_mode(hsotg)) 146 s3c_hsotg_disconnect(hsotg); 147 148 if (hsotg->op_state == OTG_STATE_B_HOST) { 149 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 150 } else { 151 /* 152 * If not B_HOST and Device HNP still set, HNP did 153 * not succeed! 154 */ 155 if (gotgctl & GOTGCTL_DEVHNPEN) { 156 dev_dbg(hsotg->dev, "Session End Detected\n"); 157 dev_err(hsotg->dev, 158 "Device Not Connected/Responding!\n"); 159 } 160 161 /* 162 * If Session End Detected the B-Cable has been 163 * disconnected 164 */ 165 /* Reset to a clean state */ 166 hsotg->lx_state = DWC2_L0; 167 } 168 169 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 170 gotgctl &= ~GOTGCTL_DEVHNPEN; 171 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 172 } 173 174 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 175 dev_dbg(hsotg->dev, 176 " ++OTG Interrupt: Session Request Success Status Change++\n"); 177 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 178 if (gotgctl & GOTGCTL_SESREQSCS) { 179 if (hsotg->core_params->phy_type == 180 DWC2_PHY_TYPE_PARAM_FS 181 && hsotg->core_params->i2c_enable > 0) { 182 hsotg->srp_success = 1; 183 } else { 184 /* Clear Session Request */ 185 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 186 gotgctl &= ~GOTGCTL_SESREQ; 187 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 188 } 189 } 190 } 191 192 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { 193 /* 194 * Print statements during the HNP interrupt handling 195 * can cause it to fail 196 */ 197 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 198 /* 199 * WA for 3.00a- HW is not setting cur_mode, even sometimes 200 * this does not help 201 */ 202 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) 203 udelay(100); 204 if (gotgctl & GOTGCTL_HSTNEGSCS) { 205 if (dwc2_is_host_mode(hsotg)) { 206 hsotg->op_state = OTG_STATE_B_HOST; 207 /* 208 * Need to disable SOF interrupt immediately. 209 * When switching from device to host, the PCD 210 * interrupt handler won't handle the interrupt 211 * if host mode is already set. The HCD 212 * interrupt handler won't get called if the 213 * HCD state is HALT. This means that the 214 * interrupt does not get handled and Linux 215 * complains loudly. 216 */ 217 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 218 gintmsk &= ~GINTSTS_SOF; 219 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 220 221 /* 222 * Call callback function with spin lock 223 * released 224 */ 225 spin_unlock(&hsotg->lock); 226 227 /* Initialize the Core for Host mode */ 228 dwc2_hcd_start(hsotg); 229 spin_lock(&hsotg->lock); 230 hsotg->op_state = OTG_STATE_B_HOST; 231 } 232 } else { 233 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 234 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 235 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 236 dev_dbg(hsotg->dev, "HNP Failed\n"); 237 dev_err(hsotg->dev, 238 "Device Not Connected/Responding\n"); 239 } 240 } 241 242 if (gotgint & GOTGINT_HST_NEG_DET) { 243 /* 244 * The disconnect interrupt is set at the same time as 245 * Host Negotiation Detected. During the mode switch all 246 * interrupts are cleared so the disconnect interrupt 247 * handler will not get executed. 248 */ 249 dev_dbg(hsotg->dev, 250 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", 251 (dwc2_is_host_mode(hsotg) ? "Host" : "Device")); 252 if (dwc2_is_device_mode(hsotg)) { 253 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", 254 hsotg->op_state); 255 spin_unlock(&hsotg->lock); 256 dwc2_hcd_disconnect(hsotg); 257 spin_lock(&hsotg->lock); 258 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 259 } else { 260 /* Need to disable SOF interrupt immediately */ 261 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 262 gintmsk &= ~GINTSTS_SOF; 263 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 264 spin_unlock(&hsotg->lock); 265 dwc2_hcd_start(hsotg); 266 spin_lock(&hsotg->lock); 267 hsotg->op_state = OTG_STATE_A_HOST; 268 } 269 } 270 271 if (gotgint & GOTGINT_A_DEV_TOUT_CHG) 272 dev_dbg(hsotg->dev, 273 " ++OTG Interrupt: A-Device Timeout Change++\n"); 274 if (gotgint & GOTGINT_DBNCE_DONE) 275 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 276 277 /* Clear GOTGINT */ 278 DWC2_WRITE_4(hsotg, GOTGINT, gotgint); 279 } 280 281 /** 282 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status 283 * Change Interrupt 284 * 285 * @hsotg: Programming view of DWC_otg controller 286 * 287 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a 288 * Device to Host Mode transition or a Host to Device Mode transition. This only 289 * occurs when the cable is connected/removed from the PHY connector. 290 */ 291 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) 292 { 293 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 294 295 /* Need to disable SOF interrupt immediately */ 296 gintmsk &= ~GINTSTS_SOF; 297 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 298 299 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 300 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 301 302 /* 303 * Need to schedule a work, as there are possible DELAY function calls. 304 * Release lock before scheduling workq as it holds spinlock during 305 * scheduling. 306 */ 307 if (hsotg->wq_otg) { 308 spin_unlock(&hsotg->lock); 309 workqueue_enqueue(hsotg->wq_otg, &hsotg->wf_otg, NULL); 310 spin_lock(&hsotg->lock); 311 } 312 313 /* Clear interrupt */ 314 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_CONIDSTSCHNG); 315 } 316 317 /** 318 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is 319 * initiating the Session Request Protocol to request the host to turn on bus 320 * power so a new session can begin 321 * 322 * @hsotg: Programming view of DWC_otg controller 323 * 324 * This handler responds by turning on bus power. If the DWC_otg controller is 325 * in low power mode, this handler brings the controller out of low power mode 326 * before turning on bus power. 327 */ 328 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) 329 { 330 dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); 331 332 /* Clear interrupt */ 333 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SESSREQINT); 334 335 /* 336 * Report disconnect if there is any previous session established 337 */ 338 if (dwc2_is_device_mode(hsotg)) 339 s3c_hsotg_disconnect(hsotg); 340 } 341 342 /* 343 * This interrupt indicates that the DWC_otg controller has detected a 344 * resume or remote wakeup sequence. If the DWC_otg controller is in 345 * low power mode, the handler must brings the controller out of low 346 * power mode. The controller automatically begins resume signaling. 347 * The handler schedules a time to stop resume signaling. 348 */ 349 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) 350 { 351 int ret; 352 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 353 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 354 355 if (dwc2_is_device_mode(hsotg)) { 356 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", DWC2_READ_4(hsotg, DSTS)); 357 if (hsotg->lx_state == DWC2_L2) { 358 u32 dctl = DWC2_READ_4(hsotg, DCTL); 359 360 /* Clear Remote Wakeup Signaling */ 361 dctl &= ~DCTL_RMTWKUPSIG; 362 DWC2_WRITE_4(hsotg, DCTL, dctl); 363 ret = dwc2_exit_hibernation(hsotg, true); 364 if (ret && (ret != -ENOTSUPP)) 365 dev_err(hsotg->dev, "exit hibernation failed\n"); 366 367 call_gadget(hsotg, resume); 368 } 369 /* Change to L0 state */ 370 hsotg->lx_state = DWC2_L0; 371 } else { 372 if (hsotg->lx_state != DWC2_L1) { 373 u32 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 374 375 /* Restart the Phy Clock */ 376 pcgcctl &= ~PCGCTL_STOPPCLK; 377 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 378 callout_reset(&hsotg->wkp_timer, mstohz(71), 379 dwc2_wakeup_detected, hsotg); 380 } else { 381 /* Change to L0 state */ 382 hsotg->lx_state = DWC2_L0; 383 } 384 } 385 386 /* Clear interrupt */ 387 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_WKUPINT); 388 } 389 390 /* 391 * This interrupt indicates that a device has been disconnected from the 392 * root port 393 */ 394 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 395 { 396 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 397 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 398 dwc2_op_state_str(hsotg)); 399 400 if (hsotg->op_state == OTG_STATE_A_HOST) 401 dwc2_hcd_disconnect(hsotg); 402 403 /* Change to L3 (OFF) state */ 404 hsotg->lx_state = DWC2_L3; 405 406 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_DISCONNINT); 407 } 408 409 /* 410 * This interrupt indicates that SUSPEND state has been detected on the USB. 411 * 412 * For HNP the USB Suspend interrupt signals the change from "a_peripheral" 413 * to "a_host". 414 * 415 * When power management is enabled the core will be put in low power mode. 416 */ 417 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) 418 { 419 u32 dsts; 420 int ret; 421 422 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 423 424 if (dwc2_is_device_mode(hsotg)) { 425 /* 426 * Check the Device status register to determine if the Suspend 427 * state is active 428 */ 429 dsts = DWC2_READ_4(hsotg, DSTS); 430 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); 431 dev_dbg(hsotg->dev, 432 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", 433 !!(dsts & DSTS_SUSPSTS), 434 hsotg->hw_params.power_optimized); 435 if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) { 436 /* Ignore suspend request before enumeration */ 437 if (!dwc2_is_device_connected(hsotg)) { 438 dev_dbg(hsotg->dev, 439 "ignore suspend request before enumeration\n"); 440 goto clear_int; 441 } 442 443 ret = dwc2_enter_hibernation(hsotg); 444 if (ret) { 445 if (ret != -ENOTSUPP) 446 dev_err(hsotg->dev, 447 "enter hibernation failed\n"); 448 goto skip_power_saving; 449 } 450 451 udelay(100); 452 453 /* Ask phy to be suspended */ 454 if (!IS_ERR_OR_NULL(hsotg->uphy)) 455 usb_phy_set_suspend(hsotg->uphy, true); 456 skip_power_saving: 457 /* 458 * Change to L2 (suspend) state before releasing 459 * spinlock 460 */ 461 hsotg->lx_state = DWC2_L2; 462 463 /* Call gadget suspend callback */ 464 call_gadget(hsotg, suspend); 465 } 466 } else { 467 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { 468 dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); 469 470 /* Change to L2 (suspend) state */ 471 hsotg->lx_state = DWC2_L2; 472 /* Clear the a_peripheral flag, back to a_host */ 473 spin_unlock(&hsotg->lock); 474 dwc2_hcd_start(hsotg); 475 spin_lock(&hsotg->lock); 476 hsotg->op_state = OTG_STATE_A_HOST; 477 } 478 } 479 480 clear_int: 481 /* Clear interrupt */ 482 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_USBSUSP); 483 } 484 485 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ 486 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ 487 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ 488 GINTSTS_USBSUSP | GINTSTS_PRTINT) 489 490 /* 491 * This function returns the Core Interrupt register 492 */ 493 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) 494 { 495 u32 gintsts; 496 u32 gintmsk; 497 u32 gahbcfg; 498 u32 gintmsk_common = GINTMSK_COMMON; 499 500 gintsts = DWC2_READ_4(hsotg, GINTSTS); 501 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 502 gahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 503 504 /* If any common interrupts set */ 505 if (gintsts & gintmsk_common) 506 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", 507 gintsts, gintmsk); 508 509 if (gahbcfg & GAHBCFG_GLBL_INTR_EN) 510 return gintsts & gintmsk & gintmsk_common; 511 else 512 return 0; 513 } 514 515 /* 516 * Common interrupt handler 517 * 518 * The common interrupts are those that occur in both Host and Device mode. 519 * This handler handles the following interrupts: 520 * - Mode Mismatch Interrupt 521 * - OTG Interrupt 522 * - Connector ID Status Change Interrupt 523 * - Disconnect Interrupt 524 * - Session Request Interrupt 525 * - Resume / Remote Wakeup Detected Interrupt 526 * - Suspend Interrupt 527 */ 528 irqreturn_t dwc2_handle_common_intr(void *dev) 529 { 530 struct dwc2_hsotg *hsotg = dev; 531 u32 gintsts; 532 irqreturn_t retval = IRQ_NONE; 533 534 if (!dwc2_is_controller_alive(hsotg)) { 535 dev_warn(hsotg->dev, "Controller is dead\n"); 536 goto out; 537 } 538 539 KASSERT(mutex_owned(&hsotg->lock)); 540 541 gintsts = dwc2_read_common_intr(hsotg); 542 if (gintsts & ~GINTSTS_PRTINT) 543 retval = IRQ_HANDLED; 544 545 if (gintsts & GINTSTS_MODEMIS) 546 dwc2_handle_mode_mismatch_intr(hsotg); 547 if (gintsts & GINTSTS_OTGINT) 548 dwc2_handle_otg_intr(hsotg); 549 if (gintsts & GINTSTS_CONIDSTSCHNG) 550 dwc2_handle_conn_id_status_change_intr(hsotg); 551 if (gintsts & GINTSTS_DISCONNINT) 552 dwc2_handle_disconnect_intr(hsotg); 553 if (gintsts & GINTSTS_SESSREQINT) 554 dwc2_handle_session_req_intr(hsotg); 555 if (gintsts & GINTSTS_WKUPINT) 556 dwc2_handle_wakeup_detected_intr(hsotg); 557 if (gintsts & GINTSTS_USBSUSP) 558 dwc2_handle_usb_suspend_intr(hsotg); 559 560 if (gintsts & GINTSTS_PRTINT) { 561 /* 562 * The port interrupt occurs while in device mode with HPRT0 563 * Port Enable/Disable 564 */ 565 if (dwc2_is_device_mode(hsotg)) { 566 dev_dbg(hsotg->dev, 567 " --Port interrupt received in Device mode--\n"); 568 dwc2_handle_usb_port_intr(hsotg); 569 retval = IRQ_HANDLED; 570 } 571 } 572 573 out: 574 return retval; 575 } 576