1 /* $NetBSD: dwc2_core.c,v 1.4 2013/10/05 06:51:43 skrll Exp $ */ 2 3 /* 4 * core.c - DesignWare HS OTG Controller common routines 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The Core code provides basic services for accessing and managing the 41 * DWC_otg hardware. These services are used by both the Host Controller 42 * Driver and the Peripheral Controller Driver. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.4 2013/10/05 06:51:43 skrll Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/bus.h> 50 #include <sys/proc.h> 51 #include <sys/callout.h> 52 #include <sys/mutex.h> 53 #include <sys/pool.h> 54 #include <sys/workqueue.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usb_mem.h> 60 61 #include <linux/kernel.h> 62 #include <linux/list.h> 63 64 #include <dwc2/dwc2.h> 65 #include <dwc2/dwc2var.h> 66 67 #include "dwc2_core.h" 68 #include "dwc2_hcd.h" 69 70 /** 71 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 72 * used in both device and host modes 73 * 74 * @hsotg: Programming view of the DWC_otg controller 75 */ 76 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 77 { 78 u32 intmsk; 79 80 /* Clear any pending OTG Interrupts */ 81 DWC2_WRITE_4(hsotg, GOTGINT, 0xffffffff); 82 83 /* Clear any pending interrupts */ 84 DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); 85 86 /* Enable the interrupts in the GINTMSK */ 87 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 88 89 if (hsotg->core_params->dma_enable <= 0) 90 intmsk |= GINTSTS_RXFLVL; 91 92 intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP | 93 GINTSTS_SESSREQINT; 94 95 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 96 } 97 98 /* 99 * Initializes the FSLSPClkSel field of the HCFG register depending on the 100 * PHY type 101 */ 102 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 103 { 104 u32 hcfg, val; 105 106 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 107 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 108 hsotg->core_params->ulpi_fs_ls > 0) || 109 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 110 /* Full speed PHY */ 111 val = HCFG_FSLSPCLKSEL_48_MHZ; 112 } else { 113 /* High speed PHY running at full speed or high speed */ 114 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 115 } 116 117 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 118 hcfg = DWC2_READ_4(hsotg, HCFG); 119 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 120 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 121 DWC2_WRITE_4(hsotg, HCFG, hcfg); 122 } 123 124 /* 125 * Do core a soft reset of the core. Be careful with this because it 126 * resets all the internal state machines of the core. 127 */ 128 static void dwc2_core_reset(struct dwc2_hsotg *hsotg) 129 { 130 u32 greset; 131 int count = 0; 132 133 dev_vdbg(hsotg->dev, "%s()\n", __func__); 134 135 /* Wait for AHB master IDLE state */ 136 do { 137 usleep_range(20000, 40000); 138 greset = DWC2_READ_4(hsotg, GRSTCTL); 139 if (++count > 50) { 140 dev_warn(hsotg->dev, 141 "%s() HANG! AHB Idle GRSTCTL=%0x\n", 142 __func__, greset); 143 return; 144 } 145 } while (!(greset & GRSTCTL_AHBIDLE)); 146 147 /* Core Soft Reset */ 148 count = 0; 149 greset |= GRSTCTL_CSFTRST; 150 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 151 do { 152 usleep_range(20000, 40000); 153 greset = DWC2_READ_4(hsotg, GRSTCTL); 154 if (++count > 50) { 155 dev_warn(hsotg->dev, 156 "%s() HANG! Soft Reset GRSTCTL=%0x\n", 157 __func__, greset); 158 break; 159 } 160 } while (greset & GRSTCTL_CSFTRST); 161 162 /* 163 * NOTE: This long sleep is _very_ important, otherwise the core will 164 * not stay in host mode after a connector ID change! 165 */ 166 usleep_range(150000, 200000); 167 } 168 169 static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 170 { 171 u32 usbcfg, i2cctl; 172 173 /* 174 * core_init() is now called on every switch so only call the 175 * following for the first time through 176 */ 177 if (select_phy) { 178 dev_dbg(hsotg->dev, "FS PHY selected\n"); 179 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 180 usbcfg |= GUSBCFG_PHYSEL; 181 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 182 183 /* Reset after a PHY select */ 184 dwc2_core_reset(hsotg); 185 } 186 187 /* 188 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 189 * do this on HNP Dev/Host mode switches (done in dev_init and 190 * host_init). 191 */ 192 if (dwc2_is_host_mode(hsotg)) 193 dwc2_init_fs_ls_pclk_sel(hsotg); 194 195 if (hsotg->core_params->i2c_enable > 0) { 196 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 197 198 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 199 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 200 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 201 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 202 203 /* Program GI2CCTL.I2CEn */ 204 i2cctl = DWC2_READ_4(hsotg, GI2CCTL); 205 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 206 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 207 i2cctl &= ~GI2CCTL_I2CEN; 208 DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); 209 i2cctl |= GI2CCTL_I2CEN; 210 DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); 211 } 212 } 213 214 static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 215 { 216 u32 usbcfg; 217 218 if (!select_phy) 219 return; 220 221 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 222 223 /* 224 * HS PHY parameters. These parameters are preserved during soft reset 225 * so only program the first time. Do a soft reset immediately after 226 * setting phyif. 227 */ 228 switch (hsotg->core_params->phy_type) { 229 case DWC2_PHY_TYPE_PARAM_ULPI: 230 /* ULPI interface */ 231 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 232 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 233 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 234 if (hsotg->core_params->phy_ulpi_ddr > 0) 235 usbcfg |= GUSBCFG_DDRSEL; 236 break; 237 case DWC2_PHY_TYPE_PARAM_UTMI: 238 /* UTMI+ interface */ 239 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 240 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 241 if (hsotg->core_params->phy_utmi_width == 16) 242 usbcfg |= GUSBCFG_PHYIF16; 243 break; 244 default: 245 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 246 break; 247 } 248 249 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 250 251 /* Reset after setting the PHY parameters */ 252 dwc2_core_reset(hsotg); 253 } 254 255 static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 256 { 257 u32 usbcfg; 258 259 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && 260 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 261 /* If FS mode with FS PHY */ 262 dwc2_fs_phy_init(hsotg, select_phy); 263 } else { 264 /* High speed PHY */ 265 dwc2_hs_phy_init(hsotg, select_phy); 266 } 267 268 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 269 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 270 hsotg->core_params->ulpi_fs_ls > 0) { 271 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 272 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 273 usbcfg |= GUSBCFG_ULPI_FS_LS; 274 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 275 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 276 } else { 277 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 278 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 279 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 280 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 281 } 282 } 283 284 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 285 { 286 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 287 288 switch (hsotg->hw_params.arch) { 289 case GHWCFG2_EXT_DMA_ARCH: 290 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 291 return -EINVAL; 292 293 case GHWCFG2_INT_DMA_ARCH: 294 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 295 if (hsotg->core_params->ahbcfg != -1) { 296 ahbcfg &= GAHBCFG_CTRL_MASK; 297 ahbcfg |= hsotg->core_params->ahbcfg & 298 ~GAHBCFG_CTRL_MASK; 299 } 300 break; 301 302 case GHWCFG2_SLAVE_ONLY_ARCH: 303 default: 304 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 305 break; 306 } 307 308 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", 309 hsotg->core_params->dma_enable, 310 hsotg->core_params->dma_desc_enable); 311 312 if (hsotg->core_params->dma_enable > 0) { 313 if (hsotg->core_params->dma_desc_enable > 0) 314 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 315 else 316 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 317 } else { 318 dev_dbg(hsotg->dev, "Using Slave mode\n"); 319 hsotg->core_params->dma_desc_enable = 0; 320 } 321 322 if (hsotg->core_params->dma_enable > 0) 323 ahbcfg |= GAHBCFG_DMA_EN; 324 325 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 326 327 return 0; 328 } 329 330 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 331 { 332 u32 usbcfg; 333 334 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 335 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 336 337 switch (hsotg->hw_params.op_mode) { 338 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 339 if (hsotg->core_params->otg_cap == 340 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 341 usbcfg |= GUSBCFG_HNPCAP; 342 if (hsotg->core_params->otg_cap != 343 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 344 usbcfg |= GUSBCFG_SRPCAP; 345 break; 346 347 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 348 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 349 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 350 if (hsotg->core_params->otg_cap != 351 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 352 usbcfg |= GUSBCFG_SRPCAP; 353 break; 354 355 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 356 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 357 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 358 default: 359 break; 360 } 361 362 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 363 } 364 365 /** 366 * dwc2_core_init() - Initializes the DWC_otg controller registers and 367 * prepares the core for device mode or host mode operation 368 * 369 * @hsotg: Programming view of the DWC_otg controller 370 * @select_phy: If true then also set the Phy type 371 * @irq: If >= 0, the irq to register 372 */ 373 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy) 374 { 375 u32 usbcfg, otgctl; 376 int retval; 377 378 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 379 380 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 381 382 /* Set ULPI External VBUS bit if needed */ 383 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 384 if (hsotg->core_params->phy_ulpi_ext_vbus == 385 DWC2_PHY_ULPI_EXTERNAL_VBUS) 386 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 387 388 /* Set external TS Dline pulsing bit if needed */ 389 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 390 if (hsotg->core_params->ts_dline > 0) 391 usbcfg |= GUSBCFG_TERMSELDLPULSE; 392 393 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 394 395 /* Reset the Controller */ 396 dwc2_core_reset(hsotg); 397 398 /* 399 * This needs to happen in FS mode before any other programming occurs 400 */ 401 dwc2_phy_init(hsotg, select_phy); 402 403 /* Program the GAHBCFG Register */ 404 retval = dwc2_gahbcfg_init(hsotg); 405 if (retval) 406 return retval; 407 408 /* Program the GUSBCFG register */ 409 dwc2_gusbcfg_init(hsotg); 410 411 /* Program the GOTGCTL register */ 412 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 413 otgctl &= ~GOTGCTL_OTGVER; 414 if (hsotg->core_params->otg_ver > 0) 415 otgctl |= GOTGCTL_OTGVER; 416 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 417 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); 418 419 /* Clear the SRP success bit for FS-I2c */ 420 hsotg->srp_success = 0; 421 422 /* Enable common interrupts */ 423 dwc2_enable_common_interrupts(hsotg); 424 425 /* 426 * Do device or host intialization based on mode during PCD and 427 * HCD initialization 428 */ 429 if (dwc2_is_host_mode(hsotg)) { 430 dev_dbg(hsotg->dev, "Host Mode\n"); 431 hsotg->op_state = OTG_STATE_A_HOST; 432 } else { 433 dev_dbg(hsotg->dev, "Device Mode\n"); 434 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 435 } 436 437 return 0; 438 } 439 440 /** 441 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 442 * 443 * @hsotg: Programming view of DWC_otg controller 444 */ 445 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 446 { 447 u32 intmsk; 448 449 dev_dbg(hsotg->dev, "%s()\n", __func__); 450 451 /* Disable all interrupts */ 452 DWC2_WRITE_4(hsotg, GINTMSK, 0); 453 DWC2_WRITE_4(hsotg, HAINTMSK, 0); 454 455 /* Clear any pending interrupts */ 456 DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); 457 458 /* Enable the common interrupts */ 459 dwc2_enable_common_interrupts(hsotg); 460 461 /* Enable host mode interrupts without disturbing common interrupts */ 462 intmsk = DWC2_READ_4(hsotg, GINTMSK); 463 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 464 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 465 } 466 467 /** 468 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 469 * 470 * @hsotg: Programming view of DWC_otg controller 471 */ 472 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 473 { 474 u32 intmsk = DWC2_READ_4(hsotg, GINTMSK); 475 476 /* Disable host mode interrupts without disturbing common interrupts */ 477 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 478 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 479 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 480 } 481 482 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 483 { 484 struct dwc2_core_params *params = hsotg->core_params; 485 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 486 487 if (!params->enable_dynamic_fifo) 488 return; 489 490 /* Rx FIFO */ 491 grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 492 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 493 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 494 grxfsiz |= params->host_rx_fifo_size << 495 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 496 DWC2_WRITE_4(hsotg, GRXFSIZ, grxfsiz); 497 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", DWC2_READ_4(hsotg, GRXFSIZ)); 498 499 /* Non-periodic Tx FIFO */ 500 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 501 DWC2_READ_4(hsotg, GNPTXFSIZ)); 502 nptxfsiz = params->host_nperio_tx_fifo_size << 503 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 504 nptxfsiz |= params->host_rx_fifo_size << 505 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 506 DWC2_WRITE_4(hsotg, GNPTXFSIZ, nptxfsiz); 507 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 508 DWC2_READ_4(hsotg, GNPTXFSIZ)); 509 510 /* Periodic Tx FIFO */ 511 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 512 DWC2_READ_4(hsotg, HPTXFSIZ)); 513 hptxfsiz = params->host_perio_tx_fifo_size << 514 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 515 hptxfsiz |= (params->host_rx_fifo_size + 516 params->host_nperio_tx_fifo_size) << 517 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 518 DWC2_WRITE_4(hsotg, HPTXFSIZ, hptxfsiz); 519 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 520 DWC2_READ_4(hsotg, HPTXFSIZ)); 521 522 if (hsotg->core_params->en_multiple_tx_fifo > 0 && 523 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 524 /* 525 * Global DFIFOCFG calculation for Host mode - 526 * include RxFIFO, NPTXFIFO and HPTXFIFO 527 */ 528 dfifocfg = DWC2_READ_4(hsotg, GDFIFOCFG); 529 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 530 dfifocfg |= (params->host_rx_fifo_size + 531 params->host_nperio_tx_fifo_size + 532 params->host_perio_tx_fifo_size) << 533 GDFIFOCFG_EPINFOBASE_SHIFT & 534 GDFIFOCFG_EPINFOBASE_MASK; 535 DWC2_WRITE_4(hsotg, GDFIFOCFG, dfifocfg); 536 } 537 } 538 539 /** 540 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 541 * Host mode 542 * 543 * @hsotg: Programming view of DWC_otg controller 544 * 545 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 546 * request queues. Host channels are reset to ensure that they are ready for 547 * performing transfers. 548 */ 549 void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 550 { 551 u32 hcfg, hfir, otgctl; 552 553 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 554 555 /* Restart the Phy Clock */ 556 DWC2_WRITE_4(hsotg, PCGCTL, 0); 557 558 /* Initialize Host Configuration Register */ 559 dwc2_init_fs_ls_pclk_sel(hsotg); 560 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { 561 hcfg = DWC2_READ_4(hsotg, HCFG); 562 hcfg |= HCFG_FSLSSUPP; 563 DWC2_WRITE_4(hsotg, HCFG, hcfg); 564 } 565 566 /* 567 * This bit allows dynamic reloading of the HFIR register during 568 * runtime. This bit needs to be programmed during initial configuration 569 * and its value must not be changed during runtime. 570 */ 571 if (hsotg->core_params->reload_ctl > 0) { 572 hfir = DWC2_READ_4(hsotg, HFIR); 573 hfir |= HFIR_RLDCTRL; 574 DWC2_WRITE_4(hsotg, HFIR, hfir); 575 } 576 577 if (hsotg->core_params->dma_desc_enable > 0) { 578 u32 op_mode = hsotg->hw_params.op_mode; 579 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 580 !hsotg->hw_params.dma_desc_enable || 581 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 582 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 583 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 584 dev_err(hsotg->dev, 585 "Hardware does not support descriptor DMA mode -\n"); 586 dev_err(hsotg->dev, 587 "falling back to buffer DMA mode.\n"); 588 hsotg->core_params->dma_desc_enable = 0; 589 } else { 590 hcfg = DWC2_READ_4(hsotg, HCFG); 591 hcfg |= HCFG_DESCDMA; 592 DWC2_WRITE_4(hsotg, HCFG, hcfg); 593 } 594 } 595 596 /* Configure data FIFO sizes */ 597 dwc2_config_fifos(hsotg); 598 599 /* TODO - check this */ 600 /* Clear Host Set HNP Enable in the OTG Control Register */ 601 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 602 otgctl &= ~GOTGCTL_HSTSETHNPEN; 603 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 604 605 /* Make sure the FIFOs are flushed */ 606 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 607 dwc2_flush_rx_fifo(hsotg); 608 609 /* Clear Host Set HNP Enable in the OTG Control Register */ 610 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 611 otgctl &= ~GOTGCTL_HSTSETHNPEN; 612 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 613 614 if (hsotg->core_params->dma_desc_enable <= 0) { 615 int num_channels, i; 616 u32 hcchar; 617 618 /* Flush out any leftover queued requests */ 619 num_channels = hsotg->core_params->host_channels; 620 for (i = 0; i < num_channels; i++) { 621 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 622 hcchar &= ~HCCHAR_CHENA; 623 hcchar |= HCCHAR_CHDIS; 624 hcchar &= ~HCCHAR_EPDIR; 625 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 626 } 627 628 /* Halt all channels to put them into a known state */ 629 for (i = 0; i < num_channels; i++) { 630 int count = 0; 631 632 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 633 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 634 hcchar &= ~HCCHAR_EPDIR; 635 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 636 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 637 __func__, i); 638 do { 639 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 640 if (++count > 1000) { 641 dev_err(hsotg->dev, 642 "Unable to clear enable on channel %d\n", 643 i); 644 break; 645 } 646 udelay(1); 647 } while (hcchar & HCCHAR_CHENA); 648 } 649 } 650 651 /* Turn on the vbus power */ 652 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 653 if (hsotg->op_state == OTG_STATE_A_HOST) { 654 u32 hprt0 = dwc2_read_hprt0(hsotg); 655 656 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 657 !!(hprt0 & HPRT0_PWR)); 658 if (!(hprt0 & HPRT0_PWR)) { 659 hprt0 |= HPRT0_PWR; 660 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 661 } 662 } 663 664 dwc2_enable_host_interrupts(hsotg); 665 } 666 667 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 668 struct dwc2_host_chan *chan) 669 { 670 u32 hcintmsk = HCINTMSK_CHHLTD; 671 672 switch (chan->ep_type) { 673 case USB_ENDPOINT_XFER_CONTROL: 674 case USB_ENDPOINT_XFER_BULK: 675 dev_vdbg(hsotg->dev, "control/bulk\n"); 676 hcintmsk |= HCINTMSK_XFERCOMPL; 677 hcintmsk |= HCINTMSK_STALL; 678 hcintmsk |= HCINTMSK_XACTERR; 679 hcintmsk |= HCINTMSK_DATATGLERR; 680 if (chan->ep_is_in) { 681 hcintmsk |= HCINTMSK_BBLERR; 682 } else { 683 hcintmsk |= HCINTMSK_NAK; 684 hcintmsk |= HCINTMSK_NYET; 685 if (chan->do_ping) 686 hcintmsk |= HCINTMSK_ACK; 687 } 688 689 if (chan->do_split) { 690 hcintmsk |= HCINTMSK_NAK; 691 if (chan->complete_split) 692 hcintmsk |= HCINTMSK_NYET; 693 else 694 hcintmsk |= HCINTMSK_ACK; 695 } 696 697 if (chan->error_state) 698 hcintmsk |= HCINTMSK_ACK; 699 break; 700 701 case USB_ENDPOINT_XFER_INT: 702 if (dbg_perio()) 703 dev_vdbg(hsotg->dev, "intr\n"); 704 hcintmsk |= HCINTMSK_XFERCOMPL; 705 hcintmsk |= HCINTMSK_NAK; 706 hcintmsk |= HCINTMSK_STALL; 707 hcintmsk |= HCINTMSK_XACTERR; 708 hcintmsk |= HCINTMSK_DATATGLERR; 709 hcintmsk |= HCINTMSK_FRMOVRUN; 710 711 if (chan->ep_is_in) 712 hcintmsk |= HCINTMSK_BBLERR; 713 if (chan->error_state) 714 hcintmsk |= HCINTMSK_ACK; 715 if (chan->do_split) { 716 if (chan->complete_split) 717 hcintmsk |= HCINTMSK_NYET; 718 else 719 hcintmsk |= HCINTMSK_ACK; 720 } 721 break; 722 723 case USB_ENDPOINT_XFER_ISOC: 724 if (dbg_perio()) 725 dev_vdbg(hsotg->dev, "isoc\n"); 726 hcintmsk |= HCINTMSK_XFERCOMPL; 727 hcintmsk |= HCINTMSK_FRMOVRUN; 728 hcintmsk |= HCINTMSK_ACK; 729 730 if (chan->ep_is_in) { 731 hcintmsk |= HCINTMSK_XACTERR; 732 hcintmsk |= HCINTMSK_BBLERR; 733 } 734 break; 735 default: 736 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 737 break; 738 } 739 740 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 741 if (dbg_hc(chan)) 742 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 743 } 744 745 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 746 struct dwc2_host_chan *chan) 747 { 748 u32 hcintmsk = HCINTMSK_CHHLTD; 749 750 /* 751 * For Descriptor DMA mode core halts the channel on AHB error. 752 * Interrupt is not required. 753 */ 754 if (hsotg->core_params->dma_desc_enable <= 0) { 755 if (dbg_hc(chan)) 756 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 757 hcintmsk |= HCINTMSK_AHBERR; 758 } else { 759 if (dbg_hc(chan)) 760 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 761 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 762 hcintmsk |= HCINTMSK_XFERCOMPL; 763 } 764 765 if (chan->error_state && !chan->do_split && 766 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 767 if (dbg_hc(chan)) 768 dev_vdbg(hsotg->dev, "setting ACK\n"); 769 hcintmsk |= HCINTMSK_ACK; 770 if (chan->ep_is_in) { 771 hcintmsk |= HCINTMSK_DATATGLERR; 772 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 773 hcintmsk |= HCINTMSK_NAK; 774 } 775 } 776 777 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 778 if (dbg_hc(chan)) 779 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 780 } 781 782 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 783 struct dwc2_host_chan *chan) 784 { 785 u32 intmsk; 786 787 if (hsotg->core_params->dma_enable > 0) { 788 if (dbg_hc(chan)) 789 dev_vdbg(hsotg->dev, "DMA enabled\n"); 790 dwc2_hc_enable_dma_ints(hsotg, chan); 791 } else { 792 if (dbg_hc(chan)) 793 dev_vdbg(hsotg->dev, "DMA disabled\n"); 794 dwc2_hc_enable_slave_ints(hsotg, chan); 795 } 796 797 /* Enable the top level host channel interrupt */ 798 intmsk = DWC2_READ_4(hsotg, HAINTMSK); 799 intmsk |= 1 << chan->hc_num; 800 DWC2_WRITE_4(hsotg, HAINTMSK, intmsk); 801 if (dbg_hc(chan)) 802 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 803 804 /* Make sure host channel interrupts are enabled */ 805 intmsk = DWC2_READ_4(hsotg, GINTMSK); 806 intmsk |= GINTSTS_HCHINT; 807 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 808 if (dbg_hc(chan)) 809 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 810 } 811 812 /** 813 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 814 * a specific endpoint 815 * 816 * @hsotg: Programming view of DWC_otg controller 817 * @chan: Information needed to initialize the host channel 818 * 819 * The HCCHARn register is set up with the characteristics specified in chan. 820 * Host channel interrupts that may need to be serviced while this transfer is 821 * in progress are enabled. 822 */ 823 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 824 { 825 u8 hc_num = chan->hc_num; 826 u32 hcintmsk; 827 u32 hcchar; 828 u32 hcsplt = 0; 829 830 if (dbg_hc(chan)) 831 dev_vdbg(hsotg->dev, "%s()\n", __func__); 832 833 /* Clear old interrupt conditions for this host channel */ 834 hcintmsk = 0xffffffff; 835 hcintmsk &= ~HCINTMSK_RESERVED14_31; 836 DWC2_WRITE_4(hsotg, HCINT(hc_num), hcintmsk); 837 838 /* Enable channel interrupts required for this transfer */ 839 dwc2_hc_enable_ints(hsotg, chan); 840 841 /* 842 * Program the HCCHARn register with the endpoint characteristics for 843 * the current transfer 844 */ 845 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 846 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 847 if (chan->ep_is_in) 848 hcchar |= HCCHAR_EPDIR; 849 if (chan->speed == USB_SPEED_LOW) 850 hcchar |= HCCHAR_LSPDDEV; 851 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 852 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 853 DWC2_WRITE_4(hsotg, HCCHAR(hc_num), hcchar); 854 if (dbg_hc(chan)) { 855 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 856 hc_num, hcchar); 857 858 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 859 __func__, hc_num); 860 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 861 chan->dev_addr); 862 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 863 chan->ep_num); 864 dev_vdbg(hsotg->dev, " Is In: %d\n", 865 chan->ep_is_in); 866 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 867 chan->speed == USB_SPEED_LOW); 868 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 869 chan->ep_type); 870 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 871 chan->max_packet); 872 } 873 874 /* Program the HCSPLT register for SPLITs */ 875 if (chan->do_split) { 876 if (dbg_hc(chan)) 877 dev_vdbg(hsotg->dev, 878 "Programming HC %d with split --> %s\n", 879 hc_num, 880 chan->complete_split ? "CSPLIT" : "SSPLIT"); 881 if (chan->complete_split) 882 hcsplt |= HCSPLT_COMPSPLT; 883 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 884 HCSPLT_XACTPOS_MASK; 885 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 886 HCSPLT_HUBADDR_MASK; 887 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 888 HCSPLT_PRTADDR_MASK; 889 if (dbg_hc(chan)) { 890 dev_vdbg(hsotg->dev, " comp split %d\n", 891 chan->complete_split); 892 dev_vdbg(hsotg->dev, " xact pos %d\n", 893 chan->xact_pos); 894 dev_vdbg(hsotg->dev, " hub addr %d\n", 895 chan->hub_addr); 896 dev_vdbg(hsotg->dev, " hub port %d\n", 897 chan->hub_port); 898 dev_vdbg(hsotg->dev, " is_in %d\n", 899 chan->ep_is_in); 900 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 901 chan->max_packet); 902 dev_vdbg(hsotg->dev, " xferlen %d\n", 903 chan->xfer_len); 904 } 905 } 906 907 DWC2_WRITE_4(hsotg, HCSPLT(hc_num), hcsplt); 908 } 909 910 /** 911 * dwc2_hc_halt() - Attempts to halt a host channel 912 * 913 * @hsotg: Controller register interface 914 * @chan: Host channel to halt 915 * @halt_status: Reason for halting the channel 916 * 917 * This function should only be called in Slave mode or to abort a transfer in 918 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 919 * controller halts the channel when the transfer is complete or a condition 920 * occurs that requires application intervention. 921 * 922 * In slave mode, checks for a free request queue entry, then sets the Channel 923 * Enable and Channel Disable bits of the Host Channel Characteristics 924 * register of the specified channel to intiate the halt. If there is no free 925 * request queue entry, sets only the Channel Disable bit of the HCCHARn 926 * register to flush requests for this channel. In the latter case, sets a 927 * flag to indicate that the host channel needs to be halted when a request 928 * queue slot is open. 929 * 930 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 931 * HCCHARn register. The controller ensures there is space in the request 932 * queue before submitting the halt request. 933 * 934 * Some time may elapse before the core flushes any posted requests for this 935 * host channel and halts. The Channel Halted interrupt handler completes the 936 * deactivation of the host channel. 937 */ 938 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 939 enum dwc2_halt_status halt_status) 940 { 941 u32 nptxsts, hptxsts, hcchar; 942 943 if (dbg_hc(chan)) 944 dev_vdbg(hsotg->dev, "%s()\n", __func__); 945 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 946 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 947 948 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 949 halt_status == DWC2_HC_XFER_AHB_ERR) { 950 /* 951 * Disable all channel interrupts except Ch Halted. The QTD 952 * and QH state associated with this transfer has been cleared 953 * (in the case of URB_DEQUEUE), so the channel needs to be 954 * shut down carefully to prevent crashes. 955 */ 956 u32 hcintmsk = HCINTMSK_CHHLTD; 957 958 dev_vdbg(hsotg->dev, "dequeue/error\n"); 959 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 960 961 /* 962 * Make sure no other interrupts besides halt are currently 963 * pending. Handling another interrupt could cause a crash due 964 * to the QTD and QH state. 965 */ 966 DWC2_WRITE_4(hsotg, HCINT(chan->hc_num), ~hcintmsk); 967 968 /* 969 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 970 * even if the channel was already halted for some other 971 * reason 972 */ 973 chan->halt_status = halt_status; 974 975 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 976 if (!(hcchar & HCCHAR_CHENA)) { 977 /* 978 * The channel is either already halted or it hasn't 979 * started yet. In DMA mode, the transfer may halt if 980 * it finishes normally or a condition occurs that 981 * requires driver intervention. Don't want to halt 982 * the channel again. In either Slave or DMA mode, 983 * it's possible that the transfer has been assigned 984 * to a channel, but not started yet when an URB is 985 * dequeued. Don't want to halt a channel that hasn't 986 * started yet. 987 */ 988 return; 989 } 990 } 991 if (chan->halt_pending) { 992 /* 993 * A halt has already been issued for this channel. This might 994 * happen when a transfer is aborted by a higher level in 995 * the stack. 996 */ 997 dev_vdbg(hsotg->dev, 998 "*** %s: Channel %d, chan->halt_pending already set ***\n", 999 __func__, chan->hc_num); 1000 return; 1001 } 1002 1003 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1004 1005 /* No need to set the bit in DDMA for disabling the channel */ 1006 /* TODO check it everywhere channel is disabled */ 1007 if (hsotg->core_params->dma_desc_enable <= 0) { 1008 if (dbg_hc(chan)) 1009 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1010 hcchar |= HCCHAR_CHENA; 1011 } else { 1012 if (dbg_hc(chan)) 1013 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1014 } 1015 hcchar |= HCCHAR_CHDIS; 1016 1017 if (hsotg->core_params->dma_enable <= 0) { 1018 if (dbg_hc(chan)) 1019 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1020 hcchar |= HCCHAR_CHENA; 1021 1022 /* Check for space in the request queue to issue the halt */ 1023 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1024 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1025 dev_vdbg(hsotg->dev, "control/bulk\n"); 1026 nptxsts = DWC2_READ_4(hsotg, GNPTXSTS); 1027 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1028 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1029 hcchar &= ~HCCHAR_CHENA; 1030 } 1031 } else { 1032 if (dbg_perio()) 1033 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1034 hptxsts = DWC2_READ_4(hsotg, HPTXSTS); 1035 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1036 hsotg->queuing_high_bandwidth) { 1037 if (dbg_perio()) 1038 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1039 hcchar &= ~HCCHAR_CHENA; 1040 } 1041 } 1042 } else { 1043 if (dbg_hc(chan)) 1044 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1045 } 1046 1047 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1048 chan->halt_status = halt_status; 1049 1050 if (hcchar & HCCHAR_CHENA) { 1051 if (dbg_hc(chan)) 1052 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1053 chan->halt_pending = 1; 1054 chan->halt_on_queue = 0; 1055 } else { 1056 if (dbg_hc(chan)) 1057 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1058 chan->halt_on_queue = 1; 1059 } 1060 1061 if (dbg_hc(chan)) { 1062 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1063 chan->hc_num); 1064 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1065 hcchar); 1066 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1067 chan->halt_pending); 1068 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1069 chan->halt_on_queue); 1070 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1071 chan->halt_status); 1072 } 1073 } 1074 1075 /** 1076 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1077 * 1078 * @hsotg: Programming view of DWC_otg controller 1079 * @chan: Identifies the host channel to clean up 1080 * 1081 * This function is normally called after a transfer is done and the host 1082 * channel is being released 1083 */ 1084 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1085 { 1086 u32 hcintmsk; 1087 1088 chan->xfer_started = 0; 1089 1090 /* 1091 * Clear channel interrupt enables and any unhandled channel interrupt 1092 * conditions 1093 */ 1094 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), 0); 1095 hcintmsk = 0xffffffff; 1096 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1097 DWC2_WRITE_4(hsotg, HCINT(chan->hc_num), hcintmsk); 1098 } 1099 1100 /** 1101 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1102 * which frame a periodic transfer should occur 1103 * 1104 * @hsotg: Programming view of DWC_otg controller 1105 * @chan: Identifies the host channel to set up and its properties 1106 * @hcchar: Current value of the HCCHAR register for the specified host channel 1107 * 1108 * This function has no effect on non-periodic transfers 1109 */ 1110 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1111 struct dwc2_host_chan *chan, u32 *hcchar) 1112 { 1113 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1114 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1115 /* 1 if _next_ frame is odd, 0 if it's even */ 1116 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) 1117 *hcchar |= HCCHAR_ODDFRM; 1118 } 1119 } 1120 1121 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1122 { 1123 /* Set up the initial PID for the transfer */ 1124 if (chan->speed == USB_SPEED_HIGH) { 1125 if (chan->ep_is_in) { 1126 if (chan->multi_count == 1) 1127 chan->data_pid_start = DWC2_HC_PID_DATA0; 1128 else if (chan->multi_count == 2) 1129 chan->data_pid_start = DWC2_HC_PID_DATA1; 1130 else 1131 chan->data_pid_start = DWC2_HC_PID_DATA2; 1132 } else { 1133 if (chan->multi_count == 1) 1134 chan->data_pid_start = DWC2_HC_PID_DATA0; 1135 else 1136 chan->data_pid_start = DWC2_HC_PID_MDATA; 1137 } 1138 } else { 1139 chan->data_pid_start = DWC2_HC_PID_DATA0; 1140 } 1141 } 1142 1143 /** 1144 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1145 * the Host Channel 1146 * 1147 * @hsotg: Programming view of DWC_otg controller 1148 * @chan: Information needed to initialize the host channel 1149 * 1150 * This function should only be called in Slave mode. For a channel associated 1151 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1152 * associated with a periodic EP, the periodic Tx FIFO is written. 1153 * 1154 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1155 * the number of bytes written to the Tx FIFO. 1156 */ 1157 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1158 struct dwc2_host_chan *chan) 1159 { 1160 u32 i; 1161 u32 remaining_count; 1162 u32 byte_count; 1163 u32 dword_count; 1164 u32 *data_buf = (u32 *)chan->xfer_buf; 1165 u32 data_fifo; 1166 1167 if (dbg_hc(chan)) 1168 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1169 1170 data_fifo = HCFIFO(chan->hc_num); 1171 1172 remaining_count = chan->xfer_len - chan->xfer_count; 1173 if (remaining_count > chan->max_packet) 1174 byte_count = chan->max_packet; 1175 else 1176 byte_count = remaining_count; 1177 1178 dword_count = (byte_count + 3) / 4; 1179 1180 if (((unsigned long)data_buf & 0x3) == 0) { 1181 /* xfer_buf is DWORD aligned */ 1182 for (i = 0; i < dword_count; i++, data_buf++) 1183 DWC2_WRITE_4(hsotg, data_fifo, *data_buf); 1184 } else { 1185 /* xfer_buf is not DWORD aligned */ 1186 for (i = 0; i < dword_count; i++, data_buf++) { 1187 u32 data = data_buf[0] | data_buf[1] << 8 | 1188 data_buf[2] << 16 | data_buf[3] << 24; 1189 DWC2_WRITE_4(hsotg, data_fifo, data); 1190 } 1191 } 1192 1193 chan->xfer_count += byte_count; 1194 chan->xfer_buf += byte_count; 1195 } 1196 1197 /** 1198 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1199 * channel and starts the transfer 1200 * 1201 * @hsotg: Programming view of DWC_otg controller 1202 * @chan: Information needed to initialize the host channel. The xfer_len value 1203 * may be reduced to accommodate the max widths of the XferSize and 1204 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1205 * changed to reflect the final xfer_len value. 1206 * 1207 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1208 * the caller must ensure that there is sufficient space in the request queue 1209 * and Tx Data FIFO. 1210 * 1211 * For an OUT transfer in Slave mode, it loads a data packet into the 1212 * appropriate FIFO. If necessary, additional data packets are loaded in the 1213 * Host ISR. 1214 * 1215 * For an IN transfer in Slave mode, a data packet is requested. The data 1216 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1217 * additional data packets are requested in the Host ISR. 1218 * 1219 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1220 * register along with a packet count of 1 and the channel is enabled. This 1221 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1222 * simply set to 0 since no data transfer occurs in this case. 1223 * 1224 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1225 * all the information required to perform the subsequent data transfer. In 1226 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1227 * controller performs the entire PING protocol, then starts the data 1228 * transfer. 1229 */ 1230 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1231 struct dwc2_host_chan *chan) 1232 { 1233 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; 1234 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; 1235 u32 hcchar; 1236 u32 hctsiz = 0; 1237 u16 num_packets; 1238 1239 if (dbg_hc(chan)) 1240 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1241 1242 if (chan->do_ping) { 1243 if (hsotg->core_params->dma_enable <= 0) { 1244 if (dbg_hc(chan)) 1245 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1246 dwc2_hc_do_ping(hsotg, chan); 1247 chan->xfer_started = 1; 1248 return; 1249 } else { 1250 if (dbg_hc(chan)) 1251 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1252 hctsiz |= TSIZ_DOPNG; 1253 } 1254 } 1255 1256 if (chan->do_split) { 1257 if (dbg_hc(chan)) 1258 dev_vdbg(hsotg->dev, "split\n"); 1259 num_packets = 1; 1260 1261 if (chan->complete_split && !chan->ep_is_in) 1262 /* 1263 * For CSPLIT OUT Transfer, set the size to 0 so the 1264 * core doesn't expect any data written to the FIFO 1265 */ 1266 chan->xfer_len = 0; 1267 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1268 chan->xfer_len = chan->max_packet; 1269 else if (!chan->ep_is_in && chan->xfer_len > 188) 1270 chan->xfer_len = 188; 1271 1272 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1273 TSIZ_XFERSIZE_MASK; 1274 } else { 1275 if (dbg_hc(chan)) 1276 dev_vdbg(hsotg->dev, "no split\n"); 1277 /* 1278 * Ensure that the transfer length and packet count will fit 1279 * in the widths allocated for them in the HCTSIZn register 1280 */ 1281 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1282 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1283 /* 1284 * Make sure the transfer size is no larger than one 1285 * (micro)frame's worth of data. (A check was done 1286 * when the periodic transfer was accepted to ensure 1287 * that a (micro)frame's worth of data can be 1288 * programmed into a channel.) 1289 */ 1290 u32 max_periodic_len = 1291 chan->multi_count * chan->max_packet; 1292 1293 if (chan->xfer_len > max_periodic_len) 1294 chan->xfer_len = max_periodic_len; 1295 } else if (chan->xfer_len > max_hc_xfer_size) { 1296 /* 1297 * Make sure that xfer_len is a multiple of max packet 1298 * size 1299 */ 1300 chan->xfer_len = 1301 max_hc_xfer_size - chan->max_packet + 1; 1302 } 1303 1304 if (chan->xfer_len > 0) { 1305 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1306 chan->max_packet; 1307 if (num_packets > max_hc_pkt_count) { 1308 num_packets = max_hc_pkt_count; 1309 chan->xfer_len = num_packets * chan->max_packet; 1310 } 1311 } else { 1312 /* Need 1 packet for transfer length of 0 */ 1313 num_packets = 1; 1314 } 1315 1316 if (chan->ep_is_in) 1317 /* 1318 * Always program an integral # of max packets for IN 1319 * transfers 1320 */ 1321 chan->xfer_len = num_packets * chan->max_packet; 1322 1323 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1324 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1325 /* 1326 * Make sure that the multi_count field matches the 1327 * actual transfer length 1328 */ 1329 chan->multi_count = num_packets; 1330 1331 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1332 dwc2_set_pid_isoc(chan); 1333 1334 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1335 TSIZ_XFERSIZE_MASK; 1336 } 1337 1338 chan->start_pkt_count = num_packets; 1339 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1340 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1341 TSIZ_SC_MC_PID_MASK; 1342 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1343 if (dbg_hc(chan)) { 1344 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1345 hctsiz, chan->hc_num); 1346 1347 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1348 chan->hc_num); 1349 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1350 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1351 TSIZ_XFERSIZE_SHIFT); 1352 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1353 (hctsiz & TSIZ_PKTCNT_MASK) >> 1354 TSIZ_PKTCNT_SHIFT); 1355 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1356 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1357 TSIZ_SC_MC_PID_SHIFT); 1358 } 1359 1360 if (hsotg->core_params->dma_enable > 0) { 1361 dma_addr_t dma_addr; 1362 1363 if (chan->align_buf) { 1364 if (dbg_hc(chan)) 1365 dev_vdbg(hsotg->dev, "align_buf\n"); 1366 dma_addr = chan->align_buf; 1367 } else { 1368 dma_addr = chan->xfer_dma; 1369 } 1370 DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), (u32)dma_addr); 1371 if (dbg_hc(chan)) 1372 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1373 (unsigned long)dma_addr, chan->hc_num); 1374 } 1375 1376 /* Start the split */ 1377 if (chan->do_split) { 1378 u32 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 1379 1380 hcsplt |= HCSPLT_SPLTENA; 1381 DWC2_WRITE_4(hsotg, HCSPLT(chan->hc_num), hcsplt); 1382 } 1383 1384 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1385 hcchar &= ~HCCHAR_MULTICNT_MASK; 1386 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1387 HCCHAR_MULTICNT_MASK; 1388 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1389 1390 if (hcchar & HCCHAR_CHDIS) 1391 dev_warn(hsotg->dev, 1392 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1393 __func__, chan->hc_num, hcchar); 1394 1395 /* Set host channel enable after all other setup is complete */ 1396 hcchar |= HCCHAR_CHENA; 1397 hcchar &= ~HCCHAR_CHDIS; 1398 1399 if (dbg_hc(chan)) 1400 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1401 (hcchar & HCCHAR_MULTICNT_MASK) >> 1402 HCCHAR_MULTICNT_SHIFT); 1403 1404 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1405 if (dbg_hc(chan)) 1406 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1407 chan->hc_num); 1408 1409 chan->xfer_started = 1; 1410 chan->requests++; 1411 1412 if (hsotg->core_params->dma_enable <= 0 && 1413 !chan->ep_is_in && chan->xfer_len > 0) 1414 /* Load OUT packet into the appropriate Tx FIFO */ 1415 dwc2_hc_write_packet(hsotg, chan); 1416 } 1417 1418 /** 1419 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1420 * host channel and starts the transfer in Descriptor DMA mode 1421 * 1422 * @hsotg: Programming view of DWC_otg controller 1423 * @chan: Information needed to initialize the host channel 1424 * 1425 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1426 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1427 * with micro-frame bitmap. 1428 * 1429 * Initializes HCDMA register with descriptor list address and CTD value then 1430 * starts the transfer via enabling the channel. 1431 */ 1432 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1433 struct dwc2_host_chan *chan) 1434 { 1435 u32 hcchar; 1436 u32 hc_dma; 1437 u32 hctsiz = 0; 1438 1439 if (chan->do_ping) 1440 hctsiz |= TSIZ_DOPNG; 1441 1442 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1443 dwc2_set_pid_isoc(chan); 1444 1445 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1446 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1447 TSIZ_SC_MC_PID_MASK; 1448 1449 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1450 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1451 1452 /* Non-zero only for high-speed interrupt endpoints */ 1453 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1454 1455 if (dbg_hc(chan)) { 1456 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1457 chan->hc_num); 1458 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1459 chan->data_pid_start); 1460 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1461 } 1462 1463 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1464 1465 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; 1466 1467 /* Always start from first descriptor */ 1468 hc_dma &= ~HCDMA_CTD_MASK; 1469 DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), hc_dma); 1470 if (dbg_hc(chan)) 1471 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", 1472 hc_dma, chan->hc_num); 1473 1474 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1475 hcchar &= ~HCCHAR_MULTICNT_MASK; 1476 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1477 HCCHAR_MULTICNT_MASK; 1478 1479 if (hcchar & HCCHAR_CHDIS) 1480 dev_warn(hsotg->dev, 1481 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1482 __func__, chan->hc_num, hcchar); 1483 1484 /* Set host channel enable after all other setup is complete */ 1485 hcchar |= HCCHAR_CHENA; 1486 hcchar &= ~HCCHAR_CHDIS; 1487 1488 if (dbg_hc(chan)) 1489 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1490 (hcchar & HCCHAR_MULTICNT_MASK) >> 1491 HCCHAR_MULTICNT_SHIFT); 1492 1493 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1494 if (dbg_hc(chan)) 1495 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1496 chan->hc_num); 1497 1498 chan->xfer_started = 1; 1499 chan->requests++; 1500 } 1501 1502 /** 1503 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1504 * a previous call to dwc2_hc_start_transfer() 1505 * 1506 * @hsotg: Programming view of DWC_otg controller 1507 * @chan: Information needed to initialize the host channel 1508 * 1509 * The caller must ensure there is sufficient space in the request queue and Tx 1510 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1511 * the controller acts autonomously to complete transfers programmed to a host 1512 * channel. 1513 * 1514 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1515 * if there is any data remaining to be queued. For an IN transfer, another 1516 * data packet is always requested. For the SETUP phase of a control transfer, 1517 * this function does nothing. 1518 * 1519 * Return: 1 if a new request is queued, 0 if no more requests are required 1520 * for this transfer 1521 */ 1522 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1523 struct dwc2_host_chan *chan) 1524 { 1525 if (dbg_hc(chan)) 1526 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1527 chan->hc_num); 1528 1529 if (chan->do_split) 1530 /* SPLITs always queue just once per channel */ 1531 return 0; 1532 1533 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1534 /* SETUPs are queued only once since they can't be NAK'd */ 1535 return 0; 1536 1537 if (chan->ep_is_in) { 1538 /* 1539 * Always queue another request for other IN transfers. If 1540 * back-to-back INs are issued and NAKs are received for both, 1541 * the driver may still be processing the first NAK when the 1542 * second NAK is received. When the interrupt handler clears 1543 * the NAK interrupt for the first NAK, the second NAK will 1544 * not be seen. So we can't depend on the NAK interrupt 1545 * handler to requeue a NAK'd request. Instead, IN requests 1546 * are issued each time this function is called. When the 1547 * transfer completes, the extra requests for the channel will 1548 * be flushed. 1549 */ 1550 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1551 1552 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1553 hcchar |= HCCHAR_CHENA; 1554 hcchar &= ~HCCHAR_CHDIS; 1555 if (dbg_hc(chan)) 1556 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1557 hcchar); 1558 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1559 chan->requests++; 1560 return 1; 1561 } 1562 1563 /* OUT transfers */ 1564 1565 if (chan->xfer_count < chan->xfer_len) { 1566 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1567 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1568 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1569 1570 dwc2_hc_set_even_odd_frame(hsotg, chan, 1571 &hcchar); 1572 } 1573 1574 /* Load OUT packet into the appropriate Tx FIFO */ 1575 dwc2_hc_write_packet(hsotg, chan); 1576 chan->requests++; 1577 return 1; 1578 } 1579 1580 return 0; 1581 } 1582 1583 /** 1584 * dwc2_hc_do_ping() - Starts a PING transfer 1585 * 1586 * @hsotg: Programming view of DWC_otg controller 1587 * @chan: Information needed to initialize the host channel 1588 * 1589 * This function should only be called in Slave mode. The Do Ping bit is set in 1590 * the HCTSIZ register, then the channel is enabled. 1591 */ 1592 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1593 { 1594 u32 hcchar; 1595 u32 hctsiz; 1596 1597 if (dbg_hc(chan)) 1598 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1599 chan->hc_num); 1600 1601 1602 hctsiz = TSIZ_DOPNG; 1603 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1604 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1605 1606 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1607 hcchar |= HCCHAR_CHENA; 1608 hcchar &= ~HCCHAR_CHDIS; 1609 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1610 } 1611 1612 /** 1613 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 1614 * the HFIR register according to PHY type and speed 1615 * 1616 * @hsotg: Programming view of DWC_otg controller 1617 * 1618 * NOTE: The caller can modify the value of the HFIR register only after the 1619 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 1620 * has been set 1621 */ 1622 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 1623 { 1624 u32 usbcfg; 1625 u32 hprt0; 1626 int clock = 60; /* default value */ 1627 1628 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 1629 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1630 1631 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 1632 !(usbcfg & GUSBCFG_PHYIF16)) 1633 clock = 60; 1634 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 1635 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 1636 clock = 48; 1637 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 1638 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 1639 clock = 30; 1640 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 1641 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 1642 clock = 60; 1643 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 1644 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 1645 clock = 48; 1646 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 1647 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 1648 clock = 48; 1649 if ((usbcfg & GUSBCFG_PHYSEL) && 1650 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 1651 clock = 48; 1652 1653 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 1654 /* High speed case */ 1655 return 125 * clock; 1656 else 1657 /* FS/LS case */ 1658 return 1000 * clock; 1659 } 1660 1661 /** 1662 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 1663 * buffer 1664 * 1665 * @core_if: Programming view of DWC_otg controller 1666 * @dest: Destination buffer for the packet 1667 * @bytes: Number of bytes to copy to the destination 1668 */ 1669 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 1670 { 1671 bus_size_t fifo = HCFIFO(0); 1672 u32 *data_buf = (u32 *)dest; 1673 int word_count = (bytes + 3) / 4; 1674 int i; 1675 1676 /* 1677 * Todo: Account for the case where dest is not dword aligned. This 1678 * requires reading data from the FIFO into a u32 temp buffer, then 1679 * moving it into the data buffer. 1680 */ 1681 1682 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 1683 1684 for (i = 0; i < word_count; i++, data_buf++) 1685 *data_buf = DWC2_READ_4(hsotg, fifo); 1686 } 1687 1688 /** 1689 * dwc2_dump_host_registers() - Prints the host registers 1690 * 1691 * @hsotg: Programming view of DWC_otg controller 1692 * 1693 * NOTE: This function will be removed once the peripheral controller code 1694 * is integrated and the driver is stable 1695 */ 1696 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 1697 { 1698 #ifdef DEBUG 1699 bus_size_t addr; 1700 int i; 1701 1702 dev_dbg(hsotg->dev, "Host Global Registers\n"); 1703 addr = HCFG; 1704 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 1705 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1706 addr = HFIR; 1707 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 1708 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1709 addr = HFNUM; 1710 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 1711 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1712 addr = HPTXSTS; 1713 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 1714 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1715 addr = HAINT; 1716 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 1717 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1718 addr = HAINTMSK; 1719 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 1720 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1721 if (hsotg->core_params->dma_desc_enable > 0) { 1722 addr = HFLBADDR; 1723 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 1724 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1725 } 1726 1727 addr = HPRT0; 1728 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 1729 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1730 1731 for (i = 0; i < hsotg->core_params->host_channels; i++) { 1732 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 1733 addr = HCCHAR(i); 1734 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 1735 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1736 addr = HCSPLT(i); 1737 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 1738 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1739 addr = HCINT(i); 1740 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 1741 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1742 addr = HCINTMSK(i); 1743 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 1744 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1745 addr = HCTSIZ(i); 1746 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 1747 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1748 addr = HCDMA(i); 1749 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 1750 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1751 if (hsotg->core_params->dma_desc_enable > 0) { 1752 addr = HCDMAB(i); 1753 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 1754 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1755 } 1756 } 1757 #endif 1758 } 1759 1760 /** 1761 * dwc2_dump_global_registers() - Prints the core global registers 1762 * 1763 * @hsotg: Programming view of DWC_otg controller 1764 * 1765 * NOTE: This function will be removed once the peripheral controller code 1766 * is integrated and the driver is stable 1767 */ 1768 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 1769 { 1770 #ifdef DEBUG 1771 bus_size_t addr; 1772 1773 dev_dbg(hsotg->dev, "Core Global Registers\n"); 1774 addr = GOTGCTL; 1775 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 1776 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1777 addr = GOTGINT; 1778 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 1779 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1780 addr = GAHBCFG; 1781 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 1782 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1783 addr = GUSBCFG; 1784 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 1785 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1786 addr = GRSTCTL; 1787 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 1788 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1789 addr = GINTSTS; 1790 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 1791 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1792 addr = GINTMSK; 1793 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 1794 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1795 addr = GRXSTSR; 1796 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 1797 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1798 addr = GRXFSIZ; 1799 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 1800 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1801 addr = GNPTXFSIZ; 1802 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 1803 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1804 addr = GNPTXSTS; 1805 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 1806 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1807 addr = GI2CCTL; 1808 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 1809 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1810 addr = GPVNDCTL; 1811 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 1812 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1813 addr = GGPIO; 1814 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 1815 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1816 addr = GUID; 1817 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 1818 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1819 addr = GSNPSID; 1820 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 1821 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1822 addr = GHWCFG1; 1823 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 1824 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1825 addr = GHWCFG2; 1826 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 1827 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1828 addr = GHWCFG3; 1829 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 1830 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1831 addr = GHWCFG4; 1832 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 1833 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1834 addr = GLPMCFG; 1835 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 1836 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1837 addr = GPWRDN; 1838 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 1839 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1840 addr = GDFIFOCFG; 1841 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 1842 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1843 addr = HPTXFSIZ; 1844 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 1845 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1846 1847 addr = PCGCTL; 1848 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 1849 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1850 #endif 1851 } 1852 1853 /** 1854 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 1855 * 1856 * @hsotg: Programming view of DWC_otg controller 1857 * @num: Tx FIFO to flush 1858 */ 1859 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 1860 { 1861 u32 greset; 1862 int count = 0; 1863 1864 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 1865 1866 greset = GRSTCTL_TXFFLSH; 1867 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 1868 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 1869 1870 do { 1871 greset = DWC2_READ_4(hsotg, GRSTCTL); 1872 if (++count > 10000) { 1873 dev_warn(hsotg->dev, 1874 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", 1875 __func__, greset, 1876 DWC2_READ_4(hsotg, GNPTXSTS)); 1877 break; 1878 } 1879 udelay(1); 1880 } while (greset & GRSTCTL_TXFFLSH); 1881 1882 /* Wait for at least 3 PHY Clocks */ 1883 udelay(1); 1884 } 1885 1886 /** 1887 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 1888 * 1889 * @hsotg: Programming view of DWC_otg controller 1890 */ 1891 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 1892 { 1893 u32 greset; 1894 int count = 0; 1895 1896 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1897 1898 greset = GRSTCTL_RXFFLSH; 1899 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 1900 1901 do { 1902 greset = DWC2_READ_4(hsotg, GRSTCTL); 1903 if (++count > 10000) { 1904 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", 1905 __func__, greset); 1906 break; 1907 } 1908 udelay(1); 1909 } while (greset & GRSTCTL_RXFFLSH); 1910 1911 /* Wait for at least 3 PHY Clocks */ 1912 udelay(1); 1913 } 1914 1915 #define DWC2_PARAM_TEST(a, b, c) ((a) < (b) || (a) > (c)) 1916 1917 /* Parameter access functions */ 1918 int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 1919 { 1920 int valid = 1; 1921 int retval = 0; 1922 1923 switch (val) { 1924 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 1925 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 1926 valid = 0; 1927 break; 1928 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 1929 switch (hsotg->hw_params.op_mode) { 1930 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 1931 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 1932 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 1933 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 1934 break; 1935 default: 1936 valid = 0; 1937 break; 1938 } 1939 break; 1940 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 1941 /* always valid */ 1942 break; 1943 default: 1944 valid = 0; 1945 break; 1946 } 1947 1948 if (!valid) { 1949 if (val >= 0) 1950 dev_err(hsotg->dev, 1951 "%d invalid for otg_cap parameter. Check HW configuration.\n", 1952 val); 1953 switch (hsotg->hw_params.op_mode) { 1954 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 1955 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 1956 break; 1957 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 1958 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 1959 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 1960 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 1961 break; 1962 default: 1963 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 1964 break; 1965 } 1966 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 1967 retval = -EINVAL; 1968 } 1969 1970 hsotg->core_params->otg_cap = val; 1971 return retval; 1972 } 1973 1974 int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 1975 { 1976 int valid = 1; 1977 int retval = 0; 1978 1979 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) 1980 valid = 0; 1981 if (val < 0) 1982 valid = 0; 1983 1984 if (!valid) { 1985 if (val >= 0) 1986 dev_err(hsotg->dev, 1987 "%d invalid for dma_enable parameter. Check HW configuration.\n", 1988 val); 1989 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; 1990 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); 1991 retval = -EINVAL; 1992 } 1993 1994 hsotg->core_params->dma_enable = val; 1995 return retval; 1996 } 1997 1998 int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 1999 { 2000 int valid = 1; 2001 int retval = 0; 2002 2003 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 2004 !hsotg->hw_params.dma_desc_enable)) 2005 valid = 0; 2006 if (val < 0) 2007 valid = 0; 2008 2009 if (!valid) { 2010 if (val >= 0) 2011 dev_err(hsotg->dev, 2012 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 2013 val); 2014 val = (hsotg->core_params->dma_enable > 0 && 2015 hsotg->hw_params.dma_desc_enable); 2016 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 2017 retval = -EINVAL; 2018 } 2019 2020 hsotg->core_params->dma_desc_enable = val; 2021 return retval; 2022 } 2023 2024 int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 2025 int val) 2026 { 2027 int retval = 0; 2028 2029 if (DWC2_PARAM_TEST(val, 0, 1)) { 2030 if (val >= 0) { 2031 dev_err(hsotg->dev, 2032 "Wrong value for host_support_fs_low_power\n"); 2033 dev_err(hsotg->dev, 2034 "host_support_fs_low_power must be 0 or 1\n"); 2035 } 2036 val = 0; 2037 dev_dbg(hsotg->dev, 2038 "Setting host_support_fs_low_power to %d\n", val); 2039 retval = -EINVAL; 2040 } 2041 2042 hsotg->core_params->host_support_fs_ls_low_power = val; 2043 return retval; 2044 } 2045 2046 int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) 2047 { 2048 int valid = 1; 2049 int retval = 0; 2050 2051 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 2052 valid = 0; 2053 if (val < 0) 2054 valid = 0; 2055 2056 if (!valid) { 2057 if (val >= 0) 2058 dev_err(hsotg->dev, 2059 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 2060 val); 2061 val = hsotg->hw_params.enable_dynamic_fifo; 2062 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 2063 retval = -EINVAL; 2064 } 2065 2066 hsotg->core_params->enable_dynamic_fifo = val; 2067 return retval; 2068 } 2069 2070 int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2071 { 2072 int valid = 1; 2073 int retval = 0; 2074 2075 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) 2076 valid = 0; 2077 2078 if (!valid) { 2079 if (val >= 0) 2080 dev_err(hsotg->dev, 2081 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 2082 val); 2083 val = hsotg->hw_params.host_rx_fifo_size; 2084 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 2085 retval = -EINVAL; 2086 } 2087 2088 hsotg->core_params->host_rx_fifo_size = val; 2089 return retval; 2090 } 2091 2092 int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2093 { 2094 int valid = 1; 2095 int retval = 0; 2096 2097 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 2098 valid = 0; 2099 2100 if (!valid) { 2101 if (val >= 0) 2102 dev_err(hsotg->dev, 2103 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 2104 val); 2105 val = hsotg->hw_params.host_nperio_tx_fifo_size; 2106 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 2107 val); 2108 retval = -EINVAL; 2109 } 2110 2111 hsotg->core_params->host_nperio_tx_fifo_size = val; 2112 return retval; 2113 } 2114 2115 int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2116 { 2117 int valid = 1; 2118 int retval = 0; 2119 2120 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 2121 valid = 0; 2122 2123 if (!valid) { 2124 if (val >= 0) 2125 dev_err(hsotg->dev, 2126 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 2127 val); 2128 val = hsotg->hw_params.host_perio_tx_fifo_size; 2129 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 2130 val); 2131 retval = -EINVAL; 2132 } 2133 2134 hsotg->core_params->host_perio_tx_fifo_size = val; 2135 return retval; 2136 } 2137 2138 int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 2139 { 2140 int valid = 1; 2141 int retval = 0; 2142 2143 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 2144 valid = 0; 2145 2146 if (!valid) { 2147 if (val >= 0) 2148 dev_err(hsotg->dev, 2149 "%d invalid for max_transfer_size. Check HW configuration.\n", 2150 val); 2151 val = hsotg->hw_params.max_transfer_size; 2152 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 2153 retval = -EINVAL; 2154 } 2155 2156 hsotg->core_params->max_transfer_size = val; 2157 return retval; 2158 } 2159 2160 int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 2161 { 2162 int valid = 1; 2163 int retval = 0; 2164 2165 if (val < 15 || val > hsotg->hw_params.max_packet_count) 2166 valid = 0; 2167 2168 if (!valid) { 2169 if (val >= 0) 2170 dev_err(hsotg->dev, 2171 "%d invalid for max_packet_count. Check HW configuration.\n", 2172 val); 2173 val = hsotg->hw_params.max_packet_count; 2174 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 2175 retval = -EINVAL; 2176 } 2177 2178 hsotg->core_params->max_packet_count = val; 2179 return retval; 2180 } 2181 2182 int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 2183 { 2184 int valid = 1; 2185 int retval = 0; 2186 2187 if (val < 1 || val > hsotg->hw_params.host_channels) 2188 valid = 0; 2189 2190 if (!valid) { 2191 if (val >= 0) 2192 dev_err(hsotg->dev, 2193 "%d invalid for host_channels. Check HW configuration.\n", 2194 val); 2195 val = hsotg->hw_params.host_channels; 2196 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 2197 retval = -EINVAL; 2198 } 2199 2200 hsotg->core_params->host_channels = val; 2201 return retval; 2202 } 2203 2204 int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 2205 { 2206 #ifndef NO_FS_PHY_HW_CHECKS 2207 int valid = 0; 2208 u32 hs_phy_type, fs_phy_type; 2209 #endif 2210 int retval = 0; 2211 2212 if (DWC2_PARAM_TEST(val, DWC2_PHY_TYPE_PARAM_FS, 2213 DWC2_PHY_TYPE_PARAM_ULPI)) { 2214 if (val >= 0) { 2215 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 2216 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 2217 } 2218 2219 #ifndef NO_FS_PHY_HW_CHECKS 2220 valid = 0; 2221 #else 2222 val = DWC2_PHY_TYPE_PARAM_FS; 2223 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 2224 retval = -EINVAL; 2225 #endif 2226 } 2227 2228 #ifndef NO_FS_PHY_HW_CHECKS 2229 hs_phy_type = hsotg->hw_params.hs_phy_type; 2230 fs_phy_type = hsotg->hw_params.fs_phy_type; 2231 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 2232 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2233 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2234 valid = 1; 2235 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 2236 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 2237 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2238 valid = 1; 2239 else if (val == DWC2_PHY_TYPE_PARAM_FS && 2240 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 2241 valid = 1; 2242 2243 if (!valid) { 2244 if (val >= 0) 2245 dev_err(hsotg->dev, 2246 "%d invalid for phy_type. Check HW configuration.\n", 2247 val); 2248 val = DWC2_PHY_TYPE_PARAM_FS; 2249 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 2250 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2251 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 2252 val = DWC2_PHY_TYPE_PARAM_UTMI; 2253 else 2254 val = DWC2_PHY_TYPE_PARAM_ULPI; 2255 } 2256 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 2257 retval = -EINVAL; 2258 } 2259 #endif 2260 2261 hsotg->core_params->phy_type = val; 2262 return retval; 2263 } 2264 2265 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 2266 { 2267 return hsotg->core_params->phy_type; 2268 } 2269 2270 int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 2271 { 2272 int valid = 1; 2273 int retval = 0; 2274 2275 if (DWC2_PARAM_TEST(val, 0, 1)) { 2276 if (val >= 0) { 2277 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 2278 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); 2279 } 2280 valid = 0; 2281 } 2282 2283 if (val == DWC2_SPEED_PARAM_HIGH && 2284 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2285 valid = 0; 2286 2287 if (!valid) { 2288 if (val >= 0) 2289 dev_err(hsotg->dev, 2290 "%d invalid for speed parameter. Check HW configuration.\n", 2291 val); 2292 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 2293 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 2294 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 2295 retval = -EINVAL; 2296 } 2297 2298 hsotg->core_params->speed = val; 2299 return retval; 2300 } 2301 2302 int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) 2303 { 2304 int valid = 1; 2305 int retval = 0; 2306 2307 if (DWC2_PARAM_TEST(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 2308 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 2309 if (val >= 0) { 2310 dev_err(hsotg->dev, 2311 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 2312 dev_err(hsotg->dev, 2313 "host_ls_low_power_phy_clk must be 0 or 1\n"); 2314 } 2315 valid = 0; 2316 } 2317 2318 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 2319 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2320 valid = 0; 2321 2322 if (!valid) { 2323 if (val >= 0) 2324 dev_err(hsotg->dev, 2325 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 2326 val); 2327 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 2328 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 2329 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 2330 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 2331 val); 2332 retval = -EINVAL; 2333 } 2334 2335 hsotg->core_params->host_ls_low_power_phy_clk = val; 2336 return retval; 2337 } 2338 2339 int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 2340 { 2341 int retval = 0; 2342 2343 if (DWC2_PARAM_TEST(val, 0, 1)) { 2344 if (val >= 0) { 2345 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 2346 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 2347 } 2348 val = 0; 2349 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 2350 retval = -EINVAL; 2351 } 2352 2353 hsotg->core_params->phy_ulpi_ddr = val; 2354 return retval; 2355 } 2356 2357 int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 2358 { 2359 int retval = 0; 2360 2361 if (DWC2_PARAM_TEST(val, 0, 1)) { 2362 if (val >= 0) { 2363 dev_err(hsotg->dev, 2364 "Wrong value for phy_ulpi_ext_vbus\n"); 2365 dev_err(hsotg->dev, 2366 "phy_ulpi_ext_vbus must be 0 or 1\n"); 2367 } 2368 val = 0; 2369 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 2370 retval = -EINVAL; 2371 } 2372 2373 hsotg->core_params->phy_ulpi_ext_vbus = val; 2374 return retval; 2375 } 2376 2377 int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 2378 { 2379 int valid = 0; 2380 int retval = 0; 2381 2382 switch (hsotg->hw_params.utmi_phy_data_width) { 2383 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 2384 valid = (val == 8); 2385 break; 2386 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 2387 valid = (val == 16); 2388 break; 2389 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 2390 valid = (val == 8 || val == 16); 2391 break; 2392 } 2393 2394 if (!valid) { 2395 if (val >= 0) { 2396 dev_err(hsotg->dev, 2397 "%d invalid for phy_utmi_width. Check HW configuration.\n", 2398 val); 2399 } 2400 val = (hsotg->hw_params.utmi_phy_data_width == 2401 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 2402 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 2403 retval = -EINVAL; 2404 } 2405 2406 hsotg->core_params->phy_utmi_width = val; 2407 return retval; 2408 } 2409 2410 int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 2411 { 2412 int retval = 0; 2413 2414 if (DWC2_PARAM_TEST(val, 0, 1)) { 2415 if (val >= 0) { 2416 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 2417 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 2418 } 2419 val = 0; 2420 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 2421 retval = -EINVAL; 2422 } 2423 2424 hsotg->core_params->ulpi_fs_ls = val; 2425 return retval; 2426 } 2427 2428 int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 2429 { 2430 int retval = 0; 2431 2432 if (DWC2_PARAM_TEST(val, 0, 1)) { 2433 if (val >= 0) { 2434 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 2435 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 2436 } 2437 val = 0; 2438 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 2439 retval = -EINVAL; 2440 } 2441 2442 hsotg->core_params->ts_dline = val; 2443 return retval; 2444 } 2445 2446 int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 2447 { 2448 #ifndef NO_FS_PHY_HW_CHECKS 2449 int valid = 1; 2450 #endif 2451 int retval = 0; 2452 2453 if (DWC2_PARAM_TEST(val, 0, 1)) { 2454 if (val >= 0) { 2455 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 2456 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 2457 } 2458 2459 #ifndef NO_FS_PHY_HW_CHECKS 2460 valid = 0; 2461 #else 2462 val = 0; 2463 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 2464 retval = -EINVAL; 2465 #endif 2466 } 2467 2468 #ifndef NO_FS_PHY_HW_CHECKS 2469 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 2470 valid = 0; 2471 2472 if (!valid) { 2473 if (val >= 0) 2474 dev_err(hsotg->dev, 2475 "%d invalid for i2c_enable. Check HW configuration.\n", 2476 val); 2477 val = hsotg->hw_params.i2c_enable; 2478 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 2479 retval = -EINVAL; 2480 } 2481 #endif 2482 2483 hsotg->core_params->i2c_enable = val; 2484 return retval; 2485 } 2486 2487 int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) 2488 { 2489 int valid = 1; 2490 int retval = 0; 2491 2492 if (DWC2_PARAM_TEST(val, 0, 1)) { 2493 if (val >= 0) { 2494 dev_err(hsotg->dev, 2495 "Wrong value for en_multiple_tx_fifo,\n"); 2496 dev_err(hsotg->dev, 2497 "en_multiple_tx_fifo must be 0 or 1\n"); 2498 } 2499 valid = 0; 2500 } 2501 2502 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 2503 valid = 0; 2504 2505 if (!valid) { 2506 if (val >= 0) 2507 dev_err(hsotg->dev, 2508 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 2509 val); 2510 val = hsotg->hw_params.en_multiple_tx_fifo; 2511 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 2512 retval = -EINVAL; 2513 } 2514 2515 hsotg->core_params->en_multiple_tx_fifo = val; 2516 return retval; 2517 } 2518 2519 int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 2520 { 2521 int valid = 1; 2522 int retval = 0; 2523 2524 if (DWC2_PARAM_TEST(val, 0, 1)) { 2525 if (val >= 0) { 2526 dev_err(hsotg->dev, 2527 "'%d' invalid for parameter reload_ctl\n", val); 2528 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 2529 } 2530 valid = 0; 2531 } 2532 2533 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 2534 valid = 0; 2535 2536 if (!valid) { 2537 if (val >= 0) 2538 dev_err(hsotg->dev, 2539 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 2540 val); 2541 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 2542 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 2543 retval = -EINVAL; 2544 } 2545 2546 hsotg->core_params->reload_ctl = val; 2547 return retval; 2548 } 2549 2550 int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 2551 { 2552 if (val != -1) 2553 hsotg->core_params->ahbcfg = val; 2554 else 2555 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 2556 GAHBCFG_HBSTLEN_SHIFT; 2557 return 0; 2558 } 2559 2560 int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 2561 { 2562 int retval = 0; 2563 2564 if (DWC2_PARAM_TEST(val, 0, 1)) { 2565 if (val >= 0) { 2566 dev_err(hsotg->dev, 2567 "'%d' invalid for parameter otg_ver\n", val); 2568 dev_err(hsotg->dev, 2569 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 2570 } 2571 val = 0; 2572 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 2573 retval = -EINVAL; 2574 } 2575 2576 hsotg->core_params->otg_ver = val; 2577 return retval; 2578 } 2579 2580 /** 2581 * During device initialization, read various hardware configuration 2582 * registers and interpret the contents. 2583 */ 2584 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 2585 { 2586 struct dwc2_hw_params *hw = &hsotg->hw_params; 2587 unsigned width; 2588 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 2589 u32 hptxfsiz, grxfsiz, gnptxfsiz; 2590 u32 gusbcfg; 2591 2592 /* 2593 * Attempt to ensure this device is really a DWC_otg Controller. 2594 * Read and verify the GSNPSID register contents. The value should be 2595 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 2596 * as in "OTG version 2.xx" or "OTG version 3.xx". 2597 */ 2598 hw->snpsid = DWC2_READ_4(hsotg, GSNPSID); 2599 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 2600 (hw->snpsid & 0xfffff000) != 0x4f543000) { 2601 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 2602 hw->snpsid); 2603 return -ENODEV; 2604 } 2605 2606 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 2607 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 2608 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 2609 2610 hwcfg1 = DWC2_READ_4(hsotg, GHWCFG1); 2611 hwcfg2 = DWC2_READ_4(hsotg, GHWCFG2); 2612 hwcfg3 = DWC2_READ_4(hsotg, GHWCFG3); 2613 hwcfg4 = DWC2_READ_4(hsotg, GHWCFG4); 2614 gnptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ); 2615 grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 2616 2617 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 2618 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 2619 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 2620 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 2621 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 2622 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 2623 2624 /* Force host mode to get HPTXFSIZ exact power on value */ 2625 gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 2626 gusbcfg |= GUSBCFG_FORCEHOSTMODE; 2627 DWC2_WRITE_4(hsotg, GUSBCFG, gusbcfg); 2628 usleep_range(100000, 150000); 2629 2630 hptxfsiz = DWC2_READ_4(hsotg, HPTXFSIZ); 2631 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 2632 gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 2633 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 2634 DWC2_WRITE_4(hsotg, GUSBCFG, gusbcfg); 2635 usleep_range(100000, 150000); 2636 2637 /* hwcfg2 */ 2638 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 2639 GHWCFG2_OP_MODE_SHIFT; 2640 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 2641 GHWCFG2_ARCHITECTURE_SHIFT; 2642 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 2643 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 2644 GHWCFG2_NUM_HOST_CHAN_SHIFT); 2645 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 2646 GHWCFG2_HS_PHY_TYPE_SHIFT; 2647 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 2648 GHWCFG2_FS_PHY_TYPE_SHIFT; 2649 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 2650 GHWCFG2_NUM_DEV_EP_SHIFT; 2651 hw->nperio_tx_q_depth = 2652 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 2653 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 2654 hw->host_perio_tx_q_depth = 2655 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 2656 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 2657 hw->dev_token_q_depth = 2658 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 2659 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 2660 2661 /* hwcfg3 */ 2662 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 2663 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 2664 hw->max_transfer_size = (1 << (width + 11)) - 1; 2665 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 2666 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 2667 hw->max_packet_count = (1 << (width + 4)) - 1; 2668 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 2669 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 2670 GHWCFG3_DFIFO_DEPTH_SHIFT; 2671 2672 /* hwcfg4 */ 2673 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 2674 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 2675 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 2676 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 2677 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 2678 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 2679 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 2680 2681 /* fifo sizes */ 2682 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 2683 GRXFSIZ_DEPTH_SHIFT; 2684 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 2685 FIFOSIZE_DEPTH_SHIFT; 2686 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 2687 FIFOSIZE_DEPTH_SHIFT; 2688 2689 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 2690 dev_dbg(hsotg->dev, " op_mode=%d\n", 2691 hw->op_mode); 2692 dev_dbg(hsotg->dev, " arch=%d\n", 2693 hw->arch); 2694 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 2695 hw->dma_desc_enable); 2696 dev_dbg(hsotg->dev, " power_optimized=%d\n", 2697 hw->power_optimized); 2698 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 2699 hw->i2c_enable); 2700 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 2701 hw->hs_phy_type); 2702 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 2703 hw->fs_phy_type); 2704 dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n", 2705 hw->utmi_phy_data_width); 2706 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 2707 hw->num_dev_ep); 2708 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 2709 hw->num_dev_perio_in_ep); 2710 dev_dbg(hsotg->dev, " host_channels=%d\n", 2711 hw->host_channels); 2712 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 2713 hw->max_transfer_size); 2714 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 2715 hw->max_packet_count); 2716 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 2717 hw->nperio_tx_q_depth); 2718 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 2719 hw->host_perio_tx_q_depth); 2720 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 2721 hw->dev_token_q_depth); 2722 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 2723 hw->enable_dynamic_fifo); 2724 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 2725 hw->en_multiple_tx_fifo); 2726 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 2727 hw->total_fifo_size); 2728 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", 2729 hw->host_rx_fifo_size); 2730 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 2731 hw->host_nperio_tx_fifo_size); 2732 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 2733 hw->host_perio_tx_fifo_size); 2734 dev_dbg(hsotg->dev, "\n"); 2735 2736 return 0; 2737 } 2738 2739 int dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 2740 { 2741 int retval = 0; 2742 2743 if (DWC2_PARAM_TEST(val, 0, 1)) { 2744 if (val >= 0) { 2745 dev_err(hsotg->dev, 2746 "'%d' invalid for parameter uframe_sched\n", 2747 val); 2748 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 2749 } 2750 val = 1; 2751 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 2752 retval = -EINVAL; 2753 } 2754 2755 hsotg->core_params->uframe_sched = val; 2756 return retval; 2757 } 2758 2759 /* 2760 * This function is called during module intialization to pass module parameters 2761 * for the DWC_otg core. It returns non-0 if any parameters are invalid. 2762 */ 2763 int dwc2_set_parameters(struct dwc2_hsotg *hsotg, 2764 const struct dwc2_core_params *params) 2765 { 2766 int retval = 0; 2767 2768 dev_dbg(hsotg->dev, "%s()\n", __func__); 2769 2770 retval |= dwc2_set_param_otg_cap(hsotg, params->otg_cap); 2771 retval |= dwc2_set_param_dma_enable(hsotg, params->dma_enable); 2772 retval |= dwc2_set_param_dma_desc_enable(hsotg, 2773 params->dma_desc_enable); 2774 retval |= dwc2_set_param_host_support_fs_ls_low_power(hsotg, 2775 params->host_support_fs_ls_low_power); 2776 retval |= dwc2_set_param_enable_dynamic_fifo(hsotg, 2777 params->enable_dynamic_fifo); 2778 retval |= dwc2_set_param_host_rx_fifo_size(hsotg, 2779 params->host_rx_fifo_size); 2780 retval |= dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 2781 params->host_nperio_tx_fifo_size); 2782 retval |= dwc2_set_param_host_perio_tx_fifo_size(hsotg, 2783 params->host_perio_tx_fifo_size); 2784 retval |= dwc2_set_param_max_transfer_size(hsotg, 2785 params->max_transfer_size); 2786 retval |= dwc2_set_param_max_packet_count(hsotg, 2787 params->max_packet_count); 2788 retval |= dwc2_set_param_host_channels(hsotg, params->host_channels); 2789 retval |= dwc2_set_param_phy_type(hsotg, params->phy_type); 2790 retval |= dwc2_set_param_speed(hsotg, params->speed); 2791 retval |= dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 2792 params->host_ls_low_power_phy_clk); 2793 retval |= dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 2794 retval |= dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 2795 params->phy_ulpi_ext_vbus); 2796 retval |= dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 2797 retval |= dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 2798 retval |= dwc2_set_param_ts_dline(hsotg, params->ts_dline); 2799 retval |= dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 2800 retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg, 2801 params->en_multiple_tx_fifo); 2802 retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 2803 retval |= dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 2804 retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver); 2805 retval |= dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 2806 2807 return retval; 2808 } 2809 2810 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) 2811 { 2812 return (u16)(hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103); 2813 } 2814 2815 int dwc2_check_core_status(struct dwc2_hsotg *hsotg) 2816 { 2817 if (DWC2_READ_4(hsotg, GSNPSID) == 0xffffffff) 2818 return -1; 2819 else 2820 return 0; 2821 } 2822 2823 /** 2824 * dwc2_enable_global_interrupts() - Enables the controller's Global 2825 * Interrupt in the AHB Config register 2826 * 2827 * @hsotg: Programming view of DWC_otg controller 2828 */ 2829 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 2830 { 2831 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2832 2833 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 2834 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2835 } 2836 2837 /** 2838 * dwc2_disable_global_interrupts() - Disables the controller's Global 2839 * Interrupt in the AHB Config register 2840 * 2841 * @hsotg: Programming view of DWC_otg controller 2842 */ 2843 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 2844 { 2845 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2846 2847 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2848 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2849 } 2850