1 /* $NetBSD: pci.h,v 1.56 2022/10/25 23:37:06 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Taylor R. Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _LINUX_PCI_H_ 33 #define _LINUX_PCI_H_ 34 35 #ifdef _KERNEL_OPT 36 #include "acpica.h" 37 #endif 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/cdefs.h> 43 #include <sys/kmem.h> 44 #include <sys/systm.h> 45 46 #include <machine/limits.h> 47 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/agpvar.h> 52 #include <dev/pci/ppbvar.h> 53 54 #include <linux/device.h> 55 #include <linux/dma-mapping.h> 56 #include <linux/errno.h> 57 #include <linux/io.h> 58 #include <linux/interrupt.h> 59 #include <linux/ioport.h> 60 #include <linux/kernel.h> 61 62 struct acpi_devnode; 63 struct pci_driver; 64 struct pci_dev; 65 66 struct pci_bus { 67 /* NetBSD private members */ 68 pci_chipset_tag_t pb_pc; 69 device_t pb_dev; 70 71 /* Linux API */ 72 u_int number; 73 74 struct pci_dev *self; 75 }; 76 77 struct pci_device_id { 78 uint32_t vendor; 79 uint32_t device; 80 uint32_t subvendor; 81 uint32_t subdevice; 82 uint32_t class; 83 uint32_t class_mask; 84 unsigned long driver_data; 85 }; 86 87 #define PCI_DEVICE(VENDOR, DEVICE) \ 88 .vendor = (VENDOR), \ 89 .device = (DEVICE) 90 91 #define PCI_ANY_ID (~0) 92 93 #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY 94 95 #define PCI_CLASS_DISPLAY_VGA \ 96 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA) 97 CTASSERT(PCI_CLASS_DISPLAY_VGA == 0x0300); 98 99 #define PCI_CLASS_DISPLAY_OTHER \ 100 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC) 101 CTASSERT(PCI_CLASS_DISPLAY_OTHER == 0x0380); 102 103 #define PCI_CLASS_BRIDGE_ISA \ 104 ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA) 105 CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601); 106 107 /* XXX This is getting silly... */ 108 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 109 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 110 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 111 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 112 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 113 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 114 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 115 #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA 116 #define PCI_VENDOR_ID_SI PCI_VENDOR_SIS 117 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 118 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 119 120 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 121 122 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY 123 124 #define PCI_SUBDEVICE_ID_QEMU 0x1100 125 126 #define PCI_DEVFN(DEV, FN) \ 127 (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2))) 128 #define PCI_SLOT(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(3, 7))) 129 #define PCI_FUNC(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(0, 2))) 130 131 #define PCI_DEVID(BUS, DEVFN) \ 132 (__SHIFTIN((BUS), __BITS(15, 8)) | __SHIFTIN((DEVFN), __BITS(7, 0))) 133 #define PCI_BUS_NUM(DEVID) ((int)__SHIFTOUT((DEVID), __BITS(15,8))) 134 135 #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4) 136 #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES 137 138 #define PCI_CAP_ID_AGP PCI_CAP_AGP 139 140 #define PCI_EXP_LNKCTL PCIE_LCSR 141 #define PCI_EXP_LNKCTL_HAWD PCIE_LCSR_HAWD 142 #define PCI_EXP_DEVSTA (PCIE_DCSR + 2) 143 #define PCI_EXP_DEVSTA_TRPND (PCIE_DCSR_TRANSACTION_PND >> 16) 144 #define PCI_EXP_LNKCTL2 PCIE_LCAP2 145 #define PCI_EXP_LNKCTL2_ENTER_COMP PCIE_LCSR2_ENT_COMPL 146 #define PCI_EXP_LNKCTL2_TX_MARGIN PCIE_LCSR2_TX_MARGIN 147 #define PCI_EXP_LNKCTL2_TLS PCIE_LCSR2_TGT_LSPEED 148 #define PCI_EXP_LNKCTL2_TLS_2_5GT PCIE_LCSR2_TGT_LSPEED_2_5G 149 #define PCI_EXP_LNKCTL2_TLS_5_0GT PCIE_LCSR2_TGT_LSPEED_5G 150 #define PCI_EXP_LNKCTL2_TLS_8_0GT PCIE_LCSR2_TGT_LSPEED_8G 151 #define PCI_EXP_LNKCAP PCIE_LCAP 152 #define PCI_EXP_LNKCAP_CLKPM PCIE_LCAP_CLOCK_PM 153 154 155 typedef int pci_power_t; 156 157 #define PCI_D0 0 158 #define PCI_D1 1 159 #define PCI_D2 2 160 #define PCI_D3hot 3 161 #define PCI_D3cold 4 162 163 #define __pci_iomem 164 165 struct pci_dev { 166 struct pci_attach_args pd_pa; 167 int pd_kludges; /* Gotta lose 'em... */ 168 #define NBPCI_KLUDGE_GET_MUMBLE 0x01 169 #define NBPCI_KLUDGE_MAP_ROM 0x02 170 bus_space_tag_t pd_rom_bst; 171 bus_space_handle_t pd_rom_bsh; 172 bus_size_t pd_rom_size; 173 bus_space_handle_t pd_rom_found_bsh; 174 bus_size_t pd_rom_found_size; 175 void *pd_rom_vaddr; 176 device_t pd_dev; 177 void *pd_drvdata; 178 struct { 179 pcireg_t type; 180 bus_addr_t addr; 181 bus_size_t size; 182 int flags; 183 bus_space_tag_t bst; 184 bus_space_handle_t bsh; 185 void __pci_iomem *kva; 186 bool mapped; 187 } pd_resources[PCI_NUM_RESOURCES]; 188 struct pci_conf_state *pd_saved_state; 189 struct acpi_devnode *pd_ad; 190 pci_intr_handle_t *pd_intr_handles; 191 unsigned pd_enablecnt; 192 193 /* Linx API only below */ 194 struct pci_bus *bus; 195 uint32_t devfn; 196 uint16_t vendor; 197 uint16_t device; 198 uint16_t subsystem_vendor; 199 uint16_t subsystem_device; 200 uint8_t revision; 201 uint32_t class; 202 bool msi_enabled; 203 bool no_64bit_msi; 204 }; 205 206 enum pci_bus_speed { 207 PCI_SPEED_UNKNOWN, 208 PCIE_SPEED_2_5GT, 209 PCIE_SPEED_5_0GT, 210 PCIE_SPEED_8_0GT, 211 PCIE_SPEED_16_0GT, 212 PCIE_SPEED_32_0GT, 213 PCIE_SPEED_64_0GT, 214 }; 215 216 /* 217 * Actually values from the Link Status register, bits 16-19. Don't use 218 * these as a bit-mask -- these are the only known, valid values. 219 */ 220 enum pcie_link_width { 221 PCIE_LNK_WIDTH_RESRV = 0, 222 PCIE_LNK_X1 = __BIT(0), 223 PCIE_LNK_X2 = __BIT(1), 224 PCIE_LNK_X4 = __BIT(2), 225 PCIE_LNK_X8 = __BIT(3), 226 PCIE_LNK_X12 = __BITS(2,3), 227 PCIE_LNK_X16 = __BIT(4), 228 PCIE_LNK_X32 = __BIT(5), 229 PCIE_LNK_WIDTH_UNKNOWN = __BITS(0, 7), 230 }; 231 232 #define PCIBIOS_MIN_MEM 0x100000 /* XXX bogus x86 kludge bollocks */ 233 234 #define __pci_rom_iomem 235 236 /* Namespace. */ 237 #define pci_bus_alloc_resource linux_pci_bus_alloc_resource 238 #define pci_bus_read_config_byte linux_pci_bus_read_config_byte 239 #define pci_bus_read_config_dword linux_pci_bus_read_config_dword 240 #define pci_bus_read_config_word linux_pci_bus_read_config_word 241 #define pci_bus_write_config_byte linux_pci_bus_write_config_byte 242 #define pci_bus_write_config_dword linux_pci_bus_write_config_dword 243 #define pci_bus_write_config_word linux_pci_bus_write_config_word 244 #define pci_clear_master linux_pci_clear_master 245 #define pci_dev_dev linux_pci_dev_dev 246 #define pci_dev_present linux_pci_dev_present 247 #define pci_dev_put linux_pci_dev_put 248 #define pci_disable_msi linux_pci_disable_msi 249 #define pci_disable_rom linux_pci_disable_rom 250 #define pci_dma_supported linux_pci_dma_supported 251 #define pci_domain_nr linux_pci_domain_nr 252 #define pci_enable_msi linux_pci_enable_msi 253 #define pci_enable_rom linux_pci_enable_rom 254 #define pci_find_capability linux_pci_find_capability 255 #define pci_get_class linux_pci_get_class 256 #define pci_get_domain_bus_and_slot linux_pci_get_domain_bus_and_slot 257 #define pci_get_drvdata linux_pci_get_drvdata 258 #define pci_iomap linux_pci_iomap 259 #define pci_iounmap linux_pci_iounmap 260 #define pci_is_pcie linux_pci_is_pcie 261 #define pci_is_root_bus linux_pci_is_root_bus 262 #define pci_is_thunderbolt_attached linux_pci_is_thunderbolt_attached 263 #define pci_map_rom linux_pci_map_rom 264 #define pci_name linux_pci_name 265 #define pci_platform_rom linux_pci_platform_rom 266 #define pci_read_config_byte linux_pci_read_config_byte 267 #define pci_read_config_dword linux_pci_read_config_dword 268 #define pci_read_config_word linux_pci_read_config_word 269 #define pci_release_region linux_pci_release_region 270 #define pci_release_regions linux_pci_release_regions 271 #define pci_request_region linux_pci_request_region 272 #define pci_request_regions linux_pci_request_regions 273 #define pci_resource_end linux_pci_resource_end 274 #define pci_resource_flags linux_pci_resource_flags 275 #define pci_resource_len linux_pci_resource_len 276 #define pci_resource_start linux_pci_resource_start 277 #define pci_restore_state linux_pci_restore_state 278 #define pci_save_state linux_pci_save_state 279 #define pci_set_drvdata linux_pci_set_drvdata 280 #define pci_set_master linux_pci_set_master 281 #define pci_unmap_rom linux_pci_unmap_rom 282 #define pci_write_config_byte linux_pci_write_config_byte 283 #define pci_write_config_dword linux_pci_write_config_dword 284 #define pci_write_config_word linux_pci_write_config_word 285 #define pcibios_align_resource linux_pcibios_align_resource 286 #define pcie_get_speed_cap linux_pcie_get_speed_cap 287 #define pcie_bandwidth_available linux_pcie_bandwidth_available 288 #define pcie_read_config_dword linux_pcie_capability_read_dword 289 #define pcie_read_config_word linux_pcie_capability_read_word 290 #define pcie_write_config_dword linux_pcie_capability_write_dword 291 #define pcie_write_config_word linux_pcie_capability_write_word 292 293 /* NetBSD local additions. */ 294 void linux_pci_dev_init(struct pci_dev *, device_t, device_t, 295 const struct pci_attach_args *, int); 296 void linux_pci_dev_destroy(struct pci_dev *); 297 298 /* NetBSD no-renames because use requires review. */ 299 int linux_pci_enable_device(struct pci_dev *); 300 void linux_pci_disable_device(struct pci_dev *); 301 302 bool pci_is_root_bus(struct pci_bus *); 303 int pci_domain_nr(struct pci_bus *); 304 305 device_t pci_dev_dev(struct pci_dev *); 306 void pci_set_drvdata(struct pci_dev *, void *); 307 void * pci_get_drvdata(struct pci_dev *); 308 const char * pci_name(struct pci_dev *); 309 310 int pci_find_capability(struct pci_dev *, int); 311 bool pci_is_pcie(struct pci_dev *); 312 bool pci_dma_supported(struct pci_dev *, uintmax_t); 313 bool pci_is_thunderbolt_attached(struct pci_dev *); 314 315 int pci_read_config_dword(struct pci_dev *, int, uint32_t *); 316 int pci_read_config_word(struct pci_dev *, int, uint16_t *); 317 int pci_read_config_byte(struct pci_dev *, int, uint8_t *); 318 int pci_write_config_dword(struct pci_dev *, int, uint32_t); 319 int pci_write_config_word(struct pci_dev *, int, uint16_t); 320 int pci_write_config_byte(struct pci_dev *, int, uint8_t); 321 322 int pcie_capability_read_dword(struct pci_dev *, int, uint32_t *); 323 int pcie_capability_read_word(struct pci_dev *, int, uint16_t *); 324 int pcie_capability_write_dword(struct pci_dev *, int, uint32_t); 325 int pcie_capability_write_word(struct pci_dev *, int, uint16_t); 326 327 int pci_bus_read_config_dword(struct pci_bus *, unsigned, int, 328 uint32_t *); 329 int pci_bus_read_config_word(struct pci_bus *, unsigned, int, 330 uint16_t *); 331 int pci_bus_read_config_byte(struct pci_bus *, unsigned, int, 332 uint8_t *); 333 int pci_bus_write_config_dword(struct pci_bus *, unsigned, int, 334 uint32_t); 335 int pci_bus_write_config_word(struct pci_bus *, unsigned, int, 336 uint16_t); 337 int pci_bus_write_config_byte(struct pci_bus *, unsigned, int, 338 uint8_t); 339 340 int pci_enable_msi(struct pci_dev *); 341 void pci_disable_msi(struct pci_dev *); 342 void pci_set_master(struct pci_dev *); 343 void pci_clear_master(struct pci_dev *); 344 345 int pcie_get_readrq(struct pci_dev *); 346 int pcie_set_readrq(struct pci_dev *, int); 347 348 bus_addr_t pcibios_align_resource(void *, const struct resource *, 349 bus_addr_t, bus_size_t); 350 int pci_bus_alloc_resource(struct pci_bus *, struct resource *, 351 bus_size_t, bus_size_t, bus_addr_t, int, 352 bus_addr_t (*)(void *, const struct resource *, bus_addr_t, 353 bus_size_t), struct pci_dev *); 354 355 /* XXX Kludges only -- do not use without checking the implementation! */ 356 struct pci_dev *pci_get_domain_bus_and_slot(int, int, int); 357 struct pci_dev *pci_get_class(uint32_t, struct pci_dev *); /* i915 kludge */ 358 int pci_dev_present(const struct pci_device_id *); 359 void pci_dev_put(struct pci_dev *); 360 361 void __pci_rom_iomem * 362 pci_map_rom(struct pci_dev *, size_t *); 363 void __pci_rom_iomem * 364 pci_platform_rom(struct pci_dev *, size_t *); 365 void pci_unmap_rom(struct pci_dev *, void __pci_rom_iomem *); 366 int pci_enable_rom(struct pci_dev *); 367 void pci_disable_rom(struct pci_dev *); 368 369 int pci_request_regions(struct pci_dev *, const char *); 370 void pci_release_regions(struct pci_dev *); 371 int pci_request_region(struct pci_dev *, int, const char *); 372 void pci_release_region(struct pci_dev *, int); 373 374 bus_addr_t pci_resource_start(struct pci_dev *, unsigned); 375 bus_size_t pci_resource_len(struct pci_dev *, unsigned); 376 bus_addr_t pci_resource_end(struct pci_dev *, unsigned); 377 int pci_resource_flags(struct pci_dev *, unsigned); 378 379 void __pci_iomem * 380 pci_iomap(struct pci_dev *, unsigned, bus_size_t); 381 void pci_iounmap(struct pci_dev *, void __pci_iomem *); 382 383 void pci_save_state(struct pci_dev *); 384 void pci_restore_state(struct pci_dev *); 385 386 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 387 unsigned pcie_bandwidth_available(struct pci_dev *dev, 388 struct pci_dev **limiting_dev, 389 enum pci_bus_speed *speed, 390 enum pcie_link_width *width); 391 392 static inline bool 393 dev_is_pci(struct device *dev) 394 { 395 struct device *parent = device_parent(dev); 396 397 return parent && device_is_a(parent, "pci"); 398 } 399 400 #endif /* _LINUX_PCI_H_ */ 401