xref: /netbsd-src/sys/external/bsd/drm2/include/linux/pci.h (revision aef5eb5f59cdfe8314f1b5f78ac04eb144e44010)
1 /*	$NetBSD: pci.h,v 1.54 2022/09/20 23:01:42 mrg Exp $	*/
2 
3 /*-
4  * Copyright (c) 2013 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Taylor R. Campbell.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _LINUX_PCI_H_
33 #define _LINUX_PCI_H_
34 
35 #ifdef _KERNEL_OPT
36 #include "acpica.h"
37 #endif
38 
39 #include <sys/types.h>
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/cdefs.h>
43 #include <sys/kmem.h>
44 #include <sys/systm.h>
45 
46 #include <machine/limits.h>
47 
48 #include <dev/pci/pcidevs.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/agpvar.h>
52 
53 #include <linux/device.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/errno.h>
56 #include <linux/io.h>
57 #include <linux/interrupt.h>
58 #include <linux/ioport.h>
59 #include <linux/kernel.h>
60 
61 struct acpi_devnode;
62 struct pci_driver;
63 
64 struct pci_bus {
65 	/* NetBSD private members */
66 	pci_chipset_tag_t	pb_pc;
67 	device_t		pb_dev;
68 
69 	/* Linux API */
70 	u_int			number;
71 };
72 
73 struct pci_device_id {
74 	uint32_t	vendor;
75 	uint32_t	device;
76 	uint32_t	subvendor;
77 	uint32_t	subdevice;
78 	uint32_t	class;
79 	uint32_t	class_mask;
80 	unsigned long	driver_data;
81 };
82 
83 #define	PCI_DEVICE(VENDOR, DEVICE)					      \
84 	.vendor = (VENDOR),						      \
85 	.device = (DEVICE)
86 
87 #define	PCI_ANY_ID		(~0)
88 
89 #define	PCI_BASE_CLASS_DISPLAY	PCI_CLASS_DISPLAY
90 
91 #define	PCI_CLASS_DISPLAY_VGA						\
92 	((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA)
93 CTASSERT(PCI_CLASS_DISPLAY_VGA == 0x0300);
94 
95 #define	PCI_CLASS_DISPLAY_OTHER						\
96 	((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC)
97 CTASSERT(PCI_CLASS_DISPLAY_OTHER == 0x0380);
98 
99 #define	PCI_CLASS_BRIDGE_ISA						\
100 	((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA)
101 CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601);
102 
103 /* XXX This is getting silly...  */
104 #define	PCI_VENDOR_ID_APPLE	PCI_VENDOR_APPLE
105 #define	PCI_VENDOR_ID_ASUSTEK	PCI_VENDOR_ASUSTEK
106 #define	PCI_VENDOR_ID_ATI	PCI_VENDOR_ATI
107 #define	PCI_VENDOR_ID_DELL	PCI_VENDOR_DELL
108 #define	PCI_VENDOR_ID_IBM	PCI_VENDOR_IBM
109 #define	PCI_VENDOR_ID_HP	PCI_VENDOR_HP
110 #define	PCI_VENDOR_ID_INTEL	PCI_VENDOR_INTEL
111 #define	PCI_VENDOR_ID_NVIDIA	PCI_VENDOR_NVIDIA
112 #define	PCI_VENDOR_ID_SI	PCI_VENDOR_SIS
113 #define	PCI_VENDOR_ID_SONY	PCI_VENDOR_SONY
114 #define	PCI_VENDOR_ID_VIA	PCI_VENDOR_VIATECH
115 
116 #define	PCI_SUBVENDOR_ID_REDHAT_QUMRANET	0x1af4
117 
118 #define	PCI_DEVICE_ID_ATI_RADEON_QY	PCI_PRODUCT_ATI_RADEON_RV100_QY
119 
120 #define	PCI_SUBDEVICE_ID_QEMU		0x1100
121 
122 #define	PCI_DEVFN(DEV, FN)						\
123 	(__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2)))
124 #define	PCI_SLOT(DEVFN)		((int)__SHIFTOUT((DEVFN), __BITS(3, 7)))
125 #define	PCI_FUNC(DEVFN)		((int)__SHIFTOUT((DEVFN), __BITS(0, 2)))
126 
127 #define	PCI_DEVID(BUS, DEVFN)						      \
128 	(__SHIFTIN((BUS), __BITS(15, 8)) | __SHIFTIN((DEVFN), __BITS(7, 0)))
129 #define	PCI_BUS_NUM(DEVID)	((int)__SHIFTOUT((DEVID), __BITS(15,8)))
130 
131 #define	PCI_NUM_RESOURCES	((PCI_MAPREG_END - PCI_MAPREG_START) / 4)
132 #define	DEVICE_COUNT_RESOURCE	PCI_NUM_RESOURCES
133 
134 #define	PCI_CAP_ID_AGP	PCI_CAP_AGP
135 
136 typedef int pci_power_t;
137 
138 #define	PCI_D0		0
139 #define	PCI_D1		1
140 #define	PCI_D2		2
141 #define	PCI_D3hot	3
142 #define	PCI_D3cold	4
143 
144 #define	__pci_iomem
145 
146 struct pci_dev {
147 	struct pci_attach_args	pd_pa;
148 	int			pd_kludges;	/* Gotta lose 'em...  */
149 #define	NBPCI_KLUDGE_GET_MUMBLE	0x01
150 #define	NBPCI_KLUDGE_MAP_ROM	0x02
151 	bus_space_tag_t		pd_rom_bst;
152 	bus_space_handle_t	pd_rom_bsh;
153 	bus_size_t		pd_rom_size;
154 	bus_space_handle_t	pd_rom_found_bsh;
155 	bus_size_t		pd_rom_found_size;
156 	void			*pd_rom_vaddr;
157 	device_t		pd_dev;
158 	void			*pd_drvdata;
159 	struct {
160 		pcireg_t		type;
161 		bus_addr_t		addr;
162 		bus_size_t		size;
163 		int			flags;
164 		bus_space_tag_t		bst;
165 		bus_space_handle_t	bsh;
166 		void __pci_iomem	*kva;
167 		bool			mapped;
168 	}			pd_resources[PCI_NUM_RESOURCES];
169 	struct pci_conf_state	*pd_saved_state;
170 	struct acpi_devnode	*pd_ad;
171 	pci_intr_handle_t	*pd_intr_handles;
172 	unsigned		pd_enablecnt;
173 
174 	/* Linx API only below */
175 	struct pci_bus		*bus;
176 	uint32_t		devfn;
177 	uint16_t		vendor;
178 	uint16_t		device;
179 	uint16_t		subsystem_vendor;
180 	uint16_t		subsystem_device;
181 	uint8_t			revision;
182 	uint32_t		class;
183 	bool			msi_enabled;
184 	bool			no_64bit_msi;
185 };
186 
187 enum pci_bus_speed {
188 	PCI_SPEED_UNKNOWN,
189 	PCIE_SPEED_2_5GT,
190 	PCIE_SPEED_5_0GT,
191 	PCIE_SPEED_8_0GT,
192 	PCIE_SPEED_16_0GT,
193 	PCIE_SPEED_32_0GT,
194 	PCIE_SPEED_64_0GT,
195 };
196 
197 /*
198  * Actually values from the Link Status register, bits 16-19.  Don't use
199  * these as a bit-mask -- these are the only known, valid values.
200  */
201 enum pcie_link_width {
202 	PCIE_LNK_WIDTH_RESRV   = 0,
203 	PCIE_LNK_X1            = __BIT(0),
204 	PCIE_LNK_X2            = __BIT(1),
205 	PCIE_LNK_X4            = __BIT(2),
206 	PCIE_LNK_X8            = __BIT(3),
207 	PCIE_LNK_X12           = __BITS(2,3),
208 	PCIE_LNK_X16           = __BIT(4),
209 	PCIE_LNK_X32           = __BIT(5),
210 	PCIE_LNK_WIDTH_UNKNOWN = __BITS(0, 7),
211 };
212 
213 #define	PCIBIOS_MIN_MEM	0x100000	/* XXX bogus x86 kludge bollocks */
214 
215 #define	__pci_rom_iomem
216 
217 /* Namespace.  */
218 #define	pci_bus_alloc_resource		linux_pci_bus_alloc_resource
219 #define	pci_bus_read_config_byte	linux_pci_bus_read_config_byte
220 #define	pci_bus_read_config_dword	linux_pci_bus_read_config_dword
221 #define	pci_bus_read_config_word	linux_pci_bus_read_config_word
222 #define	pci_bus_write_config_byte	linux_pci_bus_write_config_byte
223 #define	pci_bus_write_config_dword	linux_pci_bus_write_config_dword
224 #define	pci_bus_write_config_word	linux_pci_bus_write_config_word
225 #define	pci_clear_master		linux_pci_clear_master
226 #define	pci_dev_dev			linux_pci_dev_dev
227 #define	pci_dev_present			linux_pci_dev_present
228 #define	pci_dev_put			linux_pci_dev_put
229 #define	pci_disable_msi			linux_pci_disable_msi
230 #define	pci_disable_rom			linux_pci_disable_rom
231 #define	pci_dma_supported		linux_pci_dma_supported
232 #define	pci_domain_nr			linux_pci_domain_nr
233 #define	pci_enable_msi			linux_pci_enable_msi
234 #define	pci_enable_rom			linux_pci_enable_rom
235 #define	pci_find_capability		linux_pci_find_capability
236 #define	pci_get_class			linux_pci_get_class
237 #define	pci_get_domain_bus_and_slot	linux_pci_get_domain_bus_and_slot
238 #define	pci_get_drvdata			linux_pci_get_drvdata
239 #define	pci_iomap			linux_pci_iomap
240 #define	pci_iounmap			linux_pci_iounmap
241 #define	pci_is_pcie			linux_pci_is_pcie
242 #define	pci_is_root_bus			linux_pci_is_root_bus
243 #define	pci_is_thunderbolt_attached	linux_pci_is_thunderbolt_attached
244 #define	pci_map_rom			linux_pci_map_rom
245 #define	pci_name			linux_pci_name
246 #define	pci_platform_rom		linux_pci_platform_rom
247 #define	pci_read_config_byte		linux_pci_read_config_byte
248 #define	pci_read_config_dword		linux_pci_read_config_dword
249 #define	pci_read_config_word		linux_pci_read_config_word
250 #define	pci_resource_end		linux_pci_resource_end
251 #define	pci_resource_flags		linux_pci_resource_flags
252 #define	pci_resource_len		linux_pci_resource_len
253 #define	pci_resource_start		linux_pci_resource_start
254 #define	pci_restore_state		linux_pci_restore_state
255 #define	pci_save_state			linux_pci_save_state
256 #define	pci_set_drvdata			linux_pci_set_drvdata
257 #define	pci_set_master			linux_pci_set_master
258 #define	pci_unmap_rom			linux_pci_unmap_rom
259 #define	pci_write_config_byte		linux_pci_write_config_byte
260 #define	pci_write_config_dword		linux_pci_write_config_dword
261 #define	pci_write_config_word		linux_pci_write_config_word
262 #define	pcibios_align_resource		linux_pcibios_align_resource
263 #define	pcie_get_speed_cap		linux_pcie_get_speed_cap
264 #define	pcie_bandwidth_available	linux_pcie_bandwidth_available
265 
266 /* NetBSD local additions.  */
267 void		linux_pci_dev_init(struct pci_dev *, device_t, device_t,
268 		    const struct pci_attach_args *, int);
269 void		linux_pci_dev_destroy(struct pci_dev *);
270 
271 /* NetBSD no-renames because use requires review.  */
272 int		linux_pci_enable_device(struct pci_dev *);
273 void		linux_pci_disable_device(struct pci_dev *);
274 
275 bool		pci_is_root_bus(struct pci_bus *);
276 int		pci_domain_nr(struct pci_bus *);
277 
278 device_t	pci_dev_dev(struct pci_dev *);
279 void		pci_set_drvdata(struct pci_dev *, void *);
280 void *		pci_get_drvdata(struct pci_dev *);
281 const char *	pci_name(struct pci_dev *);
282 
283 int		pci_find_capability(struct pci_dev *, int);
284 bool		pci_is_pcie(struct pci_dev *);
285 bool		pci_dma_supported(struct pci_dev *, uintmax_t);
286 bool		pci_is_thunderbolt_attached(struct pci_dev *);
287 
288 int		pci_read_config_dword(struct pci_dev *, int, uint32_t *);
289 int		pci_read_config_word(struct pci_dev *, int, uint16_t *);
290 int		pci_read_config_byte(struct pci_dev *, int, uint8_t *);
291 int		pci_write_config_dword(struct pci_dev *, int, uint32_t);
292 int		pci_write_config_word(struct pci_dev *, int, uint16_t);
293 int		pci_write_config_byte(struct pci_dev *, int, uint8_t);
294 
295 int		pci_bus_read_config_dword(struct pci_bus *, unsigned, int,
296 		    uint32_t *);
297 int		pci_bus_read_config_word(struct pci_bus *, unsigned, int,
298 		    uint16_t *);
299 int		pci_bus_read_config_byte(struct pci_bus *, unsigned, int,
300 		    uint8_t *);
301 int		pci_bus_write_config_dword(struct pci_bus *, unsigned, int,
302 		    uint32_t);
303 int		pci_bus_write_config_word(struct pci_bus *, unsigned, int,
304 		    uint16_t);
305 int		pci_bus_write_config_byte(struct pci_bus *, unsigned, int,
306 		    uint8_t);
307 
308 int		pci_enable_msi(struct pci_dev *);
309 void		pci_disable_msi(struct pci_dev *);
310 void		pci_set_master(struct pci_dev *);
311 void		pci_clear_master(struct pci_dev *);
312 
313 bus_addr_t	pcibios_align_resource(void *, const struct resource *,
314 		    bus_addr_t, bus_size_t);
315 int		pci_bus_alloc_resource(struct pci_bus *, struct resource *,
316 		    bus_size_t, bus_size_t, bus_addr_t, int,
317 		    bus_addr_t (*)(void *, const struct resource *, bus_addr_t,
318 			bus_size_t), struct pci_dev *);
319 
320 /* XXX Kludges only -- do not use without checking the implementation!  */
321 struct pci_dev *pci_get_domain_bus_and_slot(int, int, int);
322 struct pci_dev *pci_get_class(uint32_t, struct pci_dev *); /* i915 kludge */
323 int		pci_dev_present(const struct pci_device_id *);
324 void		pci_dev_put(struct pci_dev *);
325 
326 void __pci_rom_iomem *
327 		pci_map_rom(struct pci_dev *, size_t *);
328 void __pci_rom_iomem *
329 		pci_platform_rom(struct pci_dev *, size_t *);
330 void		pci_unmap_rom(struct pci_dev *, void __pci_rom_iomem *);
331 int		pci_enable_rom(struct pci_dev *);
332 void		pci_disable_rom(struct pci_dev *);
333 
334 bus_addr_t	pci_resource_start(struct pci_dev *, unsigned);
335 bus_size_t	pci_resource_len(struct pci_dev *, unsigned);
336 bus_addr_t	pci_resource_end(struct pci_dev *, unsigned);
337 int		pci_resource_flags(struct pci_dev *, unsigned);
338 
339 void __pci_iomem *
340 		pci_iomap(struct pci_dev *, unsigned, bus_size_t);
341 void		pci_iounmap(struct pci_dev *, void __pci_iomem *);
342 
343 void		pci_save_state(struct pci_dev *);
344 void		pci_restore_state(struct pci_dev *);
345 
346 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
347 unsigned	pcie_bandwidth_available(struct pci_dev *dev,
348 					 struct pci_dev **limiting_dev,
349 					 enum pci_bus_speed *speed,
350 					 enum pcie_link_width *width);
351 
352 static inline bool
353 dev_is_pci(struct device *dev)
354 {
355 	struct device *parent = device_parent(dev);
356 
357 	return parent && device_is_a(parent, "pci");
358 }
359 
360 #endif  /* _LINUX_PCI_H_ */
361