1 /* $NetBSD: drm_edid.h,v 1.2 2018/08/27 04:58:37 riastradh Exp $ */ 2 3 /* 4 * Copyright © 2007-2008 Intel Corporation 5 * Jesse Barnes <jesse.barnes@intel.com> 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 #ifndef __DRM_EDID_H__ 26 #define __DRM_EDID_H__ 27 28 #include <linux/types.h> 29 30 #define EDID_LENGTH 128 31 #define DDC_ADDR 0x50 32 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 33 34 #define CEA_EXT 0x02 35 #define VTB_EXT 0x10 36 #define DI_EXT 0x40 37 #define LS_EXT 0x50 38 #define MI_EXT 0x60 39 #define DISPLAYID_EXT 0x70 40 41 struct est_timings { 42 u8 t1; 43 u8 t2; 44 u8 mfg_rsvd; 45 } __attribute__((packed)); 46 47 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 48 #define EDID_TIMING_ASPECT_SHIFT 6 49 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 50 51 /* need to add 60 */ 52 #define EDID_TIMING_VFREQ_SHIFT 0 53 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 54 55 struct std_timing { 56 u8 hsize; /* need to multiply by 8 then add 248 */ 57 u8 vfreq_aspect; 58 } __attribute__((packed)); 59 60 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 61 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 62 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 63 #define DRM_EDID_PT_STEREO (1 << 5) 64 #define DRM_EDID_PT_INTERLACED (1 << 7) 65 66 /* If detailed data is pixel timing */ 67 struct detailed_pixel_timing { 68 u8 hactive_lo; 69 u8 hblank_lo; 70 u8 hactive_hblank_hi; 71 u8 vactive_lo; 72 u8 vblank_lo; 73 u8 vactive_vblank_hi; 74 u8 hsync_offset_lo; 75 u8 hsync_pulse_width_lo; 76 u8 vsync_offset_pulse_width_lo; 77 u8 hsync_vsync_offset_pulse_width_hi; 78 u8 width_mm_lo; 79 u8 height_mm_lo; 80 u8 width_height_mm_hi; 81 u8 hborder; 82 u8 vborder; 83 u8 misc; 84 } __attribute__((packed)); 85 86 /* If it's not pixel timing, it'll be one of the below */ 87 struct detailed_data_string { 88 u8 str[13]; 89 } __attribute__((packed)); 90 91 struct detailed_data_monitor_range { 92 u8 min_vfreq; 93 u8 max_vfreq; 94 u8 min_hfreq_khz; 95 u8 max_hfreq_khz; 96 u8 pixel_clock_mhz; /* need to multiply by 10 */ 97 u8 flags; 98 union { 99 struct { 100 u8 reserved; 101 u8 hfreq_start_khz; /* need to multiply by 2 */ 102 u8 c; /* need to divide by 2 */ 103 __le16 m; 104 u8 k; 105 u8 j; /* need to divide by 2 */ 106 } __attribute__((packed)) gtf2; 107 struct { 108 u8 version; 109 u8 data1; /* high 6 bits: extra clock resolution */ 110 u8 data2; /* plus low 2 of above: max hactive */ 111 u8 supported_aspects; 112 u8 flags; /* preferred aspect and blanking support */ 113 u8 supported_scalings; 114 u8 preferred_refresh; 115 } __attribute__((packed)) cvt; 116 } formula; 117 } __attribute__((packed)); 118 119 struct detailed_data_wpindex { 120 u8 white_yx_lo; /* Lower 2 bits each */ 121 u8 white_x_hi; 122 u8 white_y_hi; 123 u8 gamma; /* need to divide by 100 then add 1 */ 124 } __attribute__((packed)); 125 126 struct detailed_data_color_point { 127 u8 windex1; 128 u8 wpindex1[3]; 129 u8 windex2; 130 u8 wpindex2[3]; 131 } __attribute__((packed)); 132 133 struct cvt_timing { 134 u8 code[3]; 135 } __attribute__((packed)); 136 137 struct detailed_non_pixel { 138 u8 pad1; 139 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 140 fb=color point data, fa=standard timing data, 141 f9=undefined, f8=mfg. reserved */ 142 u8 pad2; 143 union { 144 struct detailed_data_string str; 145 struct detailed_data_monitor_range range; 146 struct detailed_data_wpindex color; 147 struct std_timing timings[6]; 148 struct cvt_timing cvt[4]; 149 } data; 150 } __attribute__((packed)); 151 152 #define EDID_DETAIL_EST_TIMINGS 0xf7 153 #define EDID_DETAIL_CVT_3BYTE 0xf8 154 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 155 #define EDID_DETAIL_STD_MODES 0xfa 156 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 157 #define EDID_DETAIL_MONITOR_NAME 0xfc 158 #define EDID_DETAIL_MONITOR_RANGE 0xfd 159 #define EDID_DETAIL_MONITOR_STRING 0xfe 160 #define EDID_DETAIL_MONITOR_SERIAL 0xff 161 162 struct detailed_timing { 163 __le16 pixel_clock; /* need to multiply by 10 KHz */ 164 union { 165 struct detailed_pixel_timing pixel_data; 166 struct detailed_non_pixel other_data; 167 } data; 168 } __attribute__((packed)); 169 170 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 171 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 172 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 173 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 174 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 175 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 176 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 177 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 178 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 179 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 180 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 181 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 182 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 183 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 184 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 185 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 186 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 187 #define DRM_EDID_DIGITAL_TYPE_DVI (1) 188 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 189 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 190 #define DRM_EDID_DIGITAL_TYPE_MDDI (4) 191 #define DRM_EDID_DIGITAL_TYPE_DP (5) 192 193 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 194 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 195 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 196 /* If analog */ 197 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 198 /* If digital */ 199 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 200 #define DRM_EDID_FEATURE_RGB (0 << 3) 201 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 202 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 203 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 204 205 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 206 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 207 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 208 209 #define DRM_EDID_HDMI_DC_48 (1 << 6) 210 #define DRM_EDID_HDMI_DC_36 (1 << 5) 211 #define DRM_EDID_HDMI_DC_30 (1 << 4) 212 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 213 214 /* ELD Header Block */ 215 #define DRM_ELD_HEADER_BLOCK_SIZE 4 216 217 #define DRM_ELD_VER 0 218 # define DRM_ELD_VER_SHIFT 3 219 # define DRM_ELD_VER_MASK (0x1f << 3) 220 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 221 # define DRM_ELD_VER_CANNED (0x1f << 3) 222 223 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 224 225 /* ELD Baseline Block for ELD_Ver == 2 */ 226 #define DRM_ELD_CEA_EDID_VER_MNL 4 227 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 228 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 229 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 230 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 231 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 232 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 233 # define DRM_ELD_MNL_SHIFT 0 234 # define DRM_ELD_MNL_MASK (0x1f << 0) 235 236 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 237 # define DRM_ELD_SAD_COUNT_SHIFT 4 238 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 239 # define DRM_ELD_CONN_TYPE_SHIFT 2 240 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 241 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 242 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 243 # define DRM_ELD_SUPPORTS_AI (1 << 1) 244 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 245 246 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 247 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 248 249 #define DRM_ELD_SPEAKER 7 250 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 251 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 252 # define DRM_ELD_SPEAKER_RC (1 << 4) 253 # define DRM_ELD_SPEAKER_RLR (1 << 3) 254 # define DRM_ELD_SPEAKER_FC (1 << 2) 255 # define DRM_ELD_SPEAKER_LFE (1 << 1) 256 # define DRM_ELD_SPEAKER_FLR (1 << 0) 257 258 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 259 # define DRM_ELD_PORT_ID_LEN 8 260 261 #define DRM_ELD_MANUFACTURER_NAME0 16 262 #define DRM_ELD_MANUFACTURER_NAME1 17 263 264 #define DRM_ELD_PRODUCT_CODE0 18 265 #define DRM_ELD_PRODUCT_CODE1 19 266 267 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 268 269 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 270 271 struct edid { 272 u8 header[8]; 273 /* Vendor & product info */ 274 u8 mfg_id[2]; 275 u8 prod_code[2]; 276 u32 serial; /* FIXME: byte order */ 277 u8 mfg_week; 278 u8 mfg_year; 279 /* EDID version */ 280 u8 version; 281 u8 revision; 282 /* Display info: */ 283 u8 input; 284 u8 width_cm; 285 u8 height_cm; 286 u8 gamma; 287 u8 features; 288 /* Color characteristics */ 289 u8 red_green_lo; 290 u8 black_white_lo; 291 u8 red_x; 292 u8 red_y; 293 u8 green_x; 294 u8 green_y; 295 u8 blue_x; 296 u8 blue_y; 297 u8 white_x; 298 u8 white_y; 299 /* Est. timings and mfg rsvd timings*/ 300 struct est_timings established_timings; 301 /* Standard timings 1-8*/ 302 struct std_timing standard_timings[8]; 303 /* Detailing timings 1-4 */ 304 struct detailed_timing detailed_timings[4]; 305 /* Number of 128 byte ext. blocks */ 306 u8 extensions; 307 /* Checksum */ 308 u8 checksum; 309 } __attribute__((packed)); 310 311 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 312 313 /* Short Audio Descriptor */ 314 struct cea_sad { 315 u8 format; 316 u8 channels; /* max number of channels - 1 */ 317 u8 freq; 318 u8 byte2; /* meaning depends on format */ 319 }; 320 321 struct drm_encoder; 322 struct drm_connector; 323 struct drm_display_mode; 324 struct hdmi_avi_infoframe; 325 struct hdmi_vendor_infoframe; 326 327 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 328 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); 329 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); 330 int drm_av_sync_delay(struct drm_connector *connector, 331 const struct drm_display_mode *mode); 332 struct drm_connector *drm_select_eld(struct drm_encoder *encoder); 333 int drm_load_edid_firmware(struct drm_connector *connector); 334 335 int 336 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 337 const struct drm_display_mode *mode); 338 int 339 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 340 const struct drm_display_mode *mode); 341 342 /** 343 * drm_eld_mnl - Get ELD monitor name length in bytes. 344 * @eld: pointer to an eld memory structure with mnl set 345 */ 346 static inline int drm_eld_mnl(const uint8_t *eld) 347 { 348 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 349 } 350 351 /** 352 * drm_eld_sad - Get ELD SAD structures. 353 * @eld: pointer to an eld memory structure with sad_count set 354 */ 355 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 356 { 357 unsigned int ver, mnl; 358 359 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 360 if (ver != 2 && ver != 31) 361 return NULL; 362 363 mnl = drm_eld_mnl(eld); 364 if (mnl > 16) 365 return NULL; 366 367 return eld + DRM_ELD_CEA_SAD(mnl, 0); 368 } 369 370 /** 371 * drm_eld_sad_count - Get ELD SAD count. 372 * @eld: pointer to an eld memory structure with sad_count set 373 */ 374 static inline int drm_eld_sad_count(const uint8_t *eld) 375 { 376 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 377 DRM_ELD_SAD_COUNT_SHIFT; 378 } 379 380 /** 381 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 382 * @eld: pointer to an eld memory structure with mnl and sad_count set 383 * 384 * This is a helper for determining the payload size of the baseline block, in 385 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 386 */ 387 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 388 { 389 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 390 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 391 } 392 393 /** 394 * drm_eld_size - Get ELD size in bytes 395 * @eld: pointer to a complete eld memory structure 396 * 397 * The returned value does not include the vendor block. It's vendor specific, 398 * and comprises of the remaining bytes in the ELD memory buffer after 399 * drm_eld_size() bytes of header and baseline block. 400 * 401 * The returned value is guaranteed to be a multiple of 4. 402 */ 403 static inline int drm_eld_size(const uint8_t *eld) 404 { 405 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 406 } 407 408 struct edid *drm_do_get_edid(struct drm_connector *connector, 409 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 410 size_t len), 411 void *data); 412 413 #endif /* __DRM_EDID_H__ */ 414