1 /* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro 2 * 3 * Copyright 2005 Thomas Hellstrom. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Thomas Hellstrom. 27 * Register info from Digeo Inc. 28 */ 29 30 #ifndef _VIA_DMABLIT_H 31 #define _VIA_DMABLIT_H 32 33 #include <linux/dma-mapping.h> 34 35 #define VIA_NUM_BLIT_ENGINES 2 36 #define VIA_NUM_BLIT_SLOTS 8 37 38 struct _drm_via_descriptor; 39 40 typedef struct _drm_via_sg_info { 41 #ifdef __NetBSD__ 42 bus_dmamap_t dmamap; 43 #else 44 struct page **pages; 45 #endif 46 unsigned long num_pages; 47 #ifdef __NetBSD__ 48 bus_dma_segment_t *desc_segs; 49 int num_desc_segs; 50 void *desc_kva; 51 bus_dmamap_t desc_dmamap; 52 #endif 53 struct _drm_via_descriptor **desc_pages; 54 int num_desc_pages; 55 int num_desc; 56 #ifdef __NetBSD__ 57 enum { DMA_FROM_DEVICE, DMA_TO_DEVICE } direction; 58 #else 59 enum dma_data_direction direction; 60 #endif 61 dma_addr_t chain_start; 62 uint32_t free_on_sequence; 63 unsigned int descriptors_per_page; 64 int aborted; 65 enum { 66 dr_via_device_mapped, 67 dr_via_desc_pages_alloc, 68 dr_via_pages_locked, 69 dr_via_pages_alloc, 70 dr_via_sg_init 71 } state; 72 } drm_via_sg_info_t; 73 74 typedef struct _drm_via_blitq { 75 struct drm_device *dev; 76 uint32_t cur_blit_handle; 77 uint32_t done_blit_handle; 78 unsigned serviced; 79 unsigned head; 80 unsigned cur; 81 unsigned num_free; 82 unsigned num_outstanding; 83 unsigned long end; 84 int aborting; 85 int is_active; 86 drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; 87 spinlock_t blit_lock; 88 #ifdef __NetBSD__ 89 drm_waitqueue_t blit_queue[VIA_NUM_BLIT_SLOTS]; 90 drm_waitqueue_t busy_queue; 91 #else 92 wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; 93 wait_queue_head_t busy_queue; 94 #endif 95 struct work_struct wq; 96 struct timer_list poll_timer; 97 } drm_via_blitq_t; 98 99 100 /* 101 * PCI DMA Registers 102 * Channels 2 & 3 don't seem to be implemented in hardware. 103 */ 104 105 #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ 106 #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ 107 #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ 108 #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ 109 110 #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ 111 #define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ 112 #define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ 113 #define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ 114 115 #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ 116 #define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ 117 #define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ 118 #define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ 119 120 #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ 121 #define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ 122 #define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ 123 #define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ 124 125 #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ 126 #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ 127 #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ 128 #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ 129 130 #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ 131 #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ 132 #define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ 133 #define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ 134 135 #define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ 136 137 /* Define for DMA engine */ 138 /* DPR */ 139 #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 140 #define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ 141 #define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ 142 143 /* MR */ 144 #define VIA_DMA_MR_CM (1<<0) /* chaining mode */ 145 #define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ 146 #define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ 147 148 /* CSR */ 149 #define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ 150 #define VIA_DMA_CSR_TS (1<<1) /* transfer start */ 151 #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ 152 #define VIA_DMA_CSR_TD (1<<3) /* transfer done */ 153 #define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ 154 #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 155 156 157 158 #endif 159