1 /* $NetBSD: si_dpm.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __SI_DPM_H__ 26 #define __SI_DPM_H__ 27 28 #include "ni_dpm.h" 29 #include "sislands_smc.h" 30 31 enum si_cac_config_reg_type 32 { 33 SISLANDS_CACCONFIG_MMR = 0, 34 SISLANDS_CACCONFIG_CGIND, 35 SISLANDS_CACCONFIG_MAX 36 }; 37 38 struct si_cac_config_reg 39 { 40 u32 offset; 41 u32 mask; 42 u32 shift; 43 u32 value; 44 enum si_cac_config_reg_type type; 45 }; 46 47 struct si_powertune_data 48 { 49 u32 cac_window; 50 u32 l2_lta_window_size_default; 51 u8 lts_truncate_default; 52 u8 shift_n_default; 53 u8 operating_temp; 54 struct ni_leakage_coeffients leakage_coefficients; 55 u32 fixed_kt; 56 u32 lkge_lut_v0_percent; 57 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; 58 bool enable_powertune_by_default; 59 }; 60 61 struct si_dyn_powertune_data 62 { 63 u32 cac_leakage; 64 s32 leakage_minimum_temperature; 65 u32 wintime; 66 u32 l2_lta_window_size; 67 u8 lts_truncate; 68 u8 shift_n; 69 u8 dc_pwr_value; 70 bool disable_uvd_powertune; 71 }; 72 73 struct si_dte_data 74 { 75 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 76 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 77 u32 k; 78 u32 t0; 79 u32 max_t; 80 u8 window_size; 81 u8 temp_select; 82 u8 dte_mode; 83 u8 tdep_count; 84 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 85 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 86 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 87 u32 t_threshold; 88 bool enable_dte_by_default; 89 }; 90 91 struct si_clock_registers { 92 u32 cg_spll_func_cntl; 93 u32 cg_spll_func_cntl_2; 94 u32 cg_spll_func_cntl_3; 95 u32 cg_spll_func_cntl_4; 96 u32 cg_spll_spread_spectrum; 97 u32 cg_spll_spread_spectrum_2; 98 u32 dll_cntl; 99 u32 mclk_pwrmgt_cntl; 100 u32 mpll_ad_func_cntl; 101 u32 mpll_dq_func_cntl; 102 u32 mpll_func_cntl; 103 u32 mpll_func_cntl_1; 104 u32 mpll_func_cntl_2; 105 u32 mpll_ss1; 106 u32 mpll_ss2; 107 }; 108 109 struct si_mc_reg_entry { 110 u32 mclk_max; 111 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 112 }; 113 114 struct si_mc_reg_table { 115 u8 last; 116 u8 num_entries; 117 u16 valid_flag; 118 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 119 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 120 }; 121 122 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 123 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 124 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2 125 #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3 126 127 struct si_leakage_voltage_entry 128 { 129 u16 voltage; 130 u16 leakage_index; 131 }; 132 133 #define SISLANDS_LEAKAGE_INDEX0 0xff01 134 #define SISLANDS_MAX_LEAKAGE_COUNT 4 135 136 struct si_leakage_voltage 137 { 138 u16 count; 139 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; 140 }; 141 142 #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5 143 144 struct si_ulv_param { 145 bool supported; 146 u32 cg_ulv_control; 147 u32 cg_ulv_parameter; 148 u32 volt_change_delay; 149 struct rv7xx_pl pl; 150 bool one_pcie_lane_in_ulv; 151 }; 152 153 struct si_power_info { 154 /* must be first! */ 155 struct ni_power_info ni; 156 struct si_clock_registers clock_registers; 157 struct si_mc_reg_table mc_reg_table; 158 struct atom_voltage_table mvdd_voltage_table; 159 struct atom_voltage_table vddc_phase_shed_table; 160 struct si_leakage_voltage leakage_voltage; 161 u16 mvdd_bootup_value; 162 struct si_ulv_param ulv; 163 u32 max_cu; 164 /* pcie gen */ 165 enum radeon_pcie_gen force_pcie_gen; 166 enum radeon_pcie_gen boot_pcie_gen; 167 enum radeon_pcie_gen acpi_pcie_gen; 168 u32 sys_pcie_mask; 169 /* flags */ 170 bool enable_dte; 171 bool enable_ppm; 172 bool vddc_phase_shed_control; 173 bool pspp_notify_required; 174 bool sclk_deep_sleep_above_low; 175 bool voltage_control_svi2; 176 bool vddci_control_svi2; 177 /* smc offsets */ 178 u32 sram_end; 179 u32 state_table_start; 180 u32 soft_regs_start; 181 u32 mc_reg_table_start; 182 u32 arb_table_start; 183 u32 cac_table_start; 184 u32 dte_table_start; 185 u32 spll_table_start; 186 u32 papm_cfg_table_start; 187 u32 fan_table_start; 188 /* CAC stuff */ 189 const struct si_cac_config_reg *cac_weights; 190 const struct si_cac_config_reg *lcac_config; 191 const struct si_cac_config_reg *cac_override; 192 const struct si_powertune_data *powertune_data; 193 struct si_dyn_powertune_data dyn_powertune_data; 194 /* DTE stuff */ 195 struct si_dte_data dte_data; 196 /* scratch structs */ 197 SMC_SIslands_MCRegisters smc_mc_reg_table; 198 SISLANDS_SMC_STATETABLE smc_statetable; 199 PP_SIslands_PAPMParameters papm_parm; 200 /* SVI2 */ 201 u8 svd_gpio_id; 202 u8 svc_gpio_id; 203 /* fan control */ 204 bool fan_ctrl_is_in_default_mode; 205 u32 t_min; 206 u32 fan_ctrl_default_mode; 207 bool fan_is_controlled_by_smc; 208 }; 209 210 #define SISLANDS_INITIAL_STATE_ARB_INDEX 0 211 #define SISLANDS_ACPI_STATE_ARB_INDEX 1 212 #define SISLANDS_ULV_STATE_ARB_INDEX 2 213 #define SISLANDS_DRIVER_STATE_ARB_INDEX 3 214 215 #define SISLANDS_DPM2_MAX_PULSE_SKIP 256 216 217 #define SISLANDS_DPM2_NEAR_TDP_DEC 10 218 #define SISLANDS_DPM2_ABOVE_SAFE_INC 5 219 #define SISLANDS_DPM2_BELOW_SAFE_INC 20 220 221 #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 222 223 #define SISLANDS_DPM2_MAXPS_PERCENT_H 99 224 #define SISLANDS_DPM2_MAXPS_PERCENT_M 99 225 226 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 227 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 228 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 229 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 230 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 231 232 #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10 233 234 #define SISLANDS_VRC_DFLT 0xC000B3 235 #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687 236 #define SISLANDS_CGULVPARAMETER_DFLT 0x00040035 237 #define SISLANDS_CGULVCONTROL_DFLT 0x1f007550 238 239 240 #endif 241