1 /* $NetBSD: radeon_sumo_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_sumo_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 28 29 #include "drmP.h" 30 #include "radeon.h" 31 #include "sumod.h" 32 #include "sumo_dpm.h" 33 #include "ppsmc.h" 34 35 #define SUMO_SMU_SERVICE_ROUTINE_PG_INIT 1 36 #define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27 37 #define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20 20 38 39 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev); 40 41 static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id) 42 { 43 u32 gfx_int_req; 44 int i; 45 46 for (i = 0; i < rdev->usec_timeout; i++) { 47 if (RREG32(GFX_INT_STATUS) & INT_DONE) 48 break; 49 udelay(1); 50 } 51 52 gfx_int_req = SERV_INDEX(id) | INT_REQ; 53 WREG32(GFX_INT_REQ, gfx_int_req); 54 55 for (i = 0; i < rdev->usec_timeout; i++) { 56 if (RREG32(GFX_INT_REQ) & INT_REQ) 57 break; 58 udelay(1); 59 } 60 61 for (i = 0; i < rdev->usec_timeout; i++) { 62 if (RREG32(GFX_INT_STATUS) & INT_ACK) 63 break; 64 udelay(1); 65 } 66 67 for (i = 0; i < rdev->usec_timeout; i++) { 68 if (RREG32(GFX_INT_STATUS) & INT_DONE) 69 break; 70 udelay(1); 71 } 72 73 gfx_int_req &= ~INT_REQ; 74 WREG32(GFX_INT_REQ, gfx_int_req); 75 } 76 77 void sumo_initialize_m3_arb(struct radeon_device *rdev) 78 { 79 struct sumo_power_info *pi = sumo_get_pi(rdev); 80 u32 i; 81 82 if (!pi->enable_dynamic_m3_arbiter) 83 return; 84 85 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) 86 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), 87 pi->sys_info.csr_m3_arb_cntl_default[i]); 88 89 for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++) 90 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), 91 pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]); 92 93 for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++) 94 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), 95 pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]); 96 } 97 98 static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev) 99 { 100 struct sumo_power_info *pi = sumo_get_pi(rdev); 101 bool return_code = false; 102 103 if (!pi->enable_alt_vddnb) 104 return return_code; 105 106 if ((rdev->family == CHIP_SUMO) || (rdev->family == CHIP_SUMO2)) { 107 if (pi->fw_version >= 0x00010C00) 108 return_code = true; 109 } 110 111 return return_code; 112 } 113 114 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev, 115 bool powersaving, bool force_nbps1) 116 { 117 u32 param = 0; 118 119 if (!sumo_is_alt_vddnb_supported(rdev)) 120 return; 121 122 if (powersaving) 123 param |= 1; 124 125 if (force_nbps1) 126 param |= 2; 127 128 WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param); 129 130 sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY); 131 } 132 133 void sumo_smu_pg_init(struct radeon_device *rdev) 134 { 135 sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_PG_INIT); 136 } 137 138 static u32 sumo_power_of_4(u32 unit) 139 { 140 u32 ret = 1; 141 u32 i; 142 143 for (i = 0; i < unit; i++) 144 ret *= 4; 145 146 return ret; 147 } 148 149 void sumo_enable_boost_timer(struct radeon_device *rdev) 150 { 151 struct sumo_power_info *pi = sumo_get_pi(rdev); 152 u32 period, unit, timer_value; 153 u32 xclk = radeon_get_xclk(rdev); 154 155 unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK) 156 >> LCLK_SCALING_TIMER_PRESCALER_SHIFT; 157 158 period = 100 * (xclk / 100 / sumo_power_of_4(unit)); 159 160 timer_value = (period << 16) | (unit << 4); 161 162 WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value); 163 WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin); 164 WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin); 165 WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit); 166 WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg); 167 168 sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20); 169 } 170 171 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit) 172 { 173 u32 regoffset = 0; 174 u32 shift = 0; 175 u32 mask = 0xFFF; 176 u32 sclk_dpm_tdp_limit; 177 178 switch (index) { 179 case 0: 180 regoffset = RCU_SclkDpmTdpLimit01; 181 shift = 16; 182 break; 183 case 1: 184 regoffset = RCU_SclkDpmTdpLimit01; 185 shift = 0; 186 break; 187 case 2: 188 regoffset = RCU_SclkDpmTdpLimit23; 189 shift = 16; 190 break; 191 case 3: 192 regoffset = RCU_SclkDpmTdpLimit23; 193 shift = 0; 194 break; 195 case 4: 196 regoffset = RCU_SclkDpmTdpLimit47; 197 shift = 16; 198 break; 199 case 7: 200 regoffset = RCU_SclkDpmTdpLimit47; 201 shift = 0; 202 break; 203 default: 204 break; 205 } 206 207 sclk_dpm_tdp_limit = RREG32_RCU(regoffset); 208 sclk_dpm_tdp_limit &= ~(mask << shift); 209 sclk_dpm_tdp_limit |= (tdp_limit << shift); 210 WREG32_RCU(regoffset, sclk_dpm_tdp_limit); 211 } 212 213 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable) 214 { 215 u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE); 216 217 boost_disable &= 0xFFFFFFFE; 218 boost_disable |= (enable ? 0 : 1); 219 WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable); 220 } 221 222 u32 sumo_get_running_fw_version(struct radeon_device *rdev) 223 { 224 return RREG32_RCU(RCU_FW_VERSION); 225 } 226 227