1 /* $NetBSD: radeon_rv515.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_rv515.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 32 33 #include <linux/seq_file.h> 34 #include <linux/slab.h> 35 #include <drm/drmP.h> 36 #include "rv515d.h" 37 #include "radeon.h" 38 #include "radeon_asic.h" 39 #include "atom.h" 40 #include "rv515_reg_safe.h" 41 42 /* This files gather functions specifics to: rv515 */ 43 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 44 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 45 static void rv515_gpu_init(struct radeon_device *rdev); 46 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 47 48 static const u32 crtc_offsets[2] = 49 { 50 0, 51 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 52 }; 53 54 void rv515_debugfs(struct radeon_device *rdev) 55 { 56 if (r100_debugfs_rbbm_init(rdev)) { 57 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 58 } 59 if (rv515_debugfs_pipes_info_init(rdev)) { 60 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 61 } 62 if (rv515_debugfs_ga_info_init(rdev)) { 63 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 64 } 65 } 66 67 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 68 { 69 int r; 70 71 r = radeon_ring_lock(rdev, ring, 64); 72 if (r) { 73 return; 74 } 75 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 76 radeon_ring_write(ring, 77 ISYNC_ANY2D_IDLE3D | 78 ISYNC_ANY3D_IDLE2D | 79 ISYNC_WAIT_IDLEGUI | 80 ISYNC_CPSCRATCH_IDLEGUI); 81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 82 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 83 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 84 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 85 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 86 radeon_ring_write(ring, 0); 87 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 88 radeon_ring_write(ring, 0); 89 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 90 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 91 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 92 radeon_ring_write(ring, 0); 93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 94 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 96 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 97 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 98 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 99 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 100 radeon_ring_write(ring, 0); 101 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 102 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 103 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 104 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 105 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 106 radeon_ring_write(ring, 107 ((6 << MS_X0_SHIFT) | 108 (6 << MS_Y0_SHIFT) | 109 (6 << MS_X1_SHIFT) | 110 (6 << MS_Y1_SHIFT) | 111 (6 << MS_X2_SHIFT) | 112 (6 << MS_Y2_SHIFT) | 113 (6 << MSBD0_Y_SHIFT) | 114 (6 << MSBD0_X_SHIFT))); 115 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 116 radeon_ring_write(ring, 117 ((6 << MS_X3_SHIFT) | 118 (6 << MS_Y3_SHIFT) | 119 (6 << MS_X4_SHIFT) | 120 (6 << MS_Y4_SHIFT) | 121 (6 << MS_X5_SHIFT) | 122 (6 << MS_Y5_SHIFT) | 123 (6 << MSBD1_SHIFT))); 124 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 125 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 126 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 127 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 128 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 129 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 130 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 131 radeon_ring_write(ring, 0); 132 radeon_ring_unlock_commit(rdev, ring, false); 133 } 134 135 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 136 { 137 unsigned i; 138 uint32_t tmp; 139 140 for (i = 0; i < rdev->usec_timeout; i++) { 141 /* read MC_STATUS */ 142 tmp = RREG32_MC(MC_STATUS); 143 if (tmp & MC_STATUS_IDLE) { 144 return 0; 145 } 146 DRM_UDELAY(1); 147 } 148 return -1; 149 } 150 151 void rv515_vga_render_disable(struct radeon_device *rdev) 152 { 153 WREG32(R_000300_VGA_RENDER_CONTROL, 154 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 155 } 156 157 static void rv515_gpu_init(struct radeon_device *rdev) 158 { 159 unsigned pipe_select_current, gb_pipe_select, tmp; 160 161 if (r100_gui_wait_for_idle(rdev)) { 162 printk(KERN_WARNING "Failed to wait GUI idle while " 163 "resetting GPU. Bad things might happen.\n"); 164 } 165 rv515_vga_render_disable(rdev); 166 r420_pipes_init(rdev); 167 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 168 tmp = RREG32(R300_DST_PIPE_CONFIG); 169 pipe_select_current = (tmp >> 2) & 3; 170 tmp = (1 << pipe_select_current) | 171 (((gb_pipe_select >> 8) & 0xF) << 4); 172 WREG32_PLL(0x000D, tmp); 173 if (r100_gui_wait_for_idle(rdev)) { 174 printk(KERN_WARNING "Failed to wait GUI idle while " 175 "resetting GPU. Bad things might happen.\n"); 176 } 177 if (rv515_mc_wait_for_idle(rdev)) { 178 printk(KERN_WARNING "Failed to wait MC idle while " 179 "programming pipes. Bad things might happen.\n"); 180 } 181 } 182 183 static void rv515_vram_get_type(struct radeon_device *rdev) 184 { 185 uint32_t tmp; 186 187 rdev->mc.vram_width = 128; 188 rdev->mc.vram_is_ddr = true; 189 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 190 switch (tmp) { 191 case 0: 192 rdev->mc.vram_width = 64; 193 break; 194 case 1: 195 rdev->mc.vram_width = 128; 196 break; 197 default: 198 rdev->mc.vram_width = 128; 199 break; 200 } 201 } 202 203 static void rv515_mc_init(struct radeon_device *rdev) 204 { 205 206 rv515_vram_get_type(rdev); 207 r100_vram_init_sizes(rdev); 208 radeon_vram_location(rdev, &rdev->mc, 0); 209 rdev->mc.gtt_base_align = 0; 210 if (!(rdev->flags & RADEON_IS_AGP)) 211 radeon_gtt_location(rdev, &rdev->mc); 212 radeon_update_bandwidth_info(rdev); 213 } 214 215 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 216 { 217 unsigned long flags; 218 uint32_t r; 219 220 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 221 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 222 r = RREG32(MC_IND_DATA); 223 WREG32(MC_IND_INDEX, 0); 224 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 225 226 return r; 227 } 228 229 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 230 { 231 unsigned long flags; 232 233 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 234 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 235 WREG32(MC_IND_DATA, (v)); 236 WREG32(MC_IND_INDEX, 0); 237 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 238 } 239 240 #if defined(CONFIG_DEBUG_FS) 241 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 242 { 243 struct drm_info_node *node = (struct drm_info_node *) m->private; 244 struct drm_device *dev = node->minor->dev; 245 struct radeon_device *rdev = dev->dev_private; 246 uint32_t tmp; 247 248 tmp = RREG32(GB_PIPE_SELECT); 249 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 250 tmp = RREG32(SU_REG_DEST); 251 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 252 tmp = RREG32(GB_TILE_CONFIG); 253 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 254 tmp = RREG32(DST_PIPE_CONFIG); 255 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 256 return 0; 257 } 258 259 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 260 { 261 struct drm_info_node *node = (struct drm_info_node *) m->private; 262 struct drm_device *dev = node->minor->dev; 263 struct radeon_device *rdev = dev->dev_private; 264 uint32_t tmp; 265 266 tmp = RREG32(0x2140); 267 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 268 radeon_asic_reset(rdev); 269 tmp = RREG32(0x425C); 270 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 271 return 0; 272 } 273 274 static struct drm_info_list rv515_pipes_info_list[] = { 275 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 276 }; 277 278 static struct drm_info_list rv515_ga_info_list[] = { 279 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 280 }; 281 #endif 282 283 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 284 { 285 #if defined(CONFIG_DEBUG_FS) 286 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 287 #else 288 return 0; 289 #endif 290 } 291 292 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 293 { 294 #if defined(CONFIG_DEBUG_FS) 295 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 296 #else 297 return 0; 298 #endif 299 } 300 301 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 302 { 303 u32 crtc_enabled, tmp, frame_count, blackout; 304 int i, j; 305 306 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 307 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 308 309 /* disable VGA render */ 310 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 311 /* blank the display controllers */ 312 for (i = 0; i < rdev->num_crtc; i++) { 313 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 314 if (crtc_enabled) { 315 save->crtc_enabled[i] = true; 316 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 317 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 318 radeon_wait_for_vblank(rdev, i); 319 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 320 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 321 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 322 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 323 } 324 /* wait for the next frame */ 325 frame_count = radeon_get_vblank_counter(rdev, i); 326 for (j = 0; j < rdev->usec_timeout; j++) { 327 if (radeon_get_vblank_counter(rdev, i) != frame_count) 328 break; 329 udelay(1); 330 } 331 332 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 333 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 335 tmp &= ~AVIVO_CRTC_EN; 336 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 337 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 338 save->crtc_enabled[i] = false; 339 /* ***** */ 340 } else { 341 save->crtc_enabled[i] = false; 342 } 343 } 344 345 radeon_mc_wait_for_idle(rdev); 346 347 if (rdev->family >= CHIP_R600) { 348 if (rdev->family >= CHIP_RV770) 349 blackout = RREG32(R700_MC_CITF_CNTL); 350 else 351 blackout = RREG32(R600_CITF_CNTL); 352 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 353 /* Block CPU access */ 354 WREG32(R600_BIF_FB_EN, 0); 355 /* blackout the MC */ 356 blackout |= R600_BLACKOUT_MASK; 357 if (rdev->family >= CHIP_RV770) 358 WREG32(R700_MC_CITF_CNTL, blackout); 359 else 360 WREG32(R600_CITF_CNTL, blackout); 361 } 362 } 363 /* wait for the MC to settle */ 364 udelay(100); 365 366 /* lock double buffered regs */ 367 for (i = 0; i < rdev->num_crtc; i++) { 368 if (save->crtc_enabled[i]) { 369 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 370 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 371 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 372 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 373 } 374 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 375 if (!(tmp & 1)) { 376 tmp |= 1; 377 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 378 } 379 } 380 } 381 } 382 383 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 384 { 385 u32 tmp, frame_count; 386 int i, j; 387 388 /* update crtc base addresses */ 389 for (i = 0; i < rdev->num_crtc; i++) { 390 if (rdev->family >= CHIP_RV770) { 391 if (i == 0) { 392 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 393 upper_32_bits(rdev->mc.vram_start)); 394 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 395 upper_32_bits(rdev->mc.vram_start)); 396 } else { 397 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 398 upper_32_bits(rdev->mc.vram_start)); 399 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 400 upper_32_bits(rdev->mc.vram_start)); 401 } 402 } 403 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 404 (u32)rdev->mc.vram_start); 405 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 406 (u32)rdev->mc.vram_start); 407 } 408 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 409 410 /* unlock regs and wait for update */ 411 for (i = 0; i < rdev->num_crtc; i++) { 412 if (save->crtc_enabled[i]) { 413 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 414 if ((tmp & 0x7) != 3) { 415 tmp &= ~0x7; 416 tmp |= 0x3; 417 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 418 } 419 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 420 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 421 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 422 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 423 } 424 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 425 if (tmp & 1) { 426 tmp &= ~1; 427 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 428 } 429 for (j = 0; j < rdev->usec_timeout; j++) { 430 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 431 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 432 break; 433 udelay(1); 434 } 435 } 436 } 437 438 if (rdev->family >= CHIP_R600) { 439 /* unblackout the MC */ 440 if (rdev->family >= CHIP_RV770) 441 tmp = RREG32(R700_MC_CITF_CNTL); 442 else 443 tmp = RREG32(R600_CITF_CNTL); 444 tmp &= ~R600_BLACKOUT_MASK; 445 if (rdev->family >= CHIP_RV770) 446 WREG32(R700_MC_CITF_CNTL, tmp); 447 else 448 WREG32(R600_CITF_CNTL, tmp); 449 /* allow CPU access */ 450 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 451 } 452 453 for (i = 0; i < rdev->num_crtc; i++) { 454 if (save->crtc_enabled[i]) { 455 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 456 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 457 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 458 /* wait for the next frame */ 459 frame_count = radeon_get_vblank_counter(rdev, i); 460 for (j = 0; j < rdev->usec_timeout; j++) { 461 if (radeon_get_vblank_counter(rdev, i) != frame_count) 462 break; 463 udelay(1); 464 } 465 } 466 } 467 /* Unlock vga access */ 468 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 469 mdelay(1); 470 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 471 } 472 473 static void rv515_mc_program(struct radeon_device *rdev) 474 { 475 struct rv515_mc_save save; 476 477 /* Stops all mc clients */ 478 rv515_mc_stop(rdev, &save); 479 480 /* Wait for mc idle */ 481 if (rv515_mc_wait_for_idle(rdev)) 482 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 483 /* Write VRAM size in case we are limiting it */ 484 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 485 /* Program MC, should be a 32bits limited address space */ 486 WREG32_MC(R_000001_MC_FB_LOCATION, 487 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 488 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 489 WREG32(R_000134_HDP_FB_LOCATION, 490 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 491 if (rdev->flags & RADEON_IS_AGP) { 492 WREG32_MC(R_000002_MC_AGP_LOCATION, 493 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 494 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 495 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 496 WREG32_MC(R_000004_MC_AGP_BASE_2, 497 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 498 } else { 499 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 500 WREG32_MC(R_000003_MC_AGP_BASE, 0); 501 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 502 } 503 504 rv515_mc_resume(rdev, &save); 505 } 506 507 void rv515_clock_startup(struct radeon_device *rdev) 508 { 509 if (radeon_dynclks != -1 && radeon_dynclks) 510 radeon_atom_set_clock_gating(rdev, 1); 511 /* We need to force on some of the block */ 512 WREG32_PLL(R_00000F_CP_DYN_CNTL, 513 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 514 WREG32_PLL(R_000011_E2_DYN_CNTL, 515 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 516 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 517 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 518 } 519 520 static int rv515_startup(struct radeon_device *rdev) 521 { 522 int r; 523 524 rv515_mc_program(rdev); 525 /* Resume clock */ 526 rv515_clock_startup(rdev); 527 /* Initialize GPU configuration (# pipes, ...) */ 528 rv515_gpu_init(rdev); 529 /* Initialize GART (initialize after TTM so we can allocate 530 * memory through TTM but finalize after TTM) */ 531 if (rdev->flags & RADEON_IS_PCIE) { 532 r = rv370_pcie_gart_enable(rdev); 533 if (r) 534 return r; 535 } 536 537 /* allocate wb buffer */ 538 r = radeon_wb_init(rdev); 539 if (r) 540 return r; 541 542 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 543 if (r) { 544 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 545 return r; 546 } 547 548 /* Enable IRQ */ 549 if (!rdev->irq.installed) { 550 r = radeon_irq_kms_init(rdev); 551 if (r) 552 return r; 553 } 554 555 rs600_irq_set(rdev); 556 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 557 /* 1M ring buffer */ 558 r = r100_cp_init(rdev, 1024 * 1024); 559 if (r) { 560 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 561 return r; 562 } 563 564 r = radeon_ib_pool_init(rdev); 565 if (r) { 566 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 567 return r; 568 } 569 570 return 0; 571 } 572 573 int rv515_resume(struct radeon_device *rdev) 574 { 575 int r; 576 577 /* Make sur GART are not working */ 578 if (rdev->flags & RADEON_IS_PCIE) 579 rv370_pcie_gart_disable(rdev); 580 /* Resume clock before doing reset */ 581 rv515_clock_startup(rdev); 582 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 583 if (radeon_asic_reset(rdev)) { 584 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 585 RREG32(R_000E40_RBBM_STATUS), 586 RREG32(R_0007C0_CP_STAT)); 587 } 588 /* post */ 589 atom_asic_init(rdev->mode_info.atom_context); 590 /* Resume clock after posting */ 591 rv515_clock_startup(rdev); 592 /* Initialize surface registers */ 593 radeon_surface_init(rdev); 594 595 rdev->accel_working = true; 596 r = rv515_startup(rdev); 597 if (r) { 598 rdev->accel_working = false; 599 } 600 return r; 601 } 602 603 int rv515_suspend(struct radeon_device *rdev) 604 { 605 radeon_pm_suspend(rdev); 606 r100_cp_disable(rdev); 607 radeon_wb_disable(rdev); 608 rs600_irq_disable(rdev); 609 if (rdev->flags & RADEON_IS_PCIE) 610 rv370_pcie_gart_disable(rdev); 611 return 0; 612 } 613 614 void rv515_set_safe_registers(struct radeon_device *rdev) 615 { 616 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 617 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 618 } 619 620 void rv515_fini(struct radeon_device *rdev) 621 { 622 radeon_pm_fini(rdev); 623 r100_cp_fini(rdev); 624 radeon_wb_fini(rdev); 625 radeon_ib_pool_fini(rdev); 626 radeon_gem_fini(rdev); 627 rv370_pcie_gart_fini(rdev); 628 radeon_agp_fini(rdev); 629 radeon_irq_kms_fini(rdev); 630 radeon_fence_driver_fini(rdev); 631 radeon_bo_fini(rdev); 632 radeon_atombios_fini(rdev); 633 kfree(rdev->bios); 634 rdev->bios = NULL; 635 } 636 637 int rv515_init(struct radeon_device *rdev) 638 { 639 int r; 640 641 /* Initialize scratch registers */ 642 radeon_scratch_init(rdev); 643 /* Initialize surface registers */ 644 radeon_surface_init(rdev); 645 /* TODO: disable VGA need to use VGA request */ 646 /* restore some register to sane defaults */ 647 r100_restore_sanity(rdev); 648 /* BIOS*/ 649 if (!radeon_get_bios(rdev)) { 650 if (ASIC_IS_AVIVO(rdev)) 651 return -EINVAL; 652 } 653 if (rdev->is_atom_bios) { 654 r = radeon_atombios_init(rdev); 655 if (r) 656 return r; 657 } else { 658 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 659 return -EINVAL; 660 } 661 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 662 if (radeon_asic_reset(rdev)) { 663 dev_warn(rdev->dev, 664 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 665 RREG32(R_000E40_RBBM_STATUS), 666 RREG32(R_0007C0_CP_STAT)); 667 } 668 /* check if cards are posted or not */ 669 if (radeon_boot_test_post_card(rdev) == false) 670 return -EINVAL; 671 /* Initialize clocks */ 672 radeon_get_clock_info(rdev->ddev); 673 /* initialize AGP */ 674 if (rdev->flags & RADEON_IS_AGP) { 675 r = radeon_agp_init(rdev); 676 if (r) { 677 radeon_agp_disable(rdev); 678 } 679 } 680 /* initialize memory controller */ 681 rv515_mc_init(rdev); 682 rv515_debugfs(rdev); 683 /* Fence driver */ 684 r = radeon_fence_driver_init(rdev); 685 if (r) 686 return r; 687 /* Memory manager */ 688 r = radeon_bo_init(rdev); 689 if (r) 690 return r; 691 r = rv370_pcie_gart_init(rdev); 692 if (r) 693 return r; 694 rv515_set_safe_registers(rdev); 695 696 /* Initialize power management */ 697 radeon_pm_init(rdev); 698 699 rdev->accel_working = true; 700 r = rv515_startup(rdev); 701 if (r) { 702 /* Somethings want wront with the accel init stop accel */ 703 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 704 r100_cp_fini(rdev); 705 radeon_wb_fini(rdev); 706 radeon_ib_pool_fini(rdev); 707 radeon_irq_kms_fini(rdev); 708 rv370_pcie_gart_fini(rdev); 709 radeon_agp_fini(rdev); 710 rdev->accel_working = false; 711 } 712 return 0; 713 } 714 715 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 716 { 717 int index_reg = 0x6578 + crtc->crtc_offset; 718 int data_reg = 0x657c + crtc->crtc_offset; 719 720 WREG32(0x659C + crtc->crtc_offset, 0x0); 721 WREG32(0x6594 + crtc->crtc_offset, 0x705); 722 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 723 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 724 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 725 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 726 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 727 WREG32(index_reg, 0x0); 728 WREG32(data_reg, 0x841880A8); 729 WREG32(index_reg, 0x1); 730 WREG32(data_reg, 0x84208680); 731 WREG32(index_reg, 0x2); 732 WREG32(data_reg, 0xBFF880B0); 733 WREG32(index_reg, 0x100); 734 WREG32(data_reg, 0x83D88088); 735 WREG32(index_reg, 0x101); 736 WREG32(data_reg, 0x84608680); 737 WREG32(index_reg, 0x102); 738 WREG32(data_reg, 0xBFF080D0); 739 WREG32(index_reg, 0x200); 740 WREG32(data_reg, 0x83988068); 741 WREG32(index_reg, 0x201); 742 WREG32(data_reg, 0x84A08680); 743 WREG32(index_reg, 0x202); 744 WREG32(data_reg, 0xBFF080F8); 745 WREG32(index_reg, 0x300); 746 WREG32(data_reg, 0x83588058); 747 WREG32(index_reg, 0x301); 748 WREG32(data_reg, 0x84E08660); 749 WREG32(index_reg, 0x302); 750 WREG32(data_reg, 0xBFF88120); 751 WREG32(index_reg, 0x400); 752 WREG32(data_reg, 0x83188040); 753 WREG32(index_reg, 0x401); 754 WREG32(data_reg, 0x85008660); 755 WREG32(index_reg, 0x402); 756 WREG32(data_reg, 0xBFF88150); 757 WREG32(index_reg, 0x500); 758 WREG32(data_reg, 0x82D88030); 759 WREG32(index_reg, 0x501); 760 WREG32(data_reg, 0x85408640); 761 WREG32(index_reg, 0x502); 762 WREG32(data_reg, 0xBFF88180); 763 WREG32(index_reg, 0x600); 764 WREG32(data_reg, 0x82A08018); 765 WREG32(index_reg, 0x601); 766 WREG32(data_reg, 0x85808620); 767 WREG32(index_reg, 0x602); 768 WREG32(data_reg, 0xBFF081B8); 769 WREG32(index_reg, 0x700); 770 WREG32(data_reg, 0x82608010); 771 WREG32(index_reg, 0x701); 772 WREG32(data_reg, 0x85A08600); 773 WREG32(index_reg, 0x702); 774 WREG32(data_reg, 0x800081F0); 775 WREG32(index_reg, 0x800); 776 WREG32(data_reg, 0x8228BFF8); 777 WREG32(index_reg, 0x801); 778 WREG32(data_reg, 0x85E085E0); 779 WREG32(index_reg, 0x802); 780 WREG32(data_reg, 0xBFF88228); 781 WREG32(index_reg, 0x10000); 782 WREG32(data_reg, 0x82A8BF00); 783 WREG32(index_reg, 0x10001); 784 WREG32(data_reg, 0x82A08CC0); 785 WREG32(index_reg, 0x10002); 786 WREG32(data_reg, 0x8008BEF8); 787 WREG32(index_reg, 0x10100); 788 WREG32(data_reg, 0x81F0BF28); 789 WREG32(index_reg, 0x10101); 790 WREG32(data_reg, 0x83608CA0); 791 WREG32(index_reg, 0x10102); 792 WREG32(data_reg, 0x8018BED0); 793 WREG32(index_reg, 0x10200); 794 WREG32(data_reg, 0x8148BF38); 795 WREG32(index_reg, 0x10201); 796 WREG32(data_reg, 0x84408C80); 797 WREG32(index_reg, 0x10202); 798 WREG32(data_reg, 0x8008BEB8); 799 WREG32(index_reg, 0x10300); 800 WREG32(data_reg, 0x80B0BF78); 801 WREG32(index_reg, 0x10301); 802 WREG32(data_reg, 0x85008C20); 803 WREG32(index_reg, 0x10302); 804 WREG32(data_reg, 0x8020BEA0); 805 WREG32(index_reg, 0x10400); 806 WREG32(data_reg, 0x8028BF90); 807 WREG32(index_reg, 0x10401); 808 WREG32(data_reg, 0x85E08BC0); 809 WREG32(index_reg, 0x10402); 810 WREG32(data_reg, 0x8018BE90); 811 WREG32(index_reg, 0x10500); 812 WREG32(data_reg, 0xBFB8BFB0); 813 WREG32(index_reg, 0x10501); 814 WREG32(data_reg, 0x86C08B40); 815 WREG32(index_reg, 0x10502); 816 WREG32(data_reg, 0x8010BE90); 817 WREG32(index_reg, 0x10600); 818 WREG32(data_reg, 0xBF58BFC8); 819 WREG32(index_reg, 0x10601); 820 WREG32(data_reg, 0x87A08AA0); 821 WREG32(index_reg, 0x10602); 822 WREG32(data_reg, 0x8010BE98); 823 WREG32(index_reg, 0x10700); 824 WREG32(data_reg, 0xBF10BFF0); 825 WREG32(index_reg, 0x10701); 826 WREG32(data_reg, 0x886089E0); 827 WREG32(index_reg, 0x10702); 828 WREG32(data_reg, 0x8018BEB0); 829 WREG32(index_reg, 0x10800); 830 WREG32(data_reg, 0xBED8BFE8); 831 WREG32(index_reg, 0x10801); 832 WREG32(data_reg, 0x89408940); 833 WREG32(index_reg, 0x10802); 834 WREG32(data_reg, 0xBFE8BED8); 835 WREG32(index_reg, 0x20000); 836 WREG32(data_reg, 0x80008000); 837 WREG32(index_reg, 0x20001); 838 WREG32(data_reg, 0x90008000); 839 WREG32(index_reg, 0x20002); 840 WREG32(data_reg, 0x80008000); 841 WREG32(index_reg, 0x20003); 842 WREG32(data_reg, 0x80008000); 843 WREG32(index_reg, 0x20100); 844 WREG32(data_reg, 0x80108000); 845 WREG32(index_reg, 0x20101); 846 WREG32(data_reg, 0x8FE0BF70); 847 WREG32(index_reg, 0x20102); 848 WREG32(data_reg, 0xBFE880C0); 849 WREG32(index_reg, 0x20103); 850 WREG32(data_reg, 0x80008000); 851 WREG32(index_reg, 0x20200); 852 WREG32(data_reg, 0x8018BFF8); 853 WREG32(index_reg, 0x20201); 854 WREG32(data_reg, 0x8F80BF08); 855 WREG32(index_reg, 0x20202); 856 WREG32(data_reg, 0xBFD081A0); 857 WREG32(index_reg, 0x20203); 858 WREG32(data_reg, 0xBFF88000); 859 WREG32(index_reg, 0x20300); 860 WREG32(data_reg, 0x80188000); 861 WREG32(index_reg, 0x20301); 862 WREG32(data_reg, 0x8EE0BEC0); 863 WREG32(index_reg, 0x20302); 864 WREG32(data_reg, 0xBFB082A0); 865 WREG32(index_reg, 0x20303); 866 WREG32(data_reg, 0x80008000); 867 WREG32(index_reg, 0x20400); 868 WREG32(data_reg, 0x80188000); 869 WREG32(index_reg, 0x20401); 870 WREG32(data_reg, 0x8E00BEA0); 871 WREG32(index_reg, 0x20402); 872 WREG32(data_reg, 0xBF8883C0); 873 WREG32(index_reg, 0x20403); 874 WREG32(data_reg, 0x80008000); 875 WREG32(index_reg, 0x20500); 876 WREG32(data_reg, 0x80188000); 877 WREG32(index_reg, 0x20501); 878 WREG32(data_reg, 0x8D00BE90); 879 WREG32(index_reg, 0x20502); 880 WREG32(data_reg, 0xBF588500); 881 WREG32(index_reg, 0x20503); 882 WREG32(data_reg, 0x80008008); 883 WREG32(index_reg, 0x20600); 884 WREG32(data_reg, 0x80188000); 885 WREG32(index_reg, 0x20601); 886 WREG32(data_reg, 0x8BC0BE98); 887 WREG32(index_reg, 0x20602); 888 WREG32(data_reg, 0xBF308660); 889 WREG32(index_reg, 0x20603); 890 WREG32(data_reg, 0x80008008); 891 WREG32(index_reg, 0x20700); 892 WREG32(data_reg, 0x80108000); 893 WREG32(index_reg, 0x20701); 894 WREG32(data_reg, 0x8A80BEB0); 895 WREG32(index_reg, 0x20702); 896 WREG32(data_reg, 0xBF0087C0); 897 WREG32(index_reg, 0x20703); 898 WREG32(data_reg, 0x80008008); 899 WREG32(index_reg, 0x20800); 900 WREG32(data_reg, 0x80108000); 901 WREG32(index_reg, 0x20801); 902 WREG32(data_reg, 0x8920BED0); 903 WREG32(index_reg, 0x20802); 904 WREG32(data_reg, 0xBED08920); 905 WREG32(index_reg, 0x20803); 906 WREG32(data_reg, 0x80008010); 907 WREG32(index_reg, 0x30000); 908 WREG32(data_reg, 0x90008000); 909 WREG32(index_reg, 0x30001); 910 WREG32(data_reg, 0x80008000); 911 WREG32(index_reg, 0x30100); 912 WREG32(data_reg, 0x8FE0BF90); 913 WREG32(index_reg, 0x30101); 914 WREG32(data_reg, 0xBFF880A0); 915 WREG32(index_reg, 0x30200); 916 WREG32(data_reg, 0x8F60BF40); 917 WREG32(index_reg, 0x30201); 918 WREG32(data_reg, 0xBFE88180); 919 WREG32(index_reg, 0x30300); 920 WREG32(data_reg, 0x8EC0BF00); 921 WREG32(index_reg, 0x30301); 922 WREG32(data_reg, 0xBFC88280); 923 WREG32(index_reg, 0x30400); 924 WREG32(data_reg, 0x8DE0BEE0); 925 WREG32(index_reg, 0x30401); 926 WREG32(data_reg, 0xBFA083A0); 927 WREG32(index_reg, 0x30500); 928 WREG32(data_reg, 0x8CE0BED0); 929 WREG32(index_reg, 0x30501); 930 WREG32(data_reg, 0xBF7884E0); 931 WREG32(index_reg, 0x30600); 932 WREG32(data_reg, 0x8BA0BED8); 933 WREG32(index_reg, 0x30601); 934 WREG32(data_reg, 0xBF508640); 935 WREG32(index_reg, 0x30700); 936 WREG32(data_reg, 0x8A60BEE8); 937 WREG32(index_reg, 0x30701); 938 WREG32(data_reg, 0xBF2087A0); 939 WREG32(index_reg, 0x30800); 940 WREG32(data_reg, 0x8900BF00); 941 WREG32(index_reg, 0x30801); 942 WREG32(data_reg, 0xBF008900); 943 } 944 945 struct rv515_watermark { 946 u32 lb_request_fifo_depth; 947 fixed20_12 num_line_pair; 948 fixed20_12 estimated_width; 949 fixed20_12 worst_case_latency; 950 fixed20_12 consumption_rate; 951 fixed20_12 active_time; 952 fixed20_12 dbpp; 953 fixed20_12 priority_mark_max; 954 fixed20_12 priority_mark; 955 fixed20_12 sclk; 956 }; 957 958 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 959 struct radeon_crtc *crtc, 960 struct rv515_watermark *wm, 961 bool low) 962 { 963 struct drm_display_mode *mode = &crtc->base.mode; 964 fixed20_12 a, b, c; 965 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 966 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 967 fixed20_12 sclk; 968 u32 selected_sclk; 969 970 if (!crtc->base.enabled) { 971 /* FIXME: wouldn't it better to set priority mark to maximum */ 972 wm->lb_request_fifo_depth = 4; 973 return; 974 } 975 976 /* rv6xx, rv7xx */ 977 if ((rdev->family >= CHIP_RV610) && 978 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 979 selected_sclk = radeon_dpm_get_sclk(rdev, low); 980 else 981 selected_sclk = rdev->pm.current_sclk; 982 983 /* sclk in Mhz */ 984 a.full = dfixed_const(100); 985 sclk.full = dfixed_const(selected_sclk); 986 sclk.full = dfixed_div(sclk, a); 987 988 if (crtc->vsc.full > dfixed_const(2)) 989 wm->num_line_pair.full = dfixed_const(2); 990 else 991 wm->num_line_pair.full = dfixed_const(1); 992 993 b.full = dfixed_const(mode->crtc_hdisplay); 994 c.full = dfixed_const(256); 995 a.full = dfixed_div(b, c); 996 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 997 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 998 if (a.full < dfixed_const(4)) { 999 wm->lb_request_fifo_depth = 4; 1000 } else { 1001 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 1002 } 1003 1004 /* Determine consumption rate 1005 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 1006 * vtaps = number of vertical taps, 1007 * vsc = vertical scaling ratio, defined as source/destination 1008 * hsc = horizontal scaling ration, defined as source/destination 1009 */ 1010 a.full = dfixed_const(mode->clock); 1011 b.full = dfixed_const(1000); 1012 a.full = dfixed_div(a, b); 1013 pclk.full = dfixed_div(b, a); 1014 if (crtc->rmx_type != RMX_OFF) { 1015 b.full = dfixed_const(2); 1016 if (crtc->vsc.full > b.full) 1017 b.full = crtc->vsc.full; 1018 b.full = dfixed_mul(b, crtc->hsc); 1019 c.full = dfixed_const(2); 1020 b.full = dfixed_div(b, c); 1021 consumption_time.full = dfixed_div(pclk, b); 1022 } else { 1023 consumption_time.full = pclk.full; 1024 } 1025 a.full = dfixed_const(1); 1026 wm->consumption_rate.full = dfixed_div(a, consumption_time); 1027 1028 1029 /* Determine line time 1030 * LineTime = total time for one line of displayhtotal 1031 * LineTime = total number of horizontal pixels 1032 * pclk = pixel clock period(ns) 1033 */ 1034 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1035 line_time.full = dfixed_mul(a, pclk); 1036 1037 /* Determine active time 1038 * ActiveTime = time of active region of display within one line, 1039 * hactive = total number of horizontal active pixels 1040 * htotal = total number of horizontal pixels 1041 */ 1042 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1043 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1044 wm->active_time.full = dfixed_mul(line_time, b); 1045 wm->active_time.full = dfixed_div(wm->active_time, a); 1046 1047 /* Determine chunk time 1048 * ChunkTime = the time it takes the DCP to send one chunk of data 1049 * to the LB which consists of pipeline delay and inter chunk gap 1050 * sclk = system clock(Mhz) 1051 */ 1052 a.full = dfixed_const(600 * 1000); 1053 chunk_time.full = dfixed_div(a, sclk); 1054 read_delay_latency.full = dfixed_const(1000); 1055 1056 /* Determine the worst case latency 1057 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1058 * WorstCaseLatency = worst case time from urgent to when the MC starts 1059 * to return data 1060 * READ_DELAY_IDLE_MAX = constant of 1us 1061 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1062 * which consists of pipeline delay and inter chunk gap 1063 */ 1064 if (dfixed_trunc(wm->num_line_pair) > 1) { 1065 a.full = dfixed_const(3); 1066 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1067 wm->worst_case_latency.full += read_delay_latency.full; 1068 } else { 1069 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1070 } 1071 1072 /* Determine the tolerable latency 1073 * TolerableLatency = Any given request has only 1 line time 1074 * for the data to be returned 1075 * LBRequestFifoDepth = Number of chunk requests the LB can 1076 * put into the request FIFO for a display 1077 * LineTime = total time for one line of display 1078 * ChunkTime = the time it takes the DCP to send one chunk 1079 * of data to the LB which consists of 1080 * pipeline delay and inter chunk gap 1081 */ 1082 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1083 tolerable_latency.full = line_time.full; 1084 } else { 1085 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1086 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 1087 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1088 tolerable_latency.full = line_time.full - tolerable_latency.full; 1089 } 1090 /* We assume worst case 32bits (4 bytes) */ 1091 wm->dbpp.full = dfixed_const(2 * 16); 1092 1093 /* Determine the maximum priority mark 1094 * width = viewport width in pixels 1095 */ 1096 a.full = dfixed_const(16); 1097 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1098 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 1099 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1100 1101 /* Determine estimated width */ 1102 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1103 estimated_width.full = dfixed_div(estimated_width, consumption_time); 1104 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 1105 wm->priority_mark.full = wm->priority_mark_max.full; 1106 } else { 1107 a.full = dfixed_const(16); 1108 wm->priority_mark.full = dfixed_div(estimated_width, a); 1109 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1110 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1111 } 1112 } 1113 1114 static void rv515_compute_mode_priority(struct radeon_device *rdev, 1115 struct rv515_watermark *wm0, 1116 struct rv515_watermark *wm1, 1117 struct drm_display_mode *mode0, 1118 struct drm_display_mode *mode1, 1119 u32 *d1mode_priority_a_cnt, 1120 u32 *d2mode_priority_a_cnt) 1121 { 1122 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1123 fixed20_12 a, b; 1124 1125 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 1126 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 1127 1128 if (mode0 && mode1) { 1129 if (dfixed_trunc(wm0->dbpp) > 64) 1130 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1131 else 1132 a.full = wm0->num_line_pair.full; 1133 if (dfixed_trunc(wm1->dbpp) > 64) 1134 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1135 else 1136 b.full = wm1->num_line_pair.full; 1137 a.full += b.full; 1138 fill_rate.full = dfixed_div(wm0->sclk, a); 1139 if (wm0->consumption_rate.full > fill_rate.full) { 1140 b.full = wm0->consumption_rate.full - fill_rate.full; 1141 b.full = dfixed_mul(b, wm0->active_time); 1142 a.full = dfixed_const(16); 1143 b.full = dfixed_div(b, a); 1144 a.full = dfixed_mul(wm0->worst_case_latency, 1145 wm0->consumption_rate); 1146 priority_mark02.full = a.full + b.full; 1147 } else { 1148 a.full = dfixed_mul(wm0->worst_case_latency, 1149 wm0->consumption_rate); 1150 b.full = dfixed_const(16 * 1000); 1151 priority_mark02.full = dfixed_div(a, b); 1152 } 1153 if (wm1->consumption_rate.full > fill_rate.full) { 1154 b.full = wm1->consumption_rate.full - fill_rate.full; 1155 b.full = dfixed_mul(b, wm1->active_time); 1156 a.full = dfixed_const(16); 1157 b.full = dfixed_div(b, a); 1158 a.full = dfixed_mul(wm1->worst_case_latency, 1159 wm1->consumption_rate); 1160 priority_mark12.full = a.full + b.full; 1161 } else { 1162 a.full = dfixed_mul(wm1->worst_case_latency, 1163 wm1->consumption_rate); 1164 b.full = dfixed_const(16 * 1000); 1165 priority_mark12.full = dfixed_div(a, b); 1166 } 1167 if (wm0->priority_mark.full > priority_mark02.full) 1168 priority_mark02.full = wm0->priority_mark.full; 1169 if (wm0->priority_mark_max.full > priority_mark02.full) 1170 priority_mark02.full = wm0->priority_mark_max.full; 1171 if (wm1->priority_mark.full > priority_mark12.full) 1172 priority_mark12.full = wm1->priority_mark.full; 1173 if (wm1->priority_mark_max.full > priority_mark12.full) 1174 priority_mark12.full = wm1->priority_mark_max.full; 1175 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1176 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1177 if (rdev->disp_priority == 2) { 1178 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1179 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1180 } 1181 } else if (mode0) { 1182 if (dfixed_trunc(wm0->dbpp) > 64) 1183 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1184 else 1185 a.full = wm0->num_line_pair.full; 1186 fill_rate.full = dfixed_div(wm0->sclk, a); 1187 if (wm0->consumption_rate.full > fill_rate.full) { 1188 b.full = wm0->consumption_rate.full - fill_rate.full; 1189 b.full = dfixed_mul(b, wm0->active_time); 1190 a.full = dfixed_const(16); 1191 b.full = dfixed_div(b, a); 1192 a.full = dfixed_mul(wm0->worst_case_latency, 1193 wm0->consumption_rate); 1194 priority_mark02.full = a.full + b.full; 1195 } else { 1196 a.full = dfixed_mul(wm0->worst_case_latency, 1197 wm0->consumption_rate); 1198 b.full = dfixed_const(16); 1199 priority_mark02.full = dfixed_div(a, b); 1200 } 1201 if (wm0->priority_mark.full > priority_mark02.full) 1202 priority_mark02.full = wm0->priority_mark.full; 1203 if (wm0->priority_mark_max.full > priority_mark02.full) 1204 priority_mark02.full = wm0->priority_mark_max.full; 1205 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1206 if (rdev->disp_priority == 2) 1207 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1208 } else if (mode1) { 1209 if (dfixed_trunc(wm1->dbpp) > 64) 1210 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1211 else 1212 a.full = wm1->num_line_pair.full; 1213 fill_rate.full = dfixed_div(wm1->sclk, a); 1214 if (wm1->consumption_rate.full > fill_rate.full) { 1215 b.full = wm1->consumption_rate.full - fill_rate.full; 1216 b.full = dfixed_mul(b, wm1->active_time); 1217 a.full = dfixed_const(16); 1218 b.full = dfixed_div(b, a); 1219 a.full = dfixed_mul(wm1->worst_case_latency, 1220 wm1->consumption_rate); 1221 priority_mark12.full = a.full + b.full; 1222 } else { 1223 a.full = dfixed_mul(wm1->worst_case_latency, 1224 wm1->consumption_rate); 1225 b.full = dfixed_const(16 * 1000); 1226 priority_mark12.full = dfixed_div(a, b); 1227 } 1228 if (wm1->priority_mark.full > priority_mark12.full) 1229 priority_mark12.full = wm1->priority_mark.full; 1230 if (wm1->priority_mark_max.full > priority_mark12.full) 1231 priority_mark12.full = wm1->priority_mark_max.full; 1232 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1233 if (rdev->disp_priority == 2) 1234 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1235 } 1236 } 1237 1238 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1239 { 1240 struct drm_display_mode *mode0 = NULL; 1241 struct drm_display_mode *mode1 = NULL; 1242 struct rv515_watermark wm0_high, wm0_low; 1243 struct rv515_watermark wm1_high, wm1_low; 1244 u32 tmp; 1245 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 1246 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1247 1248 if (rdev->mode_info.crtcs[0]->base.enabled) 1249 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1250 if (rdev->mode_info.crtcs[1]->base.enabled) 1251 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1252 rs690_line_buffer_adjust(rdev, mode0, mode1); 1253 1254 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 1255 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1256 1257 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 1258 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 1259 1260 tmp = wm0_high.lb_request_fifo_depth; 1261 tmp |= wm1_high.lb_request_fifo_depth << 16; 1262 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1263 1264 rv515_compute_mode_priority(rdev, 1265 &wm0_high, &wm1_high, 1266 mode0, mode1, 1267 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 1268 rv515_compute_mode_priority(rdev, 1269 &wm0_low, &wm1_low, 1270 mode0, mode1, 1271 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1272 1273 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1274 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1275 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1276 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1277 } 1278 1279 void rv515_bandwidth_update(struct radeon_device *rdev) 1280 { 1281 uint32_t tmp; 1282 struct drm_display_mode *mode0 = NULL; 1283 struct drm_display_mode *mode1 = NULL; 1284 1285 if (!rdev->mode_info.mode_config_initialized) 1286 return; 1287 1288 radeon_update_display_priority(rdev); 1289 1290 if (rdev->mode_info.crtcs[0]->base.enabled) 1291 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1292 if (rdev->mode_info.crtcs[1]->base.enabled) 1293 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1294 /* 1295 * Set display0/1 priority up in the memory controller for 1296 * modes if the user specifies HIGH for displaypriority 1297 * option. 1298 */ 1299 if ((rdev->disp_priority == 2) && 1300 (rdev->family == CHIP_RV515)) { 1301 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1302 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1303 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1304 if (mode1) 1305 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1306 if (mode0) 1307 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1308 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1309 } 1310 rv515_bandwidth_avivo_update(rdev); 1311 } 1312