1 /* $NetBSD: radeon_rs600.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 /* RS600 / Radeon X1250/X1270 integrated GPU 31 * 32 * This file gather function specific to RS600 which is the IGP of 33 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 34 * is the X1250/X1270 supporting AMD CPU). The display engine are 35 * the avivo one, bios is an atombios, 3D block are the one of the 36 * R4XX family. The GART is different from the RS400 one and is very 37 * close to the one of the R600 family (R600 likely being an evolution 38 * of the RS600 GART block). 39 */ 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: radeon_rs600.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 42 43 #include <drm/drmP.h> 44 #include "radeon.h" 45 #include "radeon_asic.h" 46 #include "radeon_audio.h" 47 #include "atom.h" 48 #include "rs600d.h" 49 50 #include "rs600_reg_safe.h" 51 52 static void rs600_gpu_init(struct radeon_device *rdev); 53 int rs600_mc_wait_for_idle(struct radeon_device *rdev); 54 55 static const u32 crtc_offsets[2] = 56 { 57 0, 58 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 59 }; 60 61 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 62 { 63 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 64 return true; 65 else 66 return false; 67 } 68 69 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 70 { 71 u32 pos1, pos2; 72 73 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 74 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 75 76 if (pos1 != pos2) 77 return true; 78 else 79 return false; 80 } 81 82 /** 83 * avivo_wait_for_vblank - vblank wait asic callback. 84 * 85 * @rdev: radeon_device pointer 86 * @crtc: crtc to wait for vblank on 87 * 88 * Wait for vblank on the requested crtc (r5xx-r7xx). 89 */ 90 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 91 { 92 unsigned i = 0; 93 94 if (crtc >= rdev->num_crtc) 95 return; 96 97 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 98 return; 99 100 /* depending on when we hit vblank, we may be close to active; if so, 101 * wait for another frame. 102 */ 103 while (avivo_is_in_vblank(rdev, crtc)) { 104 if (i++ % 100 == 0) { 105 if (!avivo_is_counter_moving(rdev, crtc)) 106 break; 107 } 108 } 109 110 while (!avivo_is_in_vblank(rdev, crtc)) { 111 if (i++ % 100 == 0) { 112 if (!avivo_is_counter_moving(rdev, crtc)) 113 break; 114 } 115 } 116 } 117 118 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 119 { 120 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 121 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 122 int i; 123 124 /* Lock the graphics update lock */ 125 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 126 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 127 128 /* update the scanout addresses */ 129 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 130 (u32)crtc_base); 131 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 132 (u32)crtc_base); 133 134 /* Wait for update_pending to go high. */ 135 for (i = 0; i < rdev->usec_timeout; i++) { 136 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 137 break; 138 udelay(1); 139 } 140 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 141 142 /* Unlock the lock, so double-buffering can take place inside vblank */ 143 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 144 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 145 } 146 147 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) 148 { 149 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 150 151 /* Return current update_pending status: */ 152 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & 153 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); 154 } 155 156 void avivo_program_fmt(struct drm_encoder *encoder) 157 { 158 struct drm_device *dev = encoder->dev; 159 struct radeon_device *rdev = dev->dev_private; 160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 161 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 162 int bpc = 0; 163 u32 tmp = 0; 164 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 165 166 if (connector) { 167 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 168 bpc = radeon_get_monitor_bpc(connector); 169 dither = radeon_connector->dither; 170 } 171 172 /* LVDS FMT is set up by atom */ 173 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 174 return; 175 176 if (bpc == 0) 177 return; 178 179 switch (bpc) { 180 case 6: 181 if (dither == RADEON_FMT_DITHER_ENABLE) 182 /* XXX sort out optimal dither settings */ 183 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 184 else 185 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; 186 break; 187 case 8: 188 if (dither == RADEON_FMT_DITHER_ENABLE) 189 /* XXX sort out optimal dither settings */ 190 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | 191 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); 192 else 193 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | 194 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); 195 break; 196 case 10: 197 default: 198 /* not needed */ 199 break; 200 } 201 202 switch (radeon_encoder->encoder_id) { 203 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 204 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); 205 break; 206 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 207 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); 208 break; 209 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 210 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); 211 break; 212 case ENCODER_OBJECT_ID_INTERNAL_DDI: 213 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); 214 break; 215 default: 216 break; 217 } 218 } 219 220 void rs600_pm_misc(struct radeon_device *rdev) 221 { 222 int requested_index = rdev->pm.requested_power_state_index; 223 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 224 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 225 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 226 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 227 228 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 229 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 230 tmp = RREG32(voltage->gpio.reg); 231 if (voltage->active_high) 232 tmp |= voltage->gpio.mask; 233 else 234 tmp &= ~(voltage->gpio.mask); 235 WREG32(voltage->gpio.reg, tmp); 236 if (voltage->delay) 237 udelay(voltage->delay); 238 } else { 239 tmp = RREG32(voltage->gpio.reg); 240 if (voltage->active_high) 241 tmp &= ~voltage->gpio.mask; 242 else 243 tmp |= voltage->gpio.mask; 244 WREG32(voltage->gpio.reg, tmp); 245 if (voltage->delay) 246 udelay(voltage->delay); 247 } 248 } else if (voltage->type == VOLTAGE_VDDC) 249 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 250 251 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 252 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 253 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 254 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 255 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 256 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 257 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 258 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 259 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 260 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 261 } 262 } else { 263 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 264 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 265 } 266 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 267 268 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 269 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 270 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 271 if (voltage->delay) { 272 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 273 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 274 } else 275 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 276 } else 277 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 278 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 279 280 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 281 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 282 hdp_dyn_cntl &= ~HDP_FORCEON; 283 else 284 hdp_dyn_cntl |= HDP_FORCEON; 285 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 286 #if 0 287 /* mc_host_dyn seems to cause hangs from time to time */ 288 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 289 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 290 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 291 else 292 mc_host_dyn_cntl |= MC_HOST_FORCEON; 293 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 294 #endif 295 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 296 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 297 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 298 else 299 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 300 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 301 302 /* set pcie lanes */ 303 if ((rdev->flags & RADEON_IS_PCIE) && 304 !(rdev->flags & RADEON_IS_IGP) && 305 rdev->asic->pm.set_pcie_lanes && 306 (ps->pcie_lanes != 307 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 308 radeon_set_pcie_lanes(rdev, 309 ps->pcie_lanes); 310 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 311 } 312 } 313 314 void rs600_pm_prepare(struct radeon_device *rdev) 315 { 316 struct drm_device *ddev = rdev->ddev; 317 struct drm_crtc *crtc; 318 struct radeon_crtc *radeon_crtc; 319 u32 tmp; 320 321 /* disable any active CRTCs */ 322 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 323 radeon_crtc = to_radeon_crtc(crtc); 324 if (radeon_crtc->enabled) { 325 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 326 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 327 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 328 } 329 } 330 } 331 332 void rs600_pm_finish(struct radeon_device *rdev) 333 { 334 struct drm_device *ddev = rdev->ddev; 335 struct drm_crtc *crtc; 336 struct radeon_crtc *radeon_crtc; 337 u32 tmp; 338 339 /* enable any active CRTCs */ 340 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 341 radeon_crtc = to_radeon_crtc(crtc); 342 if (radeon_crtc->enabled) { 343 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 344 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 345 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 346 } 347 } 348 } 349 350 /* hpd for digital panel detect/disconnect */ 351 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 352 { 353 u32 tmp; 354 bool connected = false; 355 356 switch (hpd) { 357 case RADEON_HPD_1: 358 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 359 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 360 connected = true; 361 break; 362 case RADEON_HPD_2: 363 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 364 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 365 connected = true; 366 break; 367 default: 368 break; 369 } 370 return connected; 371 } 372 373 void rs600_hpd_set_polarity(struct radeon_device *rdev, 374 enum radeon_hpd_id hpd) 375 { 376 u32 tmp; 377 bool connected = rs600_hpd_sense(rdev, hpd); 378 379 switch (hpd) { 380 case RADEON_HPD_1: 381 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 382 if (connected) 383 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 384 else 385 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 386 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 387 break; 388 case RADEON_HPD_2: 389 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 390 if (connected) 391 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 392 else 393 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 394 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 395 break; 396 default: 397 break; 398 } 399 } 400 401 void rs600_hpd_init(struct radeon_device *rdev) 402 { 403 struct drm_device *dev = rdev->ddev; 404 struct drm_connector *connector; 405 unsigned enable = 0; 406 407 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 408 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 409 switch (radeon_connector->hpd.hpd) { 410 case RADEON_HPD_1: 411 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 412 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 413 break; 414 case RADEON_HPD_2: 415 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 416 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 417 break; 418 default: 419 break; 420 } 421 enable |= 1 << radeon_connector->hpd.hpd; 422 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 423 } 424 radeon_irq_kms_enable_hpd(rdev, enable); 425 } 426 427 void rs600_hpd_fini(struct radeon_device *rdev) 428 { 429 struct drm_device *dev = rdev->ddev; 430 struct drm_connector *connector; 431 unsigned disable = 0; 432 433 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 434 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 435 switch (radeon_connector->hpd.hpd) { 436 case RADEON_HPD_1: 437 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 438 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 439 break; 440 case RADEON_HPD_2: 441 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 442 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 443 break; 444 default: 445 break; 446 } 447 disable |= 1 << radeon_connector->hpd.hpd; 448 } 449 radeon_irq_kms_disable_hpd(rdev, disable); 450 } 451 452 int rs600_asic_reset(struct radeon_device *rdev) 453 { 454 struct rv515_mc_save save; 455 u32 status, tmp; 456 int ret = 0; 457 458 status = RREG32(R_000E40_RBBM_STATUS); 459 if (!G_000E40_GUI_ACTIVE(status)) { 460 return 0; 461 } 462 /* Stops all mc clients */ 463 rv515_mc_stop(rdev, &save); 464 status = RREG32(R_000E40_RBBM_STATUS); 465 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 466 /* stop CP */ 467 WREG32(RADEON_CP_CSQ_CNTL, 0); 468 tmp = RREG32(RADEON_CP_RB_CNTL); 469 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 470 WREG32(RADEON_CP_RB_RPTR_WR, 0); 471 WREG32(RADEON_CP_RB_WPTR, 0); 472 WREG32(RADEON_CP_RB_CNTL, tmp); 473 pci_save_state(rdev->pdev); 474 /* disable bus mastering */ 475 pci_clear_master(rdev->pdev); 476 mdelay(1); 477 /* reset GA+VAP */ 478 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 479 S_0000F0_SOFT_RESET_GA(1)); 480 RREG32(R_0000F0_RBBM_SOFT_RESET); 481 mdelay(500); 482 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 483 mdelay(1); 484 status = RREG32(R_000E40_RBBM_STATUS); 485 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 486 /* reset CP */ 487 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 488 RREG32(R_0000F0_RBBM_SOFT_RESET); 489 mdelay(500); 490 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 491 mdelay(1); 492 status = RREG32(R_000E40_RBBM_STATUS); 493 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 494 /* reset MC */ 495 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 496 RREG32(R_0000F0_RBBM_SOFT_RESET); 497 mdelay(500); 498 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 499 mdelay(1); 500 status = RREG32(R_000E40_RBBM_STATUS); 501 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 502 /* restore PCI & busmastering */ 503 pci_restore_state(rdev->pdev); 504 /* Check if GPU is idle */ 505 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 506 dev_err(rdev->dev, "failed to reset GPU\n"); 507 ret = -1; 508 } else 509 dev_info(rdev->dev, "GPU reset succeed\n"); 510 rv515_mc_resume(rdev, &save); 511 return ret; 512 } 513 514 /* 515 * GART. 516 */ 517 void rs600_gart_tlb_flush(struct radeon_device *rdev) 518 { 519 uint32_t tmp; 520 521 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 522 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 523 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 524 525 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 526 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 527 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 528 529 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 530 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 531 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 532 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 533 } 534 535 static int rs600_gart_init(struct radeon_device *rdev) 536 { 537 int r; 538 539 if (rdev->gart.robj) { 540 WARN(1, "RS600 GART already initialized\n"); 541 return 0; 542 } 543 /* Initialize common gart structure */ 544 r = radeon_gart_init(rdev); 545 if (r) { 546 return r; 547 } 548 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 549 return radeon_gart_table_vram_alloc(rdev); 550 } 551 552 static int rs600_gart_enable(struct radeon_device *rdev) 553 { 554 u32 tmp; 555 int r, i; 556 557 if (rdev->gart.robj == NULL) { 558 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 559 return -EINVAL; 560 } 561 r = radeon_gart_table_vram_pin(rdev); 562 if (r) 563 return r; 564 /* Enable bus master */ 565 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 566 WREG32(RADEON_BUS_CNTL, tmp); 567 /* FIXME: setup default page */ 568 WREG32_MC(R_000100_MC_PT0_CNTL, 569 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 570 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 571 572 for (i = 0; i < 19; i++) { 573 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 574 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 575 S_00016C_SYSTEM_ACCESS_MODE_MASK( 576 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 577 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 578 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 579 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 580 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 581 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 582 } 583 /* enable first context */ 584 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 585 S_000102_ENABLE_PAGE_TABLE(1) | 586 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 587 588 /* disable all other contexts */ 589 for (i = 1; i < 8; i++) 590 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 591 592 /* setup the page table */ 593 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 594 rdev->gart.table_addr); 595 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 596 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 597 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 598 599 /* System context maps to VRAM space */ 600 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 601 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 602 603 /* enable page tables */ 604 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 605 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 606 tmp = RREG32_MC(R_000009_MC_CNTL1); 607 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 608 rs600_gart_tlb_flush(rdev); 609 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 610 (unsigned)(rdev->mc.gtt_size >> 20), 611 (unsigned long long)rdev->gart.table_addr); 612 rdev->gart.ready = true; 613 return 0; 614 } 615 616 static void rs600_gart_disable(struct radeon_device *rdev) 617 { 618 u32 tmp; 619 620 /* FIXME: disable out of gart access */ 621 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 622 tmp = RREG32_MC(R_000009_MC_CNTL1); 623 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 624 radeon_gart_table_vram_unpin(rdev); 625 } 626 627 static void rs600_gart_fini(struct radeon_device *rdev) 628 { 629 radeon_gart_fini(rdev); 630 rs600_gart_disable(rdev); 631 radeon_gart_table_vram_free(rdev); 632 } 633 634 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) 635 { 636 addr = addr & 0xFFFFFFFFFFFFF000ULL; 637 addr |= R600_PTE_SYSTEM; 638 if (flags & RADEON_GART_PAGE_VALID) 639 addr |= R600_PTE_VALID; 640 if (flags & RADEON_GART_PAGE_READ) 641 addr |= R600_PTE_READABLE; 642 if (flags & RADEON_GART_PAGE_WRITE) 643 addr |= R600_PTE_WRITEABLE; 644 if (flags & RADEON_GART_PAGE_SNOOP) 645 addr |= R600_PTE_SNOOPED; 646 return addr; 647 } 648 649 #ifdef __NetBSD__ 650 # define __iomem volatile 651 # define writeq fake_writeq 652 653 static inline void 654 fake_writeq(uint64_t v, void __iomem *ptr) 655 { 656 657 membar_producer(); 658 *(uint64_t __iomem *)ptr = v; 659 } 660 #endif 661 662 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 663 uint64_t entry) 664 { 665 void __iomem *ptr = (void *)rdev->gart.ptr; 666 writeq(entry, (char __iomem *)ptr + (i * 8)); 667 } 668 669 #ifdef __NetBSD__ 670 # undef writeq 671 # undef __iomem 672 #endif 673 674 int rs600_irq_set(struct radeon_device *rdev) 675 { 676 uint32_t tmp = 0; 677 uint32_t mode_int = 0; 678 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 679 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 680 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 681 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 682 u32 hdmi0; 683 if (ASIC_IS_DCE2(rdev)) 684 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 685 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 686 else 687 hdmi0 = 0; 688 689 if (!rdev->irq.installed) { 690 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 691 WREG32(R_000040_GEN_INT_CNTL, 0); 692 return -EINVAL; 693 } 694 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 695 tmp |= S_000040_SW_INT_EN(1); 696 } 697 if (rdev->irq.crtc_vblank_int[0] || 698 atomic_read(&rdev->irq.pflip[0])) { 699 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 700 } 701 if (rdev->irq.crtc_vblank_int[1] || 702 atomic_read(&rdev->irq.pflip[1])) { 703 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 704 } 705 if (rdev->irq.hpd[0]) { 706 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 707 } 708 if (rdev->irq.hpd[1]) { 709 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 710 } 711 if (rdev->irq.afmt[0]) { 712 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 713 } 714 WREG32(R_000040_GEN_INT_CNTL, tmp); 715 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 716 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 717 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 718 if (ASIC_IS_DCE2(rdev)) 719 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 720 721 /* posting read */ 722 RREG32(R_000040_GEN_INT_CNTL); 723 724 return 0; 725 } 726 727 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 728 { 729 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 730 uint32_t irq_mask = S_000044_SW_INT(1); 731 u32 tmp; 732 733 if (G_000044_DISPLAY_INT_STAT(irqs)) { 734 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 735 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 736 WREG32(R_006534_D1MODE_VBLANK_STATUS, 737 S_006534_D1MODE_VBLANK_ACK(1)); 738 } 739 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 740 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 741 S_006D34_D2MODE_VBLANK_ACK(1)); 742 } 743 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 744 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 745 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 746 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 747 } 748 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 749 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 750 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 751 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 752 } 753 } else { 754 rdev->irq.stat_regs.r500.disp_int = 0; 755 } 756 757 if (ASIC_IS_DCE2(rdev)) { 758 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 759 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 760 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 761 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 762 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 763 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 764 } 765 } else 766 rdev->irq.stat_regs.r500.hdmi0_status = 0; 767 768 if (irqs) { 769 WREG32(R_000044_GEN_INT_STATUS, irqs); 770 } 771 return irqs & irq_mask; 772 } 773 774 void rs600_irq_disable(struct radeon_device *rdev) 775 { 776 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 777 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 778 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 779 WREG32(R_000040_GEN_INT_CNTL, 0); 780 WREG32(R_006540_DxMODE_INT_MASK, 0); 781 /* Wait and acknowledge irq */ 782 mdelay(1); 783 rs600_irq_ack(rdev); 784 } 785 786 int rs600_irq_process(struct radeon_device *rdev) 787 { 788 u32 status, msi_rearm; 789 bool queue_hotplug = false; 790 bool queue_hdmi = false; 791 792 status = rs600_irq_ack(rdev); 793 if (!status && 794 !rdev->irq.stat_regs.r500.disp_int && 795 !rdev->irq.stat_regs.r500.hdmi0_status) { 796 return IRQ_NONE; 797 } 798 while (status || 799 rdev->irq.stat_regs.r500.disp_int || 800 rdev->irq.stat_regs.r500.hdmi0_status) { 801 /* SW interrupt */ 802 if (G_000044_SW_INT(status)) { 803 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 804 } 805 /* Vertical blank interrupts */ 806 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 807 if (rdev->irq.crtc_vblank_int[0]) { 808 drm_handle_vblank(rdev->ddev, 0); 809 #ifdef __NetBSD__ 810 spin_lock(&rdev->irq.vblank_lock); 811 rdev->pm.vblank_sync = true; 812 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 813 spin_unlock(&rdev->irq.vblank_lock); 814 #else 815 rdev->pm.vblank_sync = true; 816 wake_up(&rdev->irq.vblank_queue); 817 #endif 818 } 819 if (atomic_read(&rdev->irq.pflip[0])) 820 radeon_crtc_handle_vblank(rdev, 0); 821 } 822 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 823 if (rdev->irq.crtc_vblank_int[1]) { 824 drm_handle_vblank(rdev->ddev, 1); 825 #ifdef __NetBSD__ 826 spin_lock(&rdev->irq.vblank_lock); 827 rdev->pm.vblank_sync = true; 828 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 829 spin_unlock(&rdev->irq.vblank_lock); 830 #else 831 rdev->pm.vblank_sync = true; 832 wake_up(&rdev->irq.vblank_queue); 833 #endif 834 } 835 if (atomic_read(&rdev->irq.pflip[1])) 836 radeon_crtc_handle_vblank(rdev, 1); 837 } 838 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 839 queue_hotplug = true; 840 DRM_DEBUG("HPD1\n"); 841 } 842 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 843 queue_hotplug = true; 844 DRM_DEBUG("HPD2\n"); 845 } 846 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 847 queue_hdmi = true; 848 DRM_DEBUG("HDMI0\n"); 849 } 850 status = rs600_irq_ack(rdev); 851 } 852 if (queue_hotplug) 853 schedule_delayed_work(&rdev->hotplug_work, 0); 854 if (queue_hdmi) 855 schedule_work(&rdev->audio_work); 856 if (rdev->msi_enabled) { 857 switch (rdev->family) { 858 case CHIP_RS600: 859 case CHIP_RS690: 860 case CHIP_RS740: 861 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 862 WREG32(RADEON_BUS_CNTL, msi_rearm); 863 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 864 break; 865 default: 866 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 867 break; 868 } 869 } 870 return IRQ_HANDLED; 871 } 872 873 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 874 { 875 if (crtc == 0) 876 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 877 else 878 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 879 } 880 881 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 882 { 883 unsigned i; 884 885 for (i = 0; i < rdev->usec_timeout; i++) { 886 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 887 return 0; 888 udelay(1); 889 } 890 return -1; 891 } 892 893 static void rs600_gpu_init(struct radeon_device *rdev) 894 { 895 r420_pipes_init(rdev); 896 /* Wait for mc idle */ 897 if (rs600_mc_wait_for_idle(rdev)) 898 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 899 } 900 901 static void rs600_mc_init(struct radeon_device *rdev) 902 { 903 u64 base; 904 905 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 906 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 907 rdev->mc.vram_is_ddr = true; 908 rdev->mc.vram_width = 128; 909 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 910 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 911 rdev->mc.visible_vram_size = rdev->mc.aper_size; 912 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 913 base = RREG32_MC(R_000004_MC_FB_LOCATION); 914 base = G_000004_MC_FB_START(base) << 16; 915 radeon_vram_location(rdev, &rdev->mc, base); 916 rdev->mc.gtt_base_align = 0; 917 radeon_gtt_location(rdev, &rdev->mc); 918 radeon_update_bandwidth_info(rdev); 919 } 920 921 void rs600_bandwidth_update(struct radeon_device *rdev) 922 { 923 struct drm_display_mode *mode0 = NULL; 924 struct drm_display_mode *mode1 = NULL; 925 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 926 /* FIXME: implement full support */ 927 928 if (!rdev->mode_info.mode_config_initialized) 929 return; 930 931 radeon_update_display_priority(rdev); 932 933 if (rdev->mode_info.crtcs[0]->base.enabled) 934 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 935 if (rdev->mode_info.crtcs[1]->base.enabled) 936 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 937 938 rs690_line_buffer_adjust(rdev, mode0, mode1); 939 940 if (rdev->disp_priority == 2) { 941 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 942 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 943 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 944 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 945 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 946 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 947 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 948 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 949 } 950 } 951 952 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 953 { 954 unsigned long flags; 955 u32 r; 956 957 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 958 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 959 S_000070_MC_IND_CITF_ARB0(1)); 960 r = RREG32(R_000074_MC_IND_DATA); 961 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 962 return r; 963 } 964 965 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 966 { 967 unsigned long flags; 968 969 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 970 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 971 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 972 WREG32(R_000074_MC_IND_DATA, v); 973 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 974 } 975 976 static void rs600_debugfs(struct radeon_device *rdev) 977 { 978 if (r100_debugfs_rbbm_init(rdev)) 979 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 980 } 981 982 void rs600_set_safe_registers(struct radeon_device *rdev) 983 { 984 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 985 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 986 } 987 988 static void rs600_mc_program(struct radeon_device *rdev) 989 { 990 struct rv515_mc_save save; 991 992 /* Stops all mc clients */ 993 rv515_mc_stop(rdev, &save); 994 995 /* Wait for mc idle */ 996 if (rs600_mc_wait_for_idle(rdev)) 997 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 998 999 /* FIXME: What does AGP means for such chipset ? */ 1000 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 1001 WREG32_MC(R_000006_AGP_BASE, 0); 1002 WREG32_MC(R_000007_AGP_BASE_2, 0); 1003 /* Program MC */ 1004 WREG32_MC(R_000004_MC_FB_LOCATION, 1005 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 1006 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1007 WREG32(R_000134_HDP_FB_LOCATION, 1008 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 1009 1010 rv515_mc_resume(rdev, &save); 1011 } 1012 1013 static int rs600_startup(struct radeon_device *rdev) 1014 { 1015 int r; 1016 1017 rs600_mc_program(rdev); 1018 /* Resume clock */ 1019 rv515_clock_startup(rdev); 1020 /* Initialize GPU configuration (# pipes, ...) */ 1021 rs600_gpu_init(rdev); 1022 /* Initialize GART (initialize after TTM so we can allocate 1023 * memory through TTM but finalize after TTM) */ 1024 r = rs600_gart_enable(rdev); 1025 if (r) 1026 return r; 1027 1028 /* allocate wb buffer */ 1029 r = radeon_wb_init(rdev); 1030 if (r) 1031 return r; 1032 1033 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1034 if (r) { 1035 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1036 return r; 1037 } 1038 1039 /* Enable IRQ */ 1040 if (!rdev->irq.installed) { 1041 r = radeon_irq_kms_init(rdev); 1042 if (r) 1043 return r; 1044 } 1045 1046 rs600_irq_set(rdev); 1047 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1048 /* 1M ring buffer */ 1049 r = r100_cp_init(rdev, 1024 * 1024); 1050 if (r) { 1051 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1052 return r; 1053 } 1054 1055 r = radeon_ib_pool_init(rdev); 1056 if (r) { 1057 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1058 return r; 1059 } 1060 1061 r = radeon_audio_init(rdev); 1062 if (r) { 1063 dev_err(rdev->dev, "failed initializing audio\n"); 1064 return r; 1065 } 1066 1067 return 0; 1068 } 1069 1070 int rs600_resume(struct radeon_device *rdev) 1071 { 1072 int r; 1073 1074 /* Make sur GART are not working */ 1075 rs600_gart_disable(rdev); 1076 /* Resume clock before doing reset */ 1077 rv515_clock_startup(rdev); 1078 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1079 if (radeon_asic_reset(rdev)) { 1080 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1081 RREG32(R_000E40_RBBM_STATUS), 1082 RREG32(R_0007C0_CP_STAT)); 1083 } 1084 /* post */ 1085 atom_asic_init(rdev->mode_info.atom_context); 1086 /* Resume clock after posting */ 1087 rv515_clock_startup(rdev); 1088 /* Initialize surface registers */ 1089 radeon_surface_init(rdev); 1090 1091 rdev->accel_working = true; 1092 r = rs600_startup(rdev); 1093 if (r) { 1094 rdev->accel_working = false; 1095 } 1096 return r; 1097 } 1098 1099 int rs600_suspend(struct radeon_device *rdev) 1100 { 1101 radeon_pm_suspend(rdev); 1102 radeon_audio_fini(rdev); 1103 r100_cp_disable(rdev); 1104 radeon_wb_disable(rdev); 1105 rs600_irq_disable(rdev); 1106 rs600_gart_disable(rdev); 1107 return 0; 1108 } 1109 1110 void rs600_fini(struct radeon_device *rdev) 1111 { 1112 radeon_pm_fini(rdev); 1113 radeon_audio_fini(rdev); 1114 r100_cp_fini(rdev); 1115 radeon_wb_fini(rdev); 1116 radeon_ib_pool_fini(rdev); 1117 radeon_gem_fini(rdev); 1118 rs600_gart_fini(rdev); 1119 radeon_irq_kms_fini(rdev); 1120 radeon_fence_driver_fini(rdev); 1121 radeon_bo_fini(rdev); 1122 radeon_atombios_fini(rdev); 1123 kfree(rdev->bios); 1124 rdev->bios = NULL; 1125 } 1126 1127 int rs600_init(struct radeon_device *rdev) 1128 { 1129 int r; 1130 1131 /* Disable VGA */ 1132 rv515_vga_render_disable(rdev); 1133 /* Initialize scratch registers */ 1134 radeon_scratch_init(rdev); 1135 /* Initialize surface registers */ 1136 radeon_surface_init(rdev); 1137 /* restore some register to sane defaults */ 1138 r100_restore_sanity(rdev); 1139 /* BIOS */ 1140 if (!radeon_get_bios(rdev)) { 1141 if (ASIC_IS_AVIVO(rdev)) 1142 return -EINVAL; 1143 } 1144 if (rdev->is_atom_bios) { 1145 r = radeon_atombios_init(rdev); 1146 if (r) 1147 return r; 1148 } else { 1149 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1150 return -EINVAL; 1151 } 1152 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1153 if (radeon_asic_reset(rdev)) { 1154 dev_warn(rdev->dev, 1155 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1156 RREG32(R_000E40_RBBM_STATUS), 1157 RREG32(R_0007C0_CP_STAT)); 1158 } 1159 /* check if cards are posted or not */ 1160 if (radeon_boot_test_post_card(rdev) == false) 1161 return -EINVAL; 1162 1163 /* Initialize clocks */ 1164 radeon_get_clock_info(rdev->ddev); 1165 /* initialize memory controller */ 1166 rs600_mc_init(rdev); 1167 rs600_debugfs(rdev); 1168 /* Fence driver */ 1169 r = radeon_fence_driver_init(rdev); 1170 if (r) 1171 return r; 1172 /* Memory manager */ 1173 r = radeon_bo_init(rdev); 1174 if (r) 1175 return r; 1176 r = rs600_gart_init(rdev); 1177 if (r) 1178 return r; 1179 rs600_set_safe_registers(rdev); 1180 1181 /* Initialize power management */ 1182 radeon_pm_init(rdev); 1183 1184 rdev->accel_working = true; 1185 r = rs600_startup(rdev); 1186 if (r) { 1187 /* Somethings want wront with the accel init stop accel */ 1188 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1189 r100_cp_fini(rdev); 1190 radeon_wb_fini(rdev); 1191 radeon_ib_pool_fini(rdev); 1192 rs600_gart_fini(rdev); 1193 radeon_irq_kms_fini(rdev); 1194 rdev->accel_working = false; 1195 } 1196 return 0; 1197 } 1198