1 /* $NetBSD: radeon_r600_dpm.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_r600_dpm.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 29 30 #include "drmP.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "r600d.h" 34 #include "r600_dpm.h" 35 #include "atom.h" 36 37 const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 38 { 39 R600_UTC_DFLT_00, 40 R600_UTC_DFLT_01, 41 R600_UTC_DFLT_02, 42 R600_UTC_DFLT_03, 43 R600_UTC_DFLT_04, 44 R600_UTC_DFLT_05, 45 R600_UTC_DFLT_06, 46 R600_UTC_DFLT_07, 47 R600_UTC_DFLT_08, 48 R600_UTC_DFLT_09, 49 R600_UTC_DFLT_10, 50 R600_UTC_DFLT_11, 51 R600_UTC_DFLT_12, 52 R600_UTC_DFLT_13, 53 R600_UTC_DFLT_14, 54 }; 55 56 const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 57 { 58 R600_DTC_DFLT_00, 59 R600_DTC_DFLT_01, 60 R600_DTC_DFLT_02, 61 R600_DTC_DFLT_03, 62 R600_DTC_DFLT_04, 63 R600_DTC_DFLT_05, 64 R600_DTC_DFLT_06, 65 R600_DTC_DFLT_07, 66 R600_DTC_DFLT_08, 67 R600_DTC_DFLT_09, 68 R600_DTC_DFLT_10, 69 R600_DTC_DFLT_11, 70 R600_DTC_DFLT_12, 71 R600_DTC_DFLT_13, 72 R600_DTC_DFLT_14, 73 }; 74 75 void r600_dpm_print_class_info(u32 class, u32 class2) 76 { 77 printk("\tui class: "); 78 switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 79 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 80 default: 81 printk("none\n"); 82 break; 83 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 84 printk("battery\n"); 85 break; 86 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 87 printk("balanced\n"); 88 break; 89 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 90 printk("performance\n"); 91 break; 92 } 93 printk("\tinternal class: "); 94 if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && 95 (class2 == 0)) 96 printk("none"); 97 else { 98 if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) 99 printk("boot "); 100 if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 101 printk("thermal "); 102 if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) 103 printk("limited_pwr "); 104 if (class & ATOM_PPLIB_CLASSIFICATION_REST) 105 printk("rest "); 106 if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) 107 printk("forced "); 108 if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 109 printk("3d_perf "); 110 if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) 111 printk("ovrdrv "); 112 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 113 printk("uvd "); 114 if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) 115 printk("3d_low "); 116 if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) 117 printk("acpi "); 118 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 119 printk("uvd_hd2 "); 120 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 121 printk("uvd_hd "); 122 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 123 printk("uvd_sd "); 124 if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) 125 printk("limited_pwr2 "); 126 if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 127 printk("ulv "); 128 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 129 printk("uvd_mvc "); 130 } 131 printk("\n"); 132 } 133 134 void r600_dpm_print_cap_info(u32 caps) 135 { 136 printk("\tcaps: "); 137 if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 138 printk("single_disp "); 139 if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) 140 printk("video "); 141 if (caps & ATOM_PPLIB_DISALLOW_ON_DC) 142 printk("no_dc "); 143 printk("\n"); 144 } 145 146 void r600_dpm_print_ps_status(struct radeon_device *rdev, 147 struct radeon_ps *rps) 148 { 149 printk("\tstatus: "); 150 if (rps == rdev->pm.dpm.current_ps) 151 printk("c "); 152 if (rps == rdev->pm.dpm.requested_ps) 153 printk("r "); 154 if (rps == rdev->pm.dpm.boot_ps) 155 printk("b "); 156 printk("\n"); 157 } 158 159 u32 r600_dpm_get_vblank_time(struct radeon_device *rdev) 160 { 161 struct drm_device *dev = rdev->ddev; 162 struct drm_crtc *crtc; 163 struct radeon_crtc *radeon_crtc; 164 u32 vblank_in_pixels; 165 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */ 166 167 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 168 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 169 radeon_crtc = to_radeon_crtc(crtc); 170 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 171 vblank_in_pixels = 172 radeon_crtc->hw_mode.crtc_htotal * 173 (radeon_crtc->hw_mode.crtc_vblank_end - 174 radeon_crtc->hw_mode.crtc_vdisplay + 175 (radeon_crtc->v_border * 2)); 176 177 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock; 178 break; 179 } 180 } 181 } 182 183 return vblank_time_us; 184 } 185 186 u32 r600_dpm_get_vrefresh(struct radeon_device *rdev) 187 { 188 struct drm_device *dev = rdev->ddev; 189 struct drm_crtc *crtc; 190 struct radeon_crtc *radeon_crtc; 191 u32 vrefresh = 0; 192 193 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 194 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 195 radeon_crtc = to_radeon_crtc(crtc); 196 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 197 vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode); 198 break; 199 } 200 } 201 } 202 return vrefresh; 203 } 204 205 void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 206 u32 *p, u32 *u) 207 { 208 u32 b_c = 0; 209 u32 i_c; 210 u32 tmp; 211 212 i_c = (i * r_c) / 100; 213 tmp = i_c >> p_b; 214 215 while (tmp) { 216 b_c++; 217 tmp >>= 1; 218 } 219 220 *u = (b_c + 1) / 2; 221 *p = i_c / (1 << (2 * (*u))); 222 } 223 224 int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 225 { 226 u32 k, a, ah, al; 227 u32 t1; 228 229 if ((fl == 0) || (fh == 0) || (fl > fh)) 230 return -EINVAL; 231 232 k = (100 * fh) / fl; 233 t1 = (t * (k - 100)); 234 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 235 a = (a + 5) / 10; 236 ah = ((a * t) + 5000) / 10000; 237 al = a - ah; 238 239 *th = t - ah; 240 *tl = t + al; 241 242 return 0; 243 } 244 245 void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) 246 { 247 int i; 248 249 if (enable) { 250 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 251 } else { 252 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 253 254 WREG32(CG_RLC_REQ_AND_RSP, 0x2); 255 256 for (i = 0; i < rdev->usec_timeout; i++) { 257 if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1) 258 break; 259 udelay(1); 260 } 261 262 WREG32(CG_RLC_REQ_AND_RSP, 0x0); 263 264 WREG32(GRBM_PWR_CNTL, 0x1); 265 RREG32(GRBM_PWR_CNTL); 266 } 267 } 268 269 void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable) 270 { 271 if (enable) 272 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 273 else 274 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 275 } 276 277 void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable) 278 { 279 if (enable) 280 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 281 else 282 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 283 } 284 285 void r600_enable_acpi_pm(struct radeon_device *rdev) 286 { 287 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 288 } 289 290 void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable) 291 { 292 if (enable) 293 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); 294 else 295 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); 296 } 297 298 bool r600_dynamicpm_enabled(struct radeon_device *rdev) 299 { 300 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) 301 return true; 302 else 303 return false; 304 } 305 306 void r600_enable_sclk_control(struct radeon_device *rdev, bool enable) 307 { 308 if (enable) 309 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 310 else 311 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 312 } 313 314 void r600_enable_mclk_control(struct radeon_device *rdev, bool enable) 315 { 316 if (enable) 317 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); 318 else 319 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); 320 } 321 322 void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable) 323 { 324 if (enable) 325 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); 326 else 327 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); 328 } 329 330 void r600_wait_for_spll_change(struct radeon_device *rdev) 331 { 332 int i; 333 334 for (i = 0; i < rdev->usec_timeout; i++) { 335 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) 336 break; 337 udelay(1); 338 } 339 } 340 341 void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p) 342 { 343 WREG32(CG_BSP, BSP(p) | BSU(u)); 344 } 345 346 void r600_set_at(struct radeon_device *rdev, 347 u32 l_to_m, u32 m_to_h, 348 u32 h_to_m, u32 m_to_l) 349 { 350 WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h)); 351 WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l)); 352 } 353 354 void r600_set_tc(struct radeon_device *rdev, 355 u32 index, u32 u_t, u32 d_t) 356 { 357 WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t)); 358 } 359 360 void r600_select_td(struct radeon_device *rdev, 361 enum r600_td td) 362 { 363 if (td == R600_TD_AUTO) 364 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 365 else 366 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 367 if (td == R600_TD_UP) 368 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 369 if (td == R600_TD_DOWN) 370 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 371 } 372 373 void r600_set_vrc(struct radeon_device *rdev, u32 vrv) 374 { 375 WREG32(CG_FTV, vrv); 376 } 377 378 void r600_set_tpu(struct radeon_device *rdev, u32 u) 379 { 380 WREG32_P(CG_TPC, TPU(u), ~TPU_MASK); 381 } 382 383 void r600_set_tpc(struct radeon_device *rdev, u32 c) 384 { 385 WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK); 386 } 387 388 void r600_set_sstu(struct radeon_device *rdev, u32 u) 389 { 390 WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK); 391 } 392 393 void r600_set_sst(struct radeon_device *rdev, u32 t) 394 { 395 WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK); 396 } 397 398 void r600_set_git(struct radeon_device *rdev, u32 t) 399 { 400 WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK); 401 } 402 403 void r600_set_fctu(struct radeon_device *rdev, u32 u) 404 { 405 WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK); 406 } 407 408 void r600_set_fct(struct radeon_device *rdev, u32 t) 409 { 410 WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK); 411 } 412 413 void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p) 414 { 415 WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK); 416 } 417 418 void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s) 419 { 420 WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK); 421 } 422 423 void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u) 424 { 425 WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK); 426 } 427 428 void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p) 429 { 430 WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK); 431 } 432 433 void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s) 434 { 435 WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK); 436 } 437 438 void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time) 439 { 440 WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK); 441 } 442 443 void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time) 444 { 445 WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK); 446 } 447 448 void r600_engine_clock_entry_enable(struct radeon_device *rdev, 449 u32 index, bool enable) 450 { 451 if (enable) 452 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 453 STEP_0_SPLL_ENTRY_VALID, ~STEP_0_SPLL_ENTRY_VALID); 454 else 455 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 456 0, ~STEP_0_SPLL_ENTRY_VALID); 457 } 458 459 void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev, 460 u32 index, bool enable) 461 { 462 if (enable) 463 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 464 STEP_0_SPLL_STEP_ENABLE, ~STEP_0_SPLL_STEP_ENABLE); 465 else 466 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 467 0, ~STEP_0_SPLL_STEP_ENABLE); 468 } 469 470 void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev, 471 u32 index, bool enable) 472 { 473 if (enable) 474 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 475 STEP_0_POST_DIV_EN, ~STEP_0_POST_DIV_EN); 476 else 477 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 478 0, ~STEP_0_POST_DIV_EN); 479 } 480 481 void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, 482 u32 index, u32 divider) 483 { 484 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 485 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK); 486 } 487 488 void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, 489 u32 index, u32 divider) 490 { 491 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 492 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK); 493 } 494 495 void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, 496 u32 index, u32 divider) 497 { 498 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 499 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK); 500 } 501 502 void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev, 503 u32 index, u32 step_time) 504 { 505 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 506 STEP_0_SPLL_STEP_TIME(step_time), ~STEP_0_SPLL_STEP_TIME_MASK); 507 } 508 509 void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u) 510 { 511 WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK); 512 } 513 514 void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u) 515 { 516 WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK); 517 } 518 519 void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt) 520 { 521 WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK); 522 } 523 524 void r600_voltage_control_enable_pins(struct radeon_device *rdev, 525 u64 mask) 526 { 527 WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff); 528 WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask)); 529 } 530 531 532 void r600_voltage_control_program_voltages(struct radeon_device *rdev, 533 enum r600_power_level index, u64 pins) 534 { 535 u32 tmp, mask; 536 u32 ix = 3 - (3 & index); 537 538 WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff); 539 540 mask = 7 << (3 * ix); 541 tmp = RREG32(VID_UPPER_GPIO_CNTL); 542 tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask); 543 WREG32(VID_UPPER_GPIO_CNTL, tmp); 544 } 545 546 void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev, 547 u64 mask) 548 { 549 u32 gpio; 550 551 gpio = RREG32(GPIOPAD_MASK); 552 gpio &= ~mask; 553 WREG32(GPIOPAD_MASK, gpio); 554 555 gpio = RREG32(GPIOPAD_EN); 556 gpio &= ~mask; 557 WREG32(GPIOPAD_EN, gpio); 558 559 gpio = RREG32(GPIOPAD_A); 560 gpio &= ~mask; 561 WREG32(GPIOPAD_A, gpio); 562 } 563 564 void r600_power_level_enable(struct radeon_device *rdev, 565 enum r600_power_level index, bool enable) 566 { 567 u32 ix = 3 - (3 & index); 568 569 if (enable) 570 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE, 571 ~CTXSW_FREQ_STATE_ENABLE); 572 else 573 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0, 574 ~CTXSW_FREQ_STATE_ENABLE); 575 } 576 577 void r600_power_level_set_voltage_index(struct radeon_device *rdev, 578 enum r600_power_level index, u32 voltage_index) 579 { 580 u32 ix = 3 - (3 & index); 581 582 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 583 CTXSW_FREQ_VIDS_CFG_INDEX(voltage_index), ~CTXSW_FREQ_VIDS_CFG_INDEX_MASK); 584 } 585 586 void r600_power_level_set_mem_clock_index(struct radeon_device *rdev, 587 enum r600_power_level index, u32 mem_clock_index) 588 { 589 u32 ix = 3 - (3 & index); 590 591 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 592 CTXSW_FREQ_MCLK_CFG_INDEX(mem_clock_index), ~CTXSW_FREQ_MCLK_CFG_INDEX_MASK); 593 } 594 595 void r600_power_level_set_eng_clock_index(struct radeon_device *rdev, 596 enum r600_power_level index, u32 eng_clock_index) 597 { 598 u32 ix = 3 - (3 & index); 599 600 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 601 CTXSW_FREQ_SCLK_CFG_INDEX(eng_clock_index), ~CTXSW_FREQ_SCLK_CFG_INDEX_MASK); 602 } 603 604 void r600_power_level_set_watermark_id(struct radeon_device *rdev, 605 enum r600_power_level index, 606 enum r600_display_watermark watermark_id) 607 { 608 u32 ix = 3 - (3 & index); 609 u32 tmp = 0; 610 611 if (watermark_id == R600_DISPLAY_WATERMARK_HIGH) 612 tmp = CTXSW_FREQ_DISPLAY_WATERMARK; 613 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK); 614 } 615 616 void r600_power_level_set_pcie_gen2(struct radeon_device *rdev, 617 enum r600_power_level index, bool compatible) 618 { 619 u32 ix = 3 - (3 & index); 620 u32 tmp = 0; 621 622 if (compatible) 623 tmp = CTXSW_FREQ_GEN2PCIE_VOLT; 624 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT); 625 } 626 627 enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev) 628 { 629 u32 tmp; 630 631 tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK; 632 tmp >>= CURRENT_PROFILE_INDEX_SHIFT; 633 return tmp; 634 } 635 636 enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev) 637 { 638 u32 tmp; 639 640 tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK; 641 tmp >>= TARGET_PROFILE_INDEX_SHIFT; 642 return tmp; 643 } 644 645 void r600_power_level_set_enter_index(struct radeon_device *rdev, 646 enum r600_power_level index) 647 { 648 WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index), 649 ~DYN_PWR_ENTER_INDEX_MASK); 650 } 651 652 void r600_wait_for_power_level_unequal(struct radeon_device *rdev, 653 enum r600_power_level index) 654 { 655 int i; 656 657 for (i = 0; i < rdev->usec_timeout; i++) { 658 if (r600_power_level_get_target_index(rdev) != index) 659 break; 660 udelay(1); 661 } 662 663 for (i = 0; i < rdev->usec_timeout; i++) { 664 if (r600_power_level_get_current_index(rdev) != index) 665 break; 666 udelay(1); 667 } 668 } 669 670 void r600_wait_for_power_level(struct radeon_device *rdev, 671 enum r600_power_level index) 672 { 673 int i; 674 675 for (i = 0; i < rdev->usec_timeout; i++) { 676 if (r600_power_level_get_target_index(rdev) == index) 677 break; 678 udelay(1); 679 } 680 681 for (i = 0; i < rdev->usec_timeout; i++) { 682 if (r600_power_level_get_current_index(rdev) == index) 683 break; 684 udelay(1); 685 } 686 } 687 688 void r600_start_dpm(struct radeon_device *rdev) 689 { 690 r600_enable_sclk_control(rdev, false); 691 r600_enable_mclk_control(rdev, false); 692 693 r600_dynamicpm_enable(rdev, true); 694 695 radeon_wait_for_vblank(rdev, 0); 696 radeon_wait_for_vblank(rdev, 1); 697 698 r600_enable_spll_bypass(rdev, true); 699 r600_wait_for_spll_change(rdev); 700 r600_enable_spll_bypass(rdev, false); 701 r600_wait_for_spll_change(rdev); 702 703 r600_enable_spll_bypass(rdev, true); 704 r600_wait_for_spll_change(rdev); 705 r600_enable_spll_bypass(rdev, false); 706 r600_wait_for_spll_change(rdev); 707 708 r600_enable_sclk_control(rdev, true); 709 r600_enable_mclk_control(rdev, true); 710 } 711 712 void r600_stop_dpm(struct radeon_device *rdev) 713 { 714 r600_dynamicpm_enable(rdev, false); 715 } 716 717 int r600_dpm_pre_set_power_state(struct radeon_device *rdev) 718 { 719 return 0; 720 } 721 722 void r600_dpm_post_set_power_state(struct radeon_device *rdev) 723 { 724 725 } 726 727 bool r600_is_uvd_state(u32 class, u32 class2) 728 { 729 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 730 return true; 731 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 732 return true; 733 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 734 return true; 735 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 736 return true; 737 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 738 return true; 739 return false; 740 } 741 742 static int r600_set_thermal_temperature_range(struct radeon_device *rdev, 743 int min_temp, int max_temp) 744 { 745 int low_temp = 0 * 1000; 746 int high_temp = 255 * 1000; 747 748 if (low_temp < min_temp) 749 low_temp = min_temp; 750 if (high_temp > max_temp) 751 high_temp = max_temp; 752 if (high_temp < low_temp) { 753 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 754 return -EINVAL; 755 } 756 757 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 758 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 759 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 760 761 rdev->pm.dpm.thermal.min_temp = low_temp; 762 rdev->pm.dpm.thermal.max_temp = high_temp; 763 764 return 0; 765 } 766 767 bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor) 768 { 769 switch (sensor) { 770 case THERMAL_TYPE_RV6XX: 771 case THERMAL_TYPE_RV770: 772 case THERMAL_TYPE_EVERGREEN: 773 case THERMAL_TYPE_SUMO: 774 case THERMAL_TYPE_NI: 775 case THERMAL_TYPE_SI: 776 case THERMAL_TYPE_CI: 777 case THERMAL_TYPE_KV: 778 return true; 779 case THERMAL_TYPE_ADT7473_WITH_INTERNAL: 780 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 781 return false; /* need special handling */ 782 case THERMAL_TYPE_NONE: 783 case THERMAL_TYPE_EXTERNAL: 784 case THERMAL_TYPE_EXTERNAL_GPIO: 785 default: 786 return false; 787 } 788 } 789 790 int r600_dpm_late_enable(struct radeon_device *rdev) 791 { 792 int ret; 793 794 if (rdev->irq.installed && 795 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 796 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 797 if (ret) 798 return ret; 799 rdev->irq.dpm_thermal = true; 800 radeon_irq_set(rdev); 801 } 802 803 return 0; 804 } 805 806 union power_info { 807 struct _ATOM_POWERPLAY_INFO info; 808 struct _ATOM_POWERPLAY_INFO_V2 info_2; 809 struct _ATOM_POWERPLAY_INFO_V3 info_3; 810 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 811 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 812 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 813 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 814 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 815 }; 816 817 union fan_info { 818 struct _ATOM_PPLIB_FANTABLE fan; 819 struct _ATOM_PPLIB_FANTABLE2 fan2; 820 struct _ATOM_PPLIB_FANTABLE3 fan3; 821 }; 822 823 static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table *radeon_table, 824 ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table) 825 { 826 u32 size = atom_table->ucNumEntries * 827 sizeof(struct radeon_clock_voltage_dependency_entry); 828 int i; 829 ATOM_PPLIB_Clock_Voltage_Dependency_Record *entry; 830 831 radeon_table->entries = kzalloc(size, GFP_KERNEL); 832 if (!radeon_table->entries) 833 return -ENOMEM; 834 835 entry = &atom_table->entries[0]; 836 for (i = 0; i < atom_table->ucNumEntries; i++) { 837 radeon_table->entries[i].clk = le16_to_cpu(entry->usClockLow) | 838 (entry->ucClockHigh << 16); 839 radeon_table->entries[i].v = le16_to_cpu(entry->usVoltage); 840 entry = (ATOM_PPLIB_Clock_Voltage_Dependency_Record *) 841 ((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record)); 842 } 843 radeon_table->count = atom_table->ucNumEntries; 844 845 return 0; 846 } 847 848 int r600_get_platform_caps(struct radeon_device *rdev) 849 { 850 struct radeon_mode_info *mode_info = &rdev->mode_info; 851 union power_info *power_info; 852 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 853 u16 data_offset; 854 u8 frev, crev; 855 856 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 857 &frev, &crev, &data_offset)) 858 return -EINVAL; 859 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 860 861 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 862 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 863 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 864 865 return 0; 866 } 867 868 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 869 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 870 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 871 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 872 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 873 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 874 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 875 876 int r600_parse_extended_power_table(struct radeon_device *rdev) 877 { 878 struct radeon_mode_info *mode_info = &rdev->mode_info; 879 union power_info *power_info; 880 union fan_info *fan_info; 881 ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table; 882 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 883 u16 data_offset; 884 u8 frev, crev; 885 int ret, i; 886 887 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 888 &frev, &crev, &data_offset)) 889 return -EINVAL; 890 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 891 892 /* fan table */ 893 if (le16_to_cpu(power_info->pplib.usTableSize) >= 894 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) { 895 if (power_info->pplib3.usFanTableOffset) { 896 fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset + 897 le16_to_cpu(power_info->pplib3.usFanTableOffset)); 898 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; 899 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); 900 rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); 901 rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); 902 rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); 903 rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); 904 rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); 905 if (fan_info->fan.ucFanTableFormat >= 2) 906 rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); 907 else 908 rdev->pm.dpm.fan.t_max = 10900; 909 rdev->pm.dpm.fan.cycle_delay = 100000; 910 if (fan_info->fan.ucFanTableFormat >= 3) { 911 rdev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; 912 rdev->pm.dpm.fan.default_max_fan_pwm = 913 le16_to_cpu(fan_info->fan3.usFanPWMMax); 914 rdev->pm.dpm.fan.default_fan_output_sensitivity = 4836; 915 rdev->pm.dpm.fan.fan_output_sensitivity = 916 le16_to_cpu(fan_info->fan3.usFanOutputSensitivity); 917 } 918 rdev->pm.dpm.fan.ucode_fan_control = true; 919 } 920 } 921 922 /* clock dependancy tables, shedding tables */ 923 if (le16_to_cpu(power_info->pplib.usTableSize) >= 924 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) { 925 if (power_info->pplib4.usVddcDependencyOnSCLKOffset) { 926 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) 927 (mode_info->atom_context->bios + data_offset + 928 le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); 929 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 930 dep_table); 931 if (ret) 932 return ret; 933 } 934 if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { 935 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) 936 (mode_info->atom_context->bios + data_offset + 937 le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); 938 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 939 dep_table); 940 if (ret) { 941 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); 942 return ret; 943 } 944 } 945 if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { 946 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) 947 (mode_info->atom_context->bios + data_offset + 948 le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); 949 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 950 dep_table); 951 if (ret) { 952 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); 953 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); 954 return ret; 955 } 956 } 957 if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { 958 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) 959 (mode_info->atom_context->bios + data_offset + 960 le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); 961 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 962 dep_table); 963 if (ret) { 964 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); 965 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); 966 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); 967 return ret; 968 } 969 } 970 if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { 971 ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v = 972 (ATOM_PPLIB_Clock_Voltage_Limit_Table *) 973 (mode_info->atom_context->bios + data_offset + 974 le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset)); 975 if (clk_v->ucNumEntries) { 976 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = 977 le16_to_cpu(clk_v->entries[0].usSclkLow) | 978 (clk_v->entries[0].ucSclkHigh << 16); 979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = 980 le16_to_cpu(clk_v->entries[0].usMclkLow) | 981 (clk_v->entries[0].ucMclkHigh << 16); 982 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = 983 le16_to_cpu(clk_v->entries[0].usVddc); 984 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = 985 le16_to_cpu(clk_v->entries[0].usVddci); 986 } 987 } 988 if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) { 989 ATOM_PPLIB_PhaseSheddingLimits_Table *psl = 990 (ATOM_PPLIB_PhaseSheddingLimits_Table *) 991 (mode_info->atom_context->bios + data_offset + 992 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset)); 993 ATOM_PPLIB_PhaseSheddingLimits_Record *entry; 994 995 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = 996 kzalloc(psl->ucNumEntries * 997 sizeof(struct radeon_phase_shedding_limits_entry), 998 GFP_KERNEL); 999 if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { 1000 r600_free_extended_power_table(rdev); 1001 return -ENOMEM; 1002 } 1003 1004 entry = &psl->entries[0]; 1005 for (i = 0; i < psl->ucNumEntries; i++) { 1006 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = 1007 le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16); 1008 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = 1009 le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16); 1010 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = 1011 le16_to_cpu(entry->usVoltage); 1012 entry = (ATOM_PPLIB_PhaseSheddingLimits_Record *) 1013 ((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record)); 1014 } 1015 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count = 1016 psl->ucNumEntries; 1017 } 1018 } 1019 1020 /* cac data */ 1021 if (le16_to_cpu(power_info->pplib.usTableSize) >= 1022 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) { 1023 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); 1024 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); 1025 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit; 1026 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); 1027 if (rdev->pm.dpm.tdp_od_limit) 1028 rdev->pm.dpm.power_control = true; 1029 else 1030 rdev->pm.dpm.power_control = false; 1031 rdev->pm.dpm.tdp_adjustment = 0; 1032 rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); 1033 rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); 1034 rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); 1035 if (power_info->pplib5.usCACLeakageTableOffset) { 1036 ATOM_PPLIB_CAC_Leakage_Table *cac_table = 1037 (ATOM_PPLIB_CAC_Leakage_Table *) 1038 (mode_info->atom_context->bios + data_offset + 1039 le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset)); 1040 ATOM_PPLIB_CAC_Leakage_Record *entry; 1041 u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table); 1042 rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); 1043 if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 1044 r600_free_extended_power_table(rdev); 1045 return -ENOMEM; 1046 } 1047 entry = &cac_table->entries[0]; 1048 for (i = 0; i < cac_table->ucNumEntries; i++) { 1049 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 1050 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = 1051 le16_to_cpu(entry->usVddc1); 1052 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = 1053 le16_to_cpu(entry->usVddc2); 1054 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = 1055 le16_to_cpu(entry->usVddc3); 1056 } else { 1057 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = 1058 le16_to_cpu(entry->usVddc); 1059 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = 1060 le32_to_cpu(entry->ulLeakageValue); 1061 } 1062 entry = (ATOM_PPLIB_CAC_Leakage_Record *) 1063 ((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record)); 1064 } 1065 rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; 1066 } 1067 } 1068 1069 /* ext tables */ 1070 if (le16_to_cpu(power_info->pplib.usTableSize) >= 1071 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) { 1072 ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *) 1073 (mode_info->atom_context->bios + data_offset + 1074 le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset)); 1075 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) && 1076 ext_hdr->usVCETableOffset) { 1077 VCEClockInfoArray *array = (VCEClockInfoArray *) 1078 (mode_info->atom_context->bios + data_offset + 1079 le16_to_cpu(ext_hdr->usVCETableOffset) + 1); 1080 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits = 1081 (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *) 1082 (mode_info->atom_context->bios + data_offset + 1083 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + 1084 1 + array->ucNumEntries * sizeof(VCEClockInfo)); 1085 ATOM_PPLIB_VCE_State_Table *states = 1086 (ATOM_PPLIB_VCE_State_Table *) 1087 (mode_info->atom_context->bios + data_offset + 1088 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + 1089 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) + 1090 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record))); 1091 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *entry; 1092 ATOM_PPLIB_VCE_State_Record *state_entry; 1093 VCEClockInfo *vce_clk; 1094 u32 size = limits->numEntries * 1095 sizeof(struct radeon_vce_clock_voltage_dependency_entry); 1096 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = 1097 kzalloc(size, GFP_KERNEL); 1098 if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { 1099 r600_free_extended_power_table(rdev); 1100 return -ENOMEM; 1101 } 1102 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = 1103 limits->numEntries; 1104 entry = &limits->entries[0]; 1105 state_entry = &states->entries[0]; 1106 for (i = 0; i < limits->numEntries; i++) { 1107 vce_clk = (VCEClockInfo *) 1108 ((u8 *)&array->entries[0] + 1109 (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); 1110 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = 1111 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); 1112 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = 1113 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); 1114 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = 1115 le16_to_cpu(entry->usVoltage); 1116 entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *) 1117 ((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)); 1118 } 1119 for (i = 0; i < states->numEntries; i++) { 1120 if (i >= RADEON_MAX_VCE_LEVELS) 1121 break; 1122 vce_clk = (VCEClockInfo *) 1123 ((u8 *)&array->entries[0] + 1124 (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); 1125 rdev->pm.dpm.vce_states[i].evclk = 1126 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); 1127 rdev->pm.dpm.vce_states[i].ecclk = 1128 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); 1129 rdev->pm.dpm.vce_states[i].clk_idx = 1130 state_entry->ucClockInfoIndex & 0x3f; 1131 rdev->pm.dpm.vce_states[i].pstate = 1132 (state_entry->ucClockInfoIndex & 0xc0) >> 6; 1133 state_entry = (ATOM_PPLIB_VCE_State_Record *) 1134 ((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record)); 1135 } 1136 } 1137 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) && 1138 ext_hdr->usUVDTableOffset) { 1139 UVDClockInfoArray *array = (UVDClockInfoArray *) 1140 (mode_info->atom_context->bios + data_offset + 1141 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1); 1142 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits = 1143 (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *) 1144 (mode_info->atom_context->bios + data_offset + 1145 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 + 1146 1 + (array->ucNumEntries * sizeof (UVDClockInfo))); 1147 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *entry; 1148 u32 size = limits->numEntries * 1149 sizeof(struct radeon_uvd_clock_voltage_dependency_entry); 1150 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = 1151 kzalloc(size, GFP_KERNEL); 1152 if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { 1153 r600_free_extended_power_table(rdev); 1154 return -ENOMEM; 1155 } 1156 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = 1157 limits->numEntries; 1158 entry = &limits->entries[0]; 1159 for (i = 0; i < limits->numEntries; i++) { 1160 UVDClockInfo *uvd_clk = (UVDClockInfo *) 1161 ((u8 *)&array->entries[0] + 1162 (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo))); 1163 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = 1164 le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16); 1165 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = 1166 le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16); 1167 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = 1168 le16_to_cpu(entry->usVoltage); 1169 entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *) 1170 ((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record)); 1171 } 1172 } 1173 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) && 1174 ext_hdr->usSAMUTableOffset) { 1175 ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits = 1176 (ATOM_PPLIB_SAMClk_Voltage_Limit_Table *) 1177 (mode_info->atom_context->bios + data_offset + 1178 le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1); 1179 ATOM_PPLIB_SAMClk_Voltage_Limit_Record *entry; 1180 u32 size = limits->numEntries * 1181 sizeof(struct radeon_clock_voltage_dependency_entry); 1182 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = 1183 kzalloc(size, GFP_KERNEL); 1184 if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { 1185 r600_free_extended_power_table(rdev); 1186 return -ENOMEM; 1187 } 1188 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = 1189 limits->numEntries; 1190 entry = &limits->entries[0]; 1191 for (i = 0; i < limits->numEntries; i++) { 1192 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = 1193 le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16); 1194 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = 1195 le16_to_cpu(entry->usVoltage); 1196 entry = (ATOM_PPLIB_SAMClk_Voltage_Limit_Record *) 1197 ((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record)); 1198 } 1199 } 1200 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && 1201 ext_hdr->usPPMTableOffset) { 1202 ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *) 1203 (mode_info->atom_context->bios + data_offset + 1204 le16_to_cpu(ext_hdr->usPPMTableOffset)); 1205 rdev->pm.dpm.dyn_state.ppm_table = 1206 kzalloc(sizeof(struct radeon_ppm_table), GFP_KERNEL); 1207 if (!rdev->pm.dpm.dyn_state.ppm_table) { 1208 r600_free_extended_power_table(rdev); 1209 return -ENOMEM; 1210 } 1211 rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; 1212 rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number = 1213 le16_to_cpu(ppm->usCpuCoreNumber); 1214 rdev->pm.dpm.dyn_state.ppm_table->platform_tdp = 1215 le32_to_cpu(ppm->ulPlatformTDP); 1216 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = 1217 le32_to_cpu(ppm->ulSmallACPlatformTDP); 1218 rdev->pm.dpm.dyn_state.ppm_table->platform_tdc = 1219 le32_to_cpu(ppm->ulPlatformTDC); 1220 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = 1221 le32_to_cpu(ppm->ulSmallACPlatformTDC); 1222 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp = 1223 le32_to_cpu(ppm->ulApuTDP); 1224 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = 1225 le32_to_cpu(ppm->ulDGpuTDP); 1226 rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = 1227 le32_to_cpu(ppm->ulDGpuUlvPower); 1228 rdev->pm.dpm.dyn_state.ppm_table->tj_max = 1229 le32_to_cpu(ppm->ulTjmax); 1230 } 1231 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) && 1232 ext_hdr->usACPTableOffset) { 1233 ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits = 1234 (ATOM_PPLIB_ACPClk_Voltage_Limit_Table *) 1235 (mode_info->atom_context->bios + data_offset + 1236 le16_to_cpu(ext_hdr->usACPTableOffset) + 1); 1237 ATOM_PPLIB_ACPClk_Voltage_Limit_Record *entry; 1238 u32 size = limits->numEntries * 1239 sizeof(struct radeon_clock_voltage_dependency_entry); 1240 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = 1241 kzalloc(size, GFP_KERNEL); 1242 if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { 1243 r600_free_extended_power_table(rdev); 1244 return -ENOMEM; 1245 } 1246 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = 1247 limits->numEntries; 1248 entry = &limits->entries[0]; 1249 for (i = 0; i < limits->numEntries; i++) { 1250 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = 1251 le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16); 1252 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = 1253 le16_to_cpu(entry->usVoltage); 1254 entry = (ATOM_PPLIB_ACPClk_Voltage_Limit_Record *) 1255 ((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record)); 1256 } 1257 } 1258 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) && 1259 ext_hdr->usPowerTuneTableOffset) { 1260 u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset + 1261 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); 1262 ATOM_PowerTune_Table *pt; 1263 rdev->pm.dpm.dyn_state.cac_tdp_table = 1264 kzalloc(sizeof(struct radeon_cac_tdp_table), GFP_KERNEL); 1265 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) { 1266 r600_free_extended_power_table(rdev); 1267 return -ENOMEM; 1268 } 1269 if (rev > 0) { 1270 ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *) 1271 (mode_info->atom_context->bios + data_offset + 1272 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); 1273 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 1274 le16_to_cpu(ppt->usMaximumPowerDeliveryLimit); 1275 pt = &ppt->power_tune_table; 1276 } else { 1277 ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *) 1278 (mode_info->atom_context->bios + data_offset + 1279 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); 1280 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; 1281 pt = &ppt->power_tune_table; 1282 } 1283 rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); 1284 rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = 1285 le16_to_cpu(pt->usConfigurableTDP); 1286 rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); 1287 rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = 1288 le16_to_cpu(pt->usBatteryPowerLimit); 1289 rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = 1290 le16_to_cpu(pt->usSmallPowerLimit); 1291 rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = 1292 le16_to_cpu(pt->usLowCACLeakage); 1293 rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = 1294 le16_to_cpu(pt->usHighCACLeakage); 1295 } 1296 } 1297 1298 return 0; 1299 } 1300 1301 void r600_free_extended_power_table(struct radeon_device *rdev) 1302 { 1303 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; 1304 1305 kfree(dyn_state->vddc_dependency_on_sclk.entries); 1306 kfree(dyn_state->vddci_dependency_on_mclk.entries); 1307 kfree(dyn_state->vddc_dependency_on_mclk.entries); 1308 kfree(dyn_state->mvdd_dependency_on_mclk.entries); 1309 kfree(dyn_state->cac_leakage_table.entries); 1310 kfree(dyn_state->phase_shedding_limits_table.entries); 1311 kfree(dyn_state->ppm_table); 1312 kfree(dyn_state->cac_tdp_table); 1313 kfree(dyn_state->vce_clock_voltage_dependency_table.entries); 1314 kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); 1315 kfree(dyn_state->samu_clock_voltage_dependency_table.entries); 1316 kfree(dyn_state->acp_clock_voltage_dependency_table.entries); 1317 } 1318 1319 enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, 1320 u32 sys_mask, 1321 enum radeon_pcie_gen asic_gen, 1322 enum radeon_pcie_gen default_gen) 1323 { 1324 switch (asic_gen) { 1325 case RADEON_PCIE_GEN1: 1326 return RADEON_PCIE_GEN1; 1327 case RADEON_PCIE_GEN2: 1328 return RADEON_PCIE_GEN2; 1329 case RADEON_PCIE_GEN3: 1330 return RADEON_PCIE_GEN3; 1331 default: 1332 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3)) 1333 return RADEON_PCIE_GEN3; 1334 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2)) 1335 return RADEON_PCIE_GEN2; 1336 else 1337 return RADEON_PCIE_GEN1; 1338 } 1339 return RADEON_PCIE_GEN1; 1340 } 1341 1342 u16 r600_get_pcie_lane_support(struct radeon_device *rdev, 1343 u16 asic_lanes, 1344 u16 default_lanes) 1345 { 1346 switch (asic_lanes) { 1347 case 0: 1348 default: 1349 return default_lanes; 1350 case 1: 1351 return 1; 1352 case 2: 1353 return 2; 1354 case 4: 1355 return 4; 1356 case 8: 1357 return 8; 1358 case 12: 1359 return 12; 1360 case 16: 1361 return 16; 1362 } 1363 } 1364 1365 u8 r600_encode_pci_lane_width(u32 lanes) 1366 { 1367 u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 }; 1368 1369 if (lanes > 16) 1370 return 0; 1371 1372 return encoded_lanes[lanes]; 1373 } 1374