1 /* $NetBSD: radeon_r300.c,v 1.2 2019/02/08 04:11:53 mrg Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r300.c,v 1.2 2019/02/08 04:11:53 mrg Exp $"); 32 33 #include <linux/seq_file.h> 34 #include <linux/slab.h> 35 #include <drm/drmP.h> 36 #include <drm/drm.h> 37 #include <drm/drm_crtc_helper.h> 38 #include "radeon_reg.h" 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include <drm/radeon_drm.h> 42 #include "r100_track.h" 43 #include "r300d.h" 44 #include "rv350d.h" 45 #include "r300_reg_safe.h" 46 47 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 48 * 49 * GPU Errata: 50 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 51 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 52 * However, scheduling such write to the ring seems harmless, i suspect 53 * the CP read collide with the flush somehow, or maybe the MC, hard to 54 * tell. (Jerome Glisse) 55 */ 56 57 /* 58 * Indirect registers accessor 59 */ 60 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 61 { 62 unsigned long flags; 63 uint32_t r; 64 65 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 66 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 67 r = RREG32(RADEON_PCIE_DATA); 68 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 69 return r; 70 } 71 72 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 73 { 74 unsigned long flags; 75 76 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 77 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 78 WREG32(RADEON_PCIE_DATA, (v)); 79 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 80 } 81 82 /* 83 * rv370,rv380 PCIE GART 84 */ 85 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 86 87 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 88 { 89 uint32_t tmp; 90 int i; 91 92 /* Workaround HW bug do flush 2 times */ 93 for (i = 0; i < 2; i++) { 94 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 95 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 96 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 97 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 98 } 99 mb(); 100 } 101 102 #define R300_PTE_UNSNOOPED (1 << 0) 103 #define R300_PTE_WRITEABLE (1 << 2) 104 #define R300_PTE_READABLE (1 << 3) 105 106 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) 107 { 108 addr = (lower_32_bits(addr) >> 8) | 109 ((upper_32_bits(addr) & 0xff) << 24); 110 if (flags & RADEON_GART_PAGE_READ) 111 addr |= R300_PTE_READABLE; 112 if (flags & RADEON_GART_PAGE_WRITE) 113 addr |= R300_PTE_WRITEABLE; 114 if (!(flags & RADEON_GART_PAGE_SNOOP)) 115 addr |= R300_PTE_UNSNOOPED; 116 return addr; 117 } 118 119 #ifdef __NetBSD__ 120 /* 121 * XXX Can't use bus_space here because this is all mapped through the 122 * radeon_bo abstraction. Can't assume we're x86 because this is 123 * AMD/ATI Radeon, not Intel. 124 */ 125 126 # define __iomem volatile 127 # define writel fake_writel 128 129 static inline void 130 fake_writel(uint32_t v, void __iomem *ptr) 131 { 132 133 membar_producer(); 134 *(uint32_t __iomem *)ptr = v; 135 } 136 #endif 137 138 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 139 uint64_t entry) 140 { 141 void __iomem *ptr = rdev->gart.ptr; 142 143 /* on x86 we want this to be CPU endian, on powerpc 144 * on powerpc without HW swappers, it'll get swapped on way 145 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 146 writel(entry, (uint8_t __iomem *)ptr + (i * 4)); 147 } 148 149 #ifdef __NetBSD__ 150 # undef __iomem 151 # undef writel 152 #endif 153 154 int rv370_pcie_gart_init(struct radeon_device *rdev) 155 { 156 int r; 157 158 if (rdev->gart.robj) { 159 WARN(1, "RV370 PCIE GART already initialized\n"); 160 return 0; 161 } 162 /* Initialize common gart structure */ 163 r = radeon_gart_init(rdev); 164 if (r) 165 return r; 166 r = rv370_debugfs_pcie_gart_info_init(rdev); 167 if (r) 168 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 169 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 170 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 171 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 172 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 173 return radeon_gart_table_vram_alloc(rdev); 174 } 175 176 int rv370_pcie_gart_enable(struct radeon_device *rdev) 177 { 178 uint32_t table_addr; 179 uint32_t tmp; 180 int r; 181 182 if (rdev->gart.robj == NULL) { 183 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 184 return -EINVAL; 185 } 186 r = radeon_gart_table_vram_pin(rdev); 187 if (r) 188 return r; 189 /* discard memory request outside of configured range */ 190 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 191 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 192 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 193 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 194 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 195 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 196 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 197 table_addr = rdev->gart.table_addr; 198 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 199 /* FIXME: setup default page */ 200 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 201 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 202 /* Clear error */ 203 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 204 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 205 tmp |= RADEON_PCIE_TX_GART_EN; 206 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 207 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 208 rv370_pcie_gart_tlb_flush(rdev); 209 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 210 (unsigned)(rdev->mc.gtt_size >> 20), 211 (unsigned long long)table_addr); 212 rdev->gart.ready = true; 213 return 0; 214 } 215 216 void rv370_pcie_gart_disable(struct radeon_device *rdev) 217 { 218 u32 tmp; 219 220 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 221 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 222 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 223 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 224 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 225 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 226 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 227 radeon_gart_table_vram_unpin(rdev); 228 } 229 230 void rv370_pcie_gart_fini(struct radeon_device *rdev) 231 { 232 radeon_gart_fini(rdev); 233 rv370_pcie_gart_disable(rdev); 234 radeon_gart_table_vram_free(rdev); 235 } 236 237 void r300_fence_ring_emit(struct radeon_device *rdev, 238 struct radeon_fence *fence) 239 { 240 struct radeon_ring *ring = &rdev->ring[fence->ring]; 241 242 /* Who ever call radeon_fence_emit should call ring_lock and ask 243 * for enough space (today caller are ib schedule and buffer move) */ 244 /* Write SC register so SC & US assert idle */ 245 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 246 radeon_ring_write(ring, 0); 247 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 248 radeon_ring_write(ring, 0); 249 /* Flush 3D cache */ 250 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 251 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 252 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 253 radeon_ring_write(ring, R300_ZC_FLUSH); 254 /* Wait until IDLE & CLEAN */ 255 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 256 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 257 RADEON_WAIT_2D_IDLECLEAN | 258 RADEON_WAIT_DMA_GUI_IDLE)); 259 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 260 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 261 RADEON_HDP_READ_BUFFER_INVALIDATE); 262 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 263 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 264 /* Emit fence sequence & fire IRQ */ 265 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 266 radeon_ring_write(ring, fence->seq); 267 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 268 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 269 } 270 271 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 272 { 273 unsigned gb_tile_config; 274 int r; 275 276 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 277 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 278 switch(rdev->num_gb_pipes) { 279 case 2: 280 gb_tile_config |= R300_PIPE_COUNT_R300; 281 break; 282 case 3: 283 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 284 break; 285 case 4: 286 gb_tile_config |= R300_PIPE_COUNT_R420; 287 break; 288 case 1: 289 default: 290 gb_tile_config |= R300_PIPE_COUNT_RV350; 291 break; 292 } 293 294 r = radeon_ring_lock(rdev, ring, 64); 295 if (r) { 296 return; 297 } 298 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 299 radeon_ring_write(ring, 300 RADEON_ISYNC_ANY2D_IDLE3D | 301 RADEON_ISYNC_ANY3D_IDLE2D | 302 RADEON_ISYNC_WAIT_IDLEGUI | 303 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 304 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 305 radeon_ring_write(ring, gb_tile_config); 306 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 307 radeon_ring_write(ring, 308 RADEON_WAIT_2D_IDLECLEAN | 309 RADEON_WAIT_3D_IDLECLEAN); 310 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 311 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 312 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 313 radeon_ring_write(ring, 0); 314 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 315 radeon_ring_write(ring, 0); 316 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 317 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 318 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 319 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 320 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 321 radeon_ring_write(ring, 322 RADEON_WAIT_2D_IDLECLEAN | 323 RADEON_WAIT_3D_IDLECLEAN); 324 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 325 radeon_ring_write(ring, 0); 326 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 327 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 328 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 329 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 330 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 331 radeon_ring_write(ring, 332 ((6 << R300_MS_X0_SHIFT) | 333 (6 << R300_MS_Y0_SHIFT) | 334 (6 << R300_MS_X1_SHIFT) | 335 (6 << R300_MS_Y1_SHIFT) | 336 (6 << R300_MS_X2_SHIFT) | 337 (6 << R300_MS_Y2_SHIFT) | 338 (6 << R300_MSBD0_Y_SHIFT) | 339 (6 << R300_MSBD0_X_SHIFT))); 340 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 341 radeon_ring_write(ring, 342 ((6 << R300_MS_X3_SHIFT) | 343 (6 << R300_MS_Y3_SHIFT) | 344 (6 << R300_MS_X4_SHIFT) | 345 (6 << R300_MS_Y4_SHIFT) | 346 (6 << R300_MS_X5_SHIFT) | 347 (6 << R300_MS_Y5_SHIFT) | 348 (6 << R300_MSBD1_SHIFT))); 349 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 350 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 351 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 352 radeon_ring_write(ring, 353 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 354 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 355 radeon_ring_write(ring, 356 R300_GEOMETRY_ROUND_NEAREST | 357 R300_COLOR_ROUND_NEAREST); 358 radeon_ring_unlock_commit(rdev, ring, false); 359 } 360 361 static void r300_errata(struct radeon_device *rdev) 362 { 363 rdev->pll_errata = 0; 364 365 if (rdev->family == CHIP_R300 && 366 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 367 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 368 } 369 } 370 371 int r300_mc_wait_for_idle(struct radeon_device *rdev) 372 { 373 unsigned i; 374 uint32_t tmp; 375 376 for (i = 0; i < rdev->usec_timeout; i++) { 377 /* read MC_STATUS */ 378 tmp = RREG32(RADEON_MC_STATUS); 379 if (tmp & R300_MC_IDLE) { 380 return 0; 381 } 382 DRM_UDELAY(1); 383 } 384 return -1; 385 } 386 387 static void r300_gpu_init(struct radeon_device *rdev) 388 { 389 uint32_t gb_tile_config, tmp; 390 391 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 392 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 393 /* r300,r350 */ 394 rdev->num_gb_pipes = 2; 395 } else { 396 /* rv350,rv370,rv380,r300 AD, r350 AH */ 397 rdev->num_gb_pipes = 1; 398 } 399 rdev->num_z_pipes = 1; 400 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 401 switch (rdev->num_gb_pipes) { 402 case 2: 403 gb_tile_config |= R300_PIPE_COUNT_R300; 404 break; 405 case 3: 406 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 407 break; 408 case 4: 409 gb_tile_config |= R300_PIPE_COUNT_R420; 410 break; 411 default: 412 case 1: 413 gb_tile_config |= R300_PIPE_COUNT_RV350; 414 break; 415 } 416 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 417 418 if (r100_gui_wait_for_idle(rdev)) { 419 printk(KERN_WARNING "Failed to wait GUI idle while " 420 "programming pipes. Bad things might happen.\n"); 421 } 422 423 tmp = RREG32(R300_DST_PIPE_CONFIG); 424 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 425 426 WREG32(R300_RB2D_DSTCACHE_MODE, 427 R300_DC_AUTOFLUSH_ENABLE | 428 R300_DC_DC_DISABLE_IGNORE_PE); 429 430 if (r100_gui_wait_for_idle(rdev)) { 431 printk(KERN_WARNING "Failed to wait GUI idle while " 432 "programming pipes. Bad things might happen.\n"); 433 } 434 if (r300_mc_wait_for_idle(rdev)) { 435 printk(KERN_WARNING "Failed to wait MC idle while " 436 "programming pipes. Bad things might happen.\n"); 437 } 438 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 439 rdev->num_gb_pipes, rdev->num_z_pipes); 440 } 441 442 int r300_asic_reset(struct radeon_device *rdev) 443 { 444 struct r100_mc_save save; 445 u32 status, tmp; 446 int ret = 0; 447 448 status = RREG32(R_000E40_RBBM_STATUS); 449 if (!G_000E40_GUI_ACTIVE(status)) { 450 return 0; 451 } 452 r100_mc_stop(rdev, &save); 453 status = RREG32(R_000E40_RBBM_STATUS); 454 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 455 /* stop CP */ 456 WREG32(RADEON_CP_CSQ_CNTL, 0); 457 tmp = RREG32(RADEON_CP_RB_CNTL); 458 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 459 WREG32(RADEON_CP_RB_RPTR_WR, 0); 460 WREG32(RADEON_CP_RB_WPTR, 0); 461 WREG32(RADEON_CP_RB_CNTL, tmp); 462 /* save PCI state */ 463 pci_save_state(rdev->pdev); 464 /* disable bus mastering */ 465 r100_bm_disable(rdev); 466 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 467 S_0000F0_SOFT_RESET_GA(1)); 468 RREG32(R_0000F0_RBBM_SOFT_RESET); 469 mdelay(500); 470 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 471 mdelay(1); 472 status = RREG32(R_000E40_RBBM_STATUS); 473 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 474 /* resetting the CP seems to be problematic sometimes it end up 475 * hard locking the computer, but it's necessary for successful 476 * reset more test & playing is needed on R3XX/R4XX to find a 477 * reliable (if any solution) 478 */ 479 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 480 RREG32(R_0000F0_RBBM_SOFT_RESET); 481 mdelay(500); 482 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 483 mdelay(1); 484 status = RREG32(R_000E40_RBBM_STATUS); 485 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 486 /* restore PCI & busmastering */ 487 pci_restore_state(rdev->pdev); 488 r100_enable_bm(rdev); 489 /* Check if GPU is idle */ 490 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 491 dev_err(rdev->dev, "failed to reset GPU\n"); 492 ret = -1; 493 } else 494 dev_info(rdev->dev, "GPU reset succeed\n"); 495 r100_mc_resume(rdev, &save); 496 return ret; 497 } 498 499 /* 500 * r300,r350,rv350,rv380 VRAM info 501 */ 502 void r300_mc_init(struct radeon_device *rdev) 503 { 504 u64 base; 505 u32 tmp; 506 507 /* DDR for all card after R300 & IGP */ 508 rdev->mc.vram_is_ddr = true; 509 tmp = RREG32(RADEON_MEM_CNTL); 510 tmp &= R300_MEM_NUM_CHANNELS_MASK; 511 switch (tmp) { 512 case 0: rdev->mc.vram_width = 64; break; 513 case 1: rdev->mc.vram_width = 128; break; 514 case 2: rdev->mc.vram_width = 256; break; 515 default: rdev->mc.vram_width = 128; break; 516 } 517 r100_vram_init_sizes(rdev); 518 base = rdev->mc.aper_base; 519 if (rdev->flags & RADEON_IS_IGP) 520 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 521 radeon_vram_location(rdev, &rdev->mc, base); 522 rdev->mc.gtt_base_align = 0; 523 if (!(rdev->flags & RADEON_IS_AGP)) 524 radeon_gtt_location(rdev, &rdev->mc); 525 radeon_update_bandwidth_info(rdev); 526 } 527 528 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 529 { 530 uint32_t link_width_cntl, mask; 531 532 if (rdev->flags & RADEON_IS_IGP) 533 return; 534 535 if (!(rdev->flags & RADEON_IS_PCIE)) 536 return; 537 538 /* FIXME wait for idle */ 539 540 switch (lanes) { 541 case 0: 542 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 543 break; 544 case 1: 545 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 546 break; 547 case 2: 548 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 549 break; 550 case 4: 551 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 552 break; 553 case 8: 554 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 555 break; 556 case 12: 557 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 558 break; 559 case 16: 560 default: 561 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 562 break; 563 } 564 565 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 566 567 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 568 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 569 return; 570 571 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 572 RADEON_PCIE_LC_RECONFIG_NOW | 573 RADEON_PCIE_LC_RECONFIG_LATER | 574 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 575 link_width_cntl |= mask; 576 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 577 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 578 RADEON_PCIE_LC_RECONFIG_NOW)); 579 580 /* wait for lane set to complete */ 581 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 582 while (link_width_cntl == 0xffffffff) 583 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 584 585 } 586 587 int rv370_get_pcie_lanes(struct radeon_device *rdev) 588 { 589 u32 link_width_cntl; 590 591 if (rdev->flags & RADEON_IS_IGP) 592 return 0; 593 594 if (!(rdev->flags & RADEON_IS_PCIE)) 595 return 0; 596 597 /* FIXME wait for idle */ 598 599 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 600 601 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 602 case RADEON_PCIE_LC_LINK_WIDTH_X0: 603 return 0; 604 case RADEON_PCIE_LC_LINK_WIDTH_X1: 605 return 1; 606 case RADEON_PCIE_LC_LINK_WIDTH_X2: 607 return 2; 608 case RADEON_PCIE_LC_LINK_WIDTH_X4: 609 return 4; 610 case RADEON_PCIE_LC_LINK_WIDTH_X8: 611 return 8; 612 case RADEON_PCIE_LC_LINK_WIDTH_X16: 613 default: 614 return 16; 615 } 616 } 617 618 #if defined(CONFIG_DEBUG_FS) 619 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 620 { 621 struct drm_info_node *node = (struct drm_info_node *) m->private; 622 struct drm_device *dev = node->minor->dev; 623 struct radeon_device *rdev = dev->dev_private; 624 uint32_t tmp; 625 626 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 627 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 628 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 629 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 630 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 631 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 632 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 633 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 634 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 635 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 636 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 637 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 638 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 639 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 640 return 0; 641 } 642 643 static struct drm_info_list rv370_pcie_gart_info_list[] = { 644 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 645 }; 646 #endif 647 648 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 649 { 650 #if defined(CONFIG_DEBUG_FS) 651 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 652 #else 653 return 0; 654 #endif 655 } 656 657 static int r300_packet0_check(struct radeon_cs_parser *p, 658 struct radeon_cs_packet *pkt, 659 unsigned idx, unsigned reg) 660 { 661 struct radeon_bo_list *reloc; 662 struct r100_cs_track *track; 663 volatile uint32_t *ib; 664 uint32_t tmp, tile_flags = 0; 665 unsigned i; 666 int r; 667 u32 idx_value; 668 669 ib = p->ib.ptr; 670 track = (struct r100_cs_track *)p->track; 671 idx_value = radeon_get_ib_value(p, idx); 672 673 switch(reg) { 674 case AVIVO_D1MODE_VLINE_START_END: 675 case RADEON_CRTC_GUI_TRIG_VLINE: 676 r = r100_cs_packet_parse_vline(p); 677 if (r) { 678 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 679 idx, reg); 680 radeon_cs_dump_packet(p, pkt); 681 return r; 682 } 683 break; 684 case RADEON_DST_PITCH_OFFSET: 685 case RADEON_SRC_PITCH_OFFSET: 686 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 687 if (r) 688 return r; 689 break; 690 case R300_RB3D_COLOROFFSET0: 691 case R300_RB3D_COLOROFFSET1: 692 case R300_RB3D_COLOROFFSET2: 693 case R300_RB3D_COLOROFFSET3: 694 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 695 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 696 if (r) { 697 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 698 idx, reg); 699 radeon_cs_dump_packet(p, pkt); 700 return r; 701 } 702 track->cb[i].robj = reloc->robj; 703 track->cb[i].offset = idx_value; 704 track->cb_dirty = true; 705 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 706 break; 707 case R300_ZB_DEPTHOFFSET: 708 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 709 if (r) { 710 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 711 idx, reg); 712 radeon_cs_dump_packet(p, pkt); 713 return r; 714 } 715 track->zb.robj = reloc->robj; 716 track->zb.offset = idx_value; 717 track->zb_dirty = true; 718 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 719 break; 720 case R300_TX_OFFSET_0: 721 case R300_TX_OFFSET_0+4: 722 case R300_TX_OFFSET_0+8: 723 case R300_TX_OFFSET_0+12: 724 case R300_TX_OFFSET_0+16: 725 case R300_TX_OFFSET_0+20: 726 case R300_TX_OFFSET_0+24: 727 case R300_TX_OFFSET_0+28: 728 case R300_TX_OFFSET_0+32: 729 case R300_TX_OFFSET_0+36: 730 case R300_TX_OFFSET_0+40: 731 case R300_TX_OFFSET_0+44: 732 case R300_TX_OFFSET_0+48: 733 case R300_TX_OFFSET_0+52: 734 case R300_TX_OFFSET_0+56: 735 case R300_TX_OFFSET_0+60: 736 i = (reg - R300_TX_OFFSET_0) >> 2; 737 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 738 if (r) { 739 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 740 idx, reg); 741 radeon_cs_dump_packet(p, pkt); 742 return r; 743 } 744 745 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 746 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 747 ((idx_value & ~31) + (u32)reloc->gpu_offset); 748 } else { 749 if (reloc->tiling_flags & RADEON_TILING_MACRO) 750 tile_flags |= R300_TXO_MACRO_TILE; 751 if (reloc->tiling_flags & RADEON_TILING_MICRO) 752 tile_flags |= R300_TXO_MICRO_TILE; 753 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 754 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 755 756 tmp = idx_value + ((u32)reloc->gpu_offset); 757 tmp |= tile_flags; 758 ib[idx] = tmp; 759 } 760 track->textures[i].robj = reloc->robj; 761 track->tex_dirty = true; 762 break; 763 /* Tracked registers */ 764 case 0x2084: 765 /* VAP_VF_CNTL */ 766 track->vap_vf_cntl = idx_value; 767 break; 768 case 0x20B4: 769 /* VAP_VTX_SIZE */ 770 track->vtx_size = idx_value & 0x7F; 771 break; 772 case 0x2134: 773 /* VAP_VF_MAX_VTX_INDX */ 774 track->max_indx = idx_value & 0x00FFFFFFUL; 775 break; 776 case 0x2088: 777 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 778 if (p->rdev->family < CHIP_RV515) 779 goto fail; 780 track->vap_alt_nverts = idx_value & 0xFFFFFF; 781 break; 782 case 0x43E4: 783 /* SC_SCISSOR1 */ 784 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 785 if (p->rdev->family < CHIP_RV515) { 786 track->maxy -= 1440; 787 } 788 track->cb_dirty = true; 789 track->zb_dirty = true; 790 break; 791 case 0x4E00: 792 /* RB3D_CCTL */ 793 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 794 p->rdev->cmask_filp != p->filp) { 795 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 796 return -EINVAL; 797 } 798 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 799 track->cb_dirty = true; 800 break; 801 case 0x4E38: 802 case 0x4E3C: 803 case 0x4E40: 804 case 0x4E44: 805 /* RB3D_COLORPITCH0 */ 806 /* RB3D_COLORPITCH1 */ 807 /* RB3D_COLORPITCH2 */ 808 /* RB3D_COLORPITCH3 */ 809 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 810 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 811 if (r) { 812 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 813 idx, reg); 814 radeon_cs_dump_packet(p, pkt); 815 return r; 816 } 817 818 if (reloc->tiling_flags & RADEON_TILING_MACRO) 819 tile_flags |= R300_COLOR_TILE_ENABLE; 820 if (reloc->tiling_flags & RADEON_TILING_MICRO) 821 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 822 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 823 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 824 825 tmp = idx_value & ~(0x7 << 16); 826 tmp |= tile_flags; 827 ib[idx] = tmp; 828 } 829 i = (reg - 0x4E38) >> 2; 830 track->cb[i].pitch = idx_value & 0x3FFE; 831 switch (((idx_value >> 21) & 0xF)) { 832 case 9: 833 case 11: 834 case 12: 835 track->cb[i].cpp = 1; 836 break; 837 case 3: 838 case 4: 839 case 13: 840 case 15: 841 track->cb[i].cpp = 2; 842 break; 843 case 5: 844 if (p->rdev->family < CHIP_RV515) { 845 DRM_ERROR("Invalid color buffer format (%d)!\n", 846 ((idx_value >> 21) & 0xF)); 847 return -EINVAL; 848 } 849 /* FALLTHROUGH */ 850 case 6: 851 track->cb[i].cpp = 4; 852 break; 853 case 10: 854 track->cb[i].cpp = 8; 855 break; 856 case 7: 857 track->cb[i].cpp = 16; 858 break; 859 default: 860 DRM_ERROR("Invalid color buffer format (%d) !\n", 861 ((idx_value >> 21) & 0xF)); 862 return -EINVAL; 863 } 864 track->cb_dirty = true; 865 break; 866 case 0x4F00: 867 /* ZB_CNTL */ 868 if (idx_value & 2) { 869 track->z_enabled = true; 870 } else { 871 track->z_enabled = false; 872 } 873 track->zb_dirty = true; 874 break; 875 case 0x4F10: 876 /* ZB_FORMAT */ 877 switch ((idx_value & 0xF)) { 878 case 0: 879 case 1: 880 track->zb.cpp = 2; 881 break; 882 case 2: 883 track->zb.cpp = 4; 884 break; 885 default: 886 DRM_ERROR("Invalid z buffer format (%d) !\n", 887 (idx_value & 0xF)); 888 return -EINVAL; 889 } 890 track->zb_dirty = true; 891 break; 892 case 0x4F24: 893 /* ZB_DEPTHPITCH */ 894 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 895 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 896 if (r) { 897 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 898 idx, reg); 899 radeon_cs_dump_packet(p, pkt); 900 return r; 901 } 902 903 if (reloc->tiling_flags & RADEON_TILING_MACRO) 904 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 905 if (reloc->tiling_flags & RADEON_TILING_MICRO) 906 tile_flags |= R300_DEPTHMICROTILE_TILED; 907 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 908 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 909 910 tmp = idx_value & ~(0x7 << 16); 911 tmp |= tile_flags; 912 ib[idx] = tmp; 913 } 914 track->zb.pitch = idx_value & 0x3FFC; 915 track->zb_dirty = true; 916 break; 917 case 0x4104: 918 /* TX_ENABLE */ 919 for (i = 0; i < 16; i++) { 920 bool enabled; 921 922 enabled = !!(idx_value & (1 << i)); 923 track->textures[i].enabled = enabled; 924 } 925 track->tex_dirty = true; 926 break; 927 case 0x44C0: 928 case 0x44C4: 929 case 0x44C8: 930 case 0x44CC: 931 case 0x44D0: 932 case 0x44D4: 933 case 0x44D8: 934 case 0x44DC: 935 case 0x44E0: 936 case 0x44E4: 937 case 0x44E8: 938 case 0x44EC: 939 case 0x44F0: 940 case 0x44F4: 941 case 0x44F8: 942 case 0x44FC: 943 /* TX_FORMAT1_[0-15] */ 944 i = (reg - 0x44C0) >> 2; 945 tmp = (idx_value >> 25) & 0x3; 946 track->textures[i].tex_coord_type = tmp; 947 switch ((idx_value & 0x1F)) { 948 case R300_TX_FORMAT_X8: 949 case R300_TX_FORMAT_Y4X4: 950 case R300_TX_FORMAT_Z3Y3X2: 951 track->textures[i].cpp = 1; 952 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 953 break; 954 case R300_TX_FORMAT_X16: 955 case R300_TX_FORMAT_FL_I16: 956 case R300_TX_FORMAT_Y8X8: 957 case R300_TX_FORMAT_Z5Y6X5: 958 case R300_TX_FORMAT_Z6Y5X5: 959 case R300_TX_FORMAT_W4Z4Y4X4: 960 case R300_TX_FORMAT_W1Z5Y5X5: 961 case R300_TX_FORMAT_D3DMFT_CxV8U8: 962 case R300_TX_FORMAT_B8G8_B8G8: 963 case R300_TX_FORMAT_G8R8_G8B8: 964 track->textures[i].cpp = 2; 965 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 966 break; 967 case R300_TX_FORMAT_Y16X16: 968 case R300_TX_FORMAT_FL_I16A16: 969 case R300_TX_FORMAT_Z11Y11X10: 970 case R300_TX_FORMAT_Z10Y11X11: 971 case R300_TX_FORMAT_W8Z8Y8X8: 972 case R300_TX_FORMAT_W2Z10Y10X10: 973 case 0x17: 974 case R300_TX_FORMAT_FL_I32: 975 case 0x1e: 976 track->textures[i].cpp = 4; 977 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 978 break; 979 case R300_TX_FORMAT_W16Z16Y16X16: 980 case R300_TX_FORMAT_FL_R16G16B16A16: 981 case R300_TX_FORMAT_FL_I32A32: 982 track->textures[i].cpp = 8; 983 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 984 break; 985 case R300_TX_FORMAT_FL_R32G32B32A32: 986 track->textures[i].cpp = 16; 987 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 988 break; 989 case R300_TX_FORMAT_DXT1: 990 track->textures[i].cpp = 1; 991 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 992 break; 993 case R300_TX_FORMAT_ATI2N: 994 if (p->rdev->family < CHIP_R420) { 995 DRM_ERROR("Invalid texture format %u\n", 996 (idx_value & 0x1F)); 997 return -EINVAL; 998 } 999 /* The same rules apply as for DXT3/5. */ 1000 /* FALLTHROUGH */ 1001 case R300_TX_FORMAT_DXT3: 1002 case R300_TX_FORMAT_DXT5: 1003 track->textures[i].cpp = 1; 1004 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1005 break; 1006 default: 1007 DRM_ERROR("Invalid texture format %u\n", 1008 (idx_value & 0x1F)); 1009 return -EINVAL; 1010 } 1011 track->tex_dirty = true; 1012 break; 1013 case 0x4400: 1014 case 0x4404: 1015 case 0x4408: 1016 case 0x440C: 1017 case 0x4410: 1018 case 0x4414: 1019 case 0x4418: 1020 case 0x441C: 1021 case 0x4420: 1022 case 0x4424: 1023 case 0x4428: 1024 case 0x442C: 1025 case 0x4430: 1026 case 0x4434: 1027 case 0x4438: 1028 case 0x443C: 1029 /* TX_FILTER0_[0-15] */ 1030 i = (reg - 0x4400) >> 2; 1031 tmp = idx_value & 0x7; 1032 if (tmp == 2 || tmp == 4 || tmp == 6) { 1033 track->textures[i].roundup_w = false; 1034 } 1035 tmp = (idx_value >> 3) & 0x7; 1036 if (tmp == 2 || tmp == 4 || tmp == 6) { 1037 track->textures[i].roundup_h = false; 1038 } 1039 track->tex_dirty = true; 1040 break; 1041 case 0x4500: 1042 case 0x4504: 1043 case 0x4508: 1044 case 0x450C: 1045 case 0x4510: 1046 case 0x4514: 1047 case 0x4518: 1048 case 0x451C: 1049 case 0x4520: 1050 case 0x4524: 1051 case 0x4528: 1052 case 0x452C: 1053 case 0x4530: 1054 case 0x4534: 1055 case 0x4538: 1056 case 0x453C: 1057 /* TX_FORMAT2_[0-15] */ 1058 i = (reg - 0x4500) >> 2; 1059 tmp = idx_value & 0x3FFF; 1060 track->textures[i].pitch = tmp + 1; 1061 if (p->rdev->family >= CHIP_RV515) { 1062 tmp = ((idx_value >> 15) & 1) << 11; 1063 track->textures[i].width_11 = tmp; 1064 tmp = ((idx_value >> 16) & 1) << 11; 1065 track->textures[i].height_11 = tmp; 1066 1067 /* ATI1N */ 1068 if (idx_value & (1 << 14)) { 1069 /* The same rules apply as for DXT1. */ 1070 track->textures[i].compress_format = 1071 R100_TRACK_COMP_DXT1; 1072 } 1073 } else if (idx_value & (1 << 14)) { 1074 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1075 return -EINVAL; 1076 } 1077 track->tex_dirty = true; 1078 break; 1079 case 0x4480: 1080 case 0x4484: 1081 case 0x4488: 1082 case 0x448C: 1083 case 0x4490: 1084 case 0x4494: 1085 case 0x4498: 1086 case 0x449C: 1087 case 0x44A0: 1088 case 0x44A4: 1089 case 0x44A8: 1090 case 0x44AC: 1091 case 0x44B0: 1092 case 0x44B4: 1093 case 0x44B8: 1094 case 0x44BC: 1095 /* TX_FORMAT0_[0-15] */ 1096 i = (reg - 0x4480) >> 2; 1097 tmp = idx_value & 0x7FF; 1098 track->textures[i].width = tmp + 1; 1099 tmp = (idx_value >> 11) & 0x7FF; 1100 track->textures[i].height = tmp + 1; 1101 tmp = (idx_value >> 26) & 0xF; 1102 track->textures[i].num_levels = tmp; 1103 tmp = idx_value & (1 << 31); 1104 track->textures[i].use_pitch = !!tmp; 1105 tmp = (idx_value >> 22) & 0xF; 1106 track->textures[i].txdepth = tmp; 1107 track->tex_dirty = true; 1108 break; 1109 case R300_ZB_ZPASS_ADDR: 1110 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1111 if (r) { 1112 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1113 idx, reg); 1114 radeon_cs_dump_packet(p, pkt); 1115 return r; 1116 } 1117 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1118 break; 1119 case 0x4e0c: 1120 /* RB3D_COLOR_CHANNEL_MASK */ 1121 track->color_channel_mask = idx_value; 1122 track->cb_dirty = true; 1123 break; 1124 case 0x43a4: 1125 /* SC_HYPERZ_EN */ 1126 /* r300c emits this register - we need to disable hyperz for it 1127 * without complaining */ 1128 if (p->rdev->hyperz_filp != p->filp) { 1129 if (idx_value & 0x1) 1130 ib[idx] = idx_value & ~1; 1131 } 1132 break; 1133 case 0x4f1c: 1134 /* ZB_BW_CNTL */ 1135 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1136 track->cb_dirty = true; 1137 track->zb_dirty = true; 1138 if (p->rdev->hyperz_filp != p->filp) { 1139 if (idx_value & (R300_HIZ_ENABLE | 1140 R300_RD_COMP_ENABLE | 1141 R300_WR_COMP_ENABLE | 1142 R300_FAST_FILL_ENABLE)) 1143 goto fail; 1144 } 1145 break; 1146 case 0x4e04: 1147 /* RB3D_BLENDCNTL */ 1148 track->blend_read_enable = !!(idx_value & (1 << 2)); 1149 track->cb_dirty = true; 1150 break; 1151 case R300_RB3D_AARESOLVE_OFFSET: 1152 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1153 if (r) { 1154 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1155 idx, reg); 1156 radeon_cs_dump_packet(p, pkt); 1157 return r; 1158 } 1159 track->aa.robj = reloc->robj; 1160 track->aa.offset = idx_value; 1161 track->aa_dirty = true; 1162 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1163 break; 1164 case R300_RB3D_AARESOLVE_PITCH: 1165 track->aa.pitch = idx_value & 0x3FFE; 1166 track->aa_dirty = true; 1167 break; 1168 case R300_RB3D_AARESOLVE_CTL: 1169 track->aaresolve = idx_value & 0x1; 1170 track->aa_dirty = true; 1171 break; 1172 case 0x4f30: /* ZB_MASK_OFFSET */ 1173 case 0x4f34: /* ZB_ZMASK_PITCH */ 1174 case 0x4f44: /* ZB_HIZ_OFFSET */ 1175 case 0x4f54: /* ZB_HIZ_PITCH */ 1176 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1177 goto fail; 1178 break; 1179 case 0x4028: 1180 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1181 goto fail; 1182 /* GB_Z_PEQ_CONFIG */ 1183 if (p->rdev->family >= CHIP_RV350) 1184 break; 1185 goto fail; 1186 break; 1187 case 0x4be8: 1188 /* valid register only on RV530 */ 1189 if (p->rdev->family == CHIP_RV530) 1190 break; 1191 /* fallthrough do not move */ 1192 default: 1193 goto fail; 1194 } 1195 return 0; 1196 fail: 1197 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1198 reg, idx, idx_value); 1199 return -EINVAL; 1200 } 1201 1202 static int r300_packet3_check(struct radeon_cs_parser *p, 1203 struct radeon_cs_packet *pkt) 1204 { 1205 struct radeon_bo_list *reloc; 1206 struct r100_cs_track *track; 1207 volatile uint32_t *ib; 1208 unsigned idx; 1209 int r; 1210 1211 ib = p->ib.ptr; 1212 idx = pkt->idx + 1; 1213 track = (struct r100_cs_track *)p->track; 1214 switch(pkt->opcode) { 1215 case PACKET3_3D_LOAD_VBPNTR: 1216 r = r100_packet3_load_vbpntr(p, pkt, idx); 1217 if (r) 1218 return r; 1219 break; 1220 case PACKET3_INDX_BUFFER: 1221 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1222 if (r) { 1223 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1224 radeon_cs_dump_packet(p, pkt); 1225 return r; 1226 } 1227 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1228 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1229 if (r) { 1230 return r; 1231 } 1232 break; 1233 /* Draw packet */ 1234 case PACKET3_3D_DRAW_IMMD: 1235 /* Number of dwords is vtx_size * (num_vertices - 1) 1236 * PRIM_WALK must be equal to 3 vertex data in embedded 1237 * in cmd stream */ 1238 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1239 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1240 return -EINVAL; 1241 } 1242 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1243 track->immd_dwords = pkt->count - 1; 1244 r = r100_cs_track_check(p->rdev, track); 1245 if (r) { 1246 return r; 1247 } 1248 break; 1249 case PACKET3_3D_DRAW_IMMD_2: 1250 /* Number of dwords is vtx_size * (num_vertices - 1) 1251 * PRIM_WALK must be equal to 3 vertex data in embedded 1252 * in cmd stream */ 1253 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1254 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1255 return -EINVAL; 1256 } 1257 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1258 track->immd_dwords = pkt->count; 1259 r = r100_cs_track_check(p->rdev, track); 1260 if (r) { 1261 return r; 1262 } 1263 break; 1264 case PACKET3_3D_DRAW_VBUF: 1265 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1266 r = r100_cs_track_check(p->rdev, track); 1267 if (r) { 1268 return r; 1269 } 1270 break; 1271 case PACKET3_3D_DRAW_VBUF_2: 1272 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1273 r = r100_cs_track_check(p->rdev, track); 1274 if (r) { 1275 return r; 1276 } 1277 break; 1278 case PACKET3_3D_DRAW_INDX: 1279 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1280 r = r100_cs_track_check(p->rdev, track); 1281 if (r) { 1282 return r; 1283 } 1284 break; 1285 case PACKET3_3D_DRAW_INDX_2: 1286 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1287 r = r100_cs_track_check(p->rdev, track); 1288 if (r) { 1289 return r; 1290 } 1291 break; 1292 case PACKET3_3D_CLEAR_HIZ: 1293 case PACKET3_3D_CLEAR_ZMASK: 1294 if (p->rdev->hyperz_filp != p->filp) 1295 return -EINVAL; 1296 break; 1297 case PACKET3_3D_CLEAR_CMASK: 1298 if (p->rdev->cmask_filp != p->filp) 1299 return -EINVAL; 1300 break; 1301 case PACKET3_NOP: 1302 break; 1303 default: 1304 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1305 return -EINVAL; 1306 } 1307 return 0; 1308 } 1309 1310 int r300_cs_parse(struct radeon_cs_parser *p) 1311 { 1312 struct radeon_cs_packet pkt; 1313 struct r100_cs_track *track; 1314 int r; 1315 1316 track = kzalloc(sizeof(*track), GFP_KERNEL); 1317 if (track == NULL) 1318 return -ENOMEM; 1319 r100_cs_track_clear(p->rdev, track); 1320 p->track = track; 1321 do { 1322 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1323 if (r) { 1324 return r; 1325 } 1326 p->idx += pkt.count + 2; 1327 switch (pkt.type) { 1328 case RADEON_PACKET_TYPE0: 1329 r = r100_cs_parse_packet0(p, &pkt, 1330 p->rdev->config.r300.reg_safe_bm, 1331 p->rdev->config.r300.reg_safe_bm_size, 1332 &r300_packet0_check); 1333 break; 1334 case RADEON_PACKET_TYPE2: 1335 break; 1336 case RADEON_PACKET_TYPE3: 1337 r = r300_packet3_check(p, &pkt); 1338 break; 1339 default: 1340 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1341 return -EINVAL; 1342 } 1343 if (r) { 1344 return r; 1345 } 1346 } while (p->idx < p->chunk_ib->length_dw); 1347 return 0; 1348 } 1349 1350 void r300_set_reg_safe(struct radeon_device *rdev) 1351 { 1352 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1353 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1354 } 1355 1356 void r300_mc_program(struct radeon_device *rdev) 1357 { 1358 struct r100_mc_save save; 1359 int r; 1360 1361 r = r100_debugfs_mc_info_init(rdev); 1362 if (r) { 1363 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1364 } 1365 1366 /* Stops all mc clients */ 1367 r100_mc_stop(rdev, &save); 1368 if (rdev->flags & RADEON_IS_AGP) { 1369 WREG32(R_00014C_MC_AGP_LOCATION, 1370 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1371 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1372 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1373 WREG32(R_00015C_AGP_BASE_2, 1374 upper_32_bits(rdev->mc.agp_base) & 0xff); 1375 } else { 1376 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1377 WREG32(R_000170_AGP_BASE, 0); 1378 WREG32(R_00015C_AGP_BASE_2, 0); 1379 } 1380 /* Wait for mc idle */ 1381 if (r300_mc_wait_for_idle(rdev)) 1382 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1383 /* Program MC, should be a 32bits limited address space */ 1384 WREG32(R_000148_MC_FB_LOCATION, 1385 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1386 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1387 r100_mc_resume(rdev, &save); 1388 } 1389 1390 void r300_clock_startup(struct radeon_device *rdev) 1391 { 1392 u32 tmp; 1393 1394 if (radeon_dynclks != -1 && radeon_dynclks) 1395 radeon_legacy_set_clock_gating(rdev, 1); 1396 /* We need to force on some of the block */ 1397 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1398 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1399 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1400 tmp |= S_00000D_FORCE_VAP(1); 1401 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1402 } 1403 1404 static int r300_startup(struct radeon_device *rdev) 1405 { 1406 int r; 1407 1408 /* set common regs */ 1409 r100_set_common_regs(rdev); 1410 /* program mc */ 1411 r300_mc_program(rdev); 1412 /* Resume clock */ 1413 r300_clock_startup(rdev); 1414 /* Initialize GPU configuration (# pipes, ...) */ 1415 r300_gpu_init(rdev); 1416 /* Initialize GART (initialize after TTM so we can allocate 1417 * memory through TTM but finalize after TTM) */ 1418 if (rdev->flags & RADEON_IS_PCIE) { 1419 r = rv370_pcie_gart_enable(rdev); 1420 if (r) 1421 return r; 1422 } 1423 1424 if (rdev->family == CHIP_R300 || 1425 rdev->family == CHIP_R350 || 1426 rdev->family == CHIP_RV350) 1427 r100_enable_bm(rdev); 1428 1429 if (rdev->flags & RADEON_IS_PCI) { 1430 r = r100_pci_gart_enable(rdev); 1431 if (r) 1432 return r; 1433 } 1434 1435 /* allocate wb buffer */ 1436 r = radeon_wb_init(rdev); 1437 if (r) 1438 return r; 1439 1440 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1441 if (r) { 1442 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1443 return r; 1444 } 1445 1446 /* Enable IRQ */ 1447 if (!rdev->irq.installed) { 1448 r = radeon_irq_kms_init(rdev); 1449 if (r) 1450 return r; 1451 } 1452 1453 r100_irq_set(rdev); 1454 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1455 /* 1M ring buffer */ 1456 r = r100_cp_init(rdev, 1024 * 1024); 1457 if (r) { 1458 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1459 return r; 1460 } 1461 1462 r = radeon_ib_pool_init(rdev); 1463 if (r) { 1464 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1465 return r; 1466 } 1467 1468 return 0; 1469 } 1470 1471 int r300_resume(struct radeon_device *rdev) 1472 { 1473 int r; 1474 1475 /* Make sur GART are not working */ 1476 if (rdev->flags & RADEON_IS_PCIE) 1477 rv370_pcie_gart_disable(rdev); 1478 if (rdev->flags & RADEON_IS_PCI) 1479 r100_pci_gart_disable(rdev); 1480 /* Resume clock before doing reset */ 1481 r300_clock_startup(rdev); 1482 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1483 if (radeon_asic_reset(rdev)) { 1484 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1485 RREG32(R_000E40_RBBM_STATUS), 1486 RREG32(R_0007C0_CP_STAT)); 1487 } 1488 /* post */ 1489 radeon_combios_asic_init(rdev->ddev); 1490 /* Resume clock after posting */ 1491 r300_clock_startup(rdev); 1492 /* Initialize surface registers */ 1493 radeon_surface_init(rdev); 1494 1495 rdev->accel_working = true; 1496 r = r300_startup(rdev); 1497 if (r) { 1498 rdev->accel_working = false; 1499 } 1500 return r; 1501 } 1502 1503 int r300_suspend(struct radeon_device *rdev) 1504 { 1505 radeon_pm_suspend(rdev); 1506 r100_cp_disable(rdev); 1507 radeon_wb_disable(rdev); 1508 r100_irq_disable(rdev); 1509 if (rdev->flags & RADEON_IS_PCIE) 1510 rv370_pcie_gart_disable(rdev); 1511 if (rdev->flags & RADEON_IS_PCI) 1512 r100_pci_gart_disable(rdev); 1513 return 0; 1514 } 1515 1516 void r300_fini(struct radeon_device *rdev) 1517 { 1518 radeon_pm_fini(rdev); 1519 r100_cp_fini(rdev); 1520 radeon_wb_fini(rdev); 1521 radeon_ib_pool_fini(rdev); 1522 radeon_gem_fini(rdev); 1523 if (rdev->flags & RADEON_IS_PCIE) 1524 rv370_pcie_gart_fini(rdev); 1525 if (rdev->flags & RADEON_IS_PCI) 1526 r100_pci_gart_fini(rdev); 1527 radeon_agp_fini(rdev); 1528 radeon_irq_kms_fini(rdev); 1529 radeon_fence_driver_fini(rdev); 1530 radeon_bo_fini(rdev); 1531 radeon_atombios_fini(rdev); 1532 kfree(rdev->bios); 1533 rdev->bios = NULL; 1534 } 1535 1536 int r300_init(struct radeon_device *rdev) 1537 { 1538 int r; 1539 1540 /* Disable VGA */ 1541 r100_vga_render_disable(rdev); 1542 /* Initialize scratch registers */ 1543 radeon_scratch_init(rdev); 1544 /* Initialize surface registers */ 1545 radeon_surface_init(rdev); 1546 /* TODO: disable VGA need to use VGA request */ 1547 /* restore some register to sane defaults */ 1548 r100_restore_sanity(rdev); 1549 /* BIOS*/ 1550 if (!radeon_get_bios(rdev)) { 1551 if (ASIC_IS_AVIVO(rdev)) 1552 return -EINVAL; 1553 } 1554 if (rdev->is_atom_bios) { 1555 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1556 return -EINVAL; 1557 } else { 1558 r = radeon_combios_init(rdev); 1559 if (r) 1560 return r; 1561 } 1562 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1563 if (radeon_asic_reset(rdev)) { 1564 dev_warn(rdev->dev, 1565 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1566 RREG32(R_000E40_RBBM_STATUS), 1567 RREG32(R_0007C0_CP_STAT)); 1568 } 1569 /* check if cards are posted or not */ 1570 if (radeon_boot_test_post_card(rdev) == false) 1571 return -EINVAL; 1572 /* Set asic errata */ 1573 r300_errata(rdev); 1574 /* Initialize clocks */ 1575 radeon_get_clock_info(rdev->ddev); 1576 /* initialize AGP */ 1577 if (rdev->flags & RADEON_IS_AGP) { 1578 r = radeon_agp_init(rdev); 1579 if (r) { 1580 radeon_agp_disable(rdev); 1581 } 1582 } 1583 /* initialize memory controller */ 1584 r300_mc_init(rdev); 1585 /* Fence driver */ 1586 r = radeon_fence_driver_init(rdev); 1587 if (r) 1588 return r; 1589 /* Memory manager */ 1590 r = radeon_bo_init(rdev); 1591 if (r) 1592 return r; 1593 if (rdev->flags & RADEON_IS_PCIE) { 1594 r = rv370_pcie_gart_init(rdev); 1595 if (r) 1596 return r; 1597 } 1598 if (rdev->flags & RADEON_IS_PCI) { 1599 r = r100_pci_gart_init(rdev); 1600 if (r) 1601 return r; 1602 } 1603 r300_set_reg_safe(rdev); 1604 1605 /* Initialize power management */ 1606 radeon_pm_init(rdev); 1607 1608 rdev->accel_working = true; 1609 r = r300_startup(rdev); 1610 if (r) { 1611 /* Something went wrong with the accel init, so stop accel */ 1612 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1613 r100_cp_fini(rdev); 1614 radeon_wb_fini(rdev); 1615 radeon_ib_pool_fini(rdev); 1616 radeon_irq_kms_fini(rdev); 1617 if (rdev->flags & RADEON_IS_PCIE) 1618 rv370_pcie_gart_fini(rdev); 1619 if (rdev->flags & RADEON_IS_PCI) 1620 r100_pci_gart_fini(rdev); 1621 radeon_agp_fini(rdev); 1622 rdev->accel_working = false; 1623 } 1624 return 0; 1625 } 1626