1 /* $NetBSD: radeon_object.c,v 1.7 2020/02/14 04:35:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 Jerome Glisse. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Jerome Glisse <glisse@freedesktop.org> 31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 32 * Dave Airlie 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: radeon_object.c,v 1.7 2020/02/14 04:35:20 riastradh Exp $"); 36 37 #include <linux/list.h> 38 #include <linux/slab.h> 39 #include <drm/drmP.h> 40 #include <drm/radeon_drm.h> 41 #include <drm/drm_cache.h> 42 #include "radeon.h" 43 #include "radeon_trace.h" 44 45 #include <linux/nbsd-namespace.h> 46 47 48 int radeon_ttm_init(struct radeon_device *rdev); 49 void radeon_ttm_fini(struct radeon_device *rdev); 50 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 51 52 /* 53 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 54 * function are calling it. 55 */ 56 57 static void radeon_update_memory_usage(struct radeon_bo *bo, 58 unsigned mem_type, int sign) 59 { 60 struct radeon_device *rdev = bo->rdev; 61 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; 62 63 switch (mem_type) { 64 case TTM_PL_TT: 65 if (sign > 0) 66 atomic64_add(size, &rdev->gtt_usage); 67 else 68 atomic64_sub(size, &rdev->gtt_usage); 69 break; 70 case TTM_PL_VRAM: 71 if (sign > 0) 72 atomic64_add(size, &rdev->vram_usage); 73 else 74 atomic64_sub(size, &rdev->vram_usage); 75 break; 76 } 77 } 78 79 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct radeon_bo *bo; 82 83 bo = container_of(tbo, struct radeon_bo, tbo); 84 85 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 86 87 mutex_lock(&bo->rdev->gem.mutex); 88 list_del_init(&bo->list); 89 mutex_unlock(&bo->rdev->gem.mutex); 90 radeon_bo_clear_surface_reg(bo); 91 WARN_ON(!list_empty(&bo->va)); 92 drm_gem_object_release(&bo->gem_base); 93 kfree(bo); 94 } 95 96 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 97 { 98 if (bo->destroy == &radeon_ttm_bo_destroy) 99 return true; 100 return false; 101 } 102 103 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 104 { 105 u32 c = 0, i; 106 107 rbo->placement.placement = rbo->placements; 108 rbo->placement.busy_placement = rbo->placements; 109 if (domain & RADEON_GEM_DOMAIN_VRAM) { 110 /* Try placing BOs which don't need CPU access outside of the 111 * CPU accessible part of VRAM 112 */ 113 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && 114 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 115 rbo->placements[c].fpfn = 116 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 117 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 118 TTM_PL_FLAG_UNCACHED | 119 TTM_PL_FLAG_VRAM; 120 } 121 122 rbo->placements[c].fpfn = 0; 123 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 124 TTM_PL_FLAG_UNCACHED | 125 TTM_PL_FLAG_VRAM; 126 } 127 128 if (domain & RADEON_GEM_DOMAIN_GTT) { 129 if (rbo->flags & RADEON_GEM_GTT_UC) { 130 rbo->placements[c].fpfn = 0; 131 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 132 TTM_PL_FLAG_TT; 133 134 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 135 (rbo->rdev->flags & RADEON_IS_AGP)) { 136 rbo->placements[c].fpfn = 0; 137 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 138 TTM_PL_FLAG_UNCACHED | 139 TTM_PL_FLAG_TT; 140 } else { 141 rbo->placements[c].fpfn = 0; 142 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 143 TTM_PL_FLAG_TT; 144 } 145 } 146 147 if (domain & RADEON_GEM_DOMAIN_CPU) { 148 if (rbo->flags & RADEON_GEM_GTT_UC) { 149 rbo->placements[c].fpfn = 0; 150 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 151 TTM_PL_FLAG_SYSTEM; 152 153 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 154 rbo->rdev->flags & RADEON_IS_AGP) { 155 rbo->placements[c].fpfn = 0; 156 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 157 TTM_PL_FLAG_UNCACHED | 158 TTM_PL_FLAG_SYSTEM; 159 } else { 160 rbo->placements[c].fpfn = 0; 161 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 162 TTM_PL_FLAG_SYSTEM; 163 } 164 } 165 if (!c) { 166 rbo->placements[c].fpfn = 0; 167 rbo->placements[c++].flags = TTM_PL_MASK_CACHING | 168 TTM_PL_FLAG_SYSTEM; 169 } 170 171 rbo->placement.num_placement = c; 172 rbo->placement.num_busy_placement = c; 173 174 for (i = 0; i < c; ++i) { 175 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 176 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 177 !rbo->placements[i].fpfn) 178 rbo->placements[i].lpfn = 179 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 180 else 181 rbo->placements[i].lpfn = 0; 182 } 183 } 184 185 int radeon_bo_create(struct radeon_device *rdev, 186 unsigned long size, int byte_align, bool kernel, 187 u32 domain, u32 flags, struct sg_table *sg, 188 struct reservation_object *resv, 189 struct radeon_bo **bo_ptr) 190 { 191 struct radeon_bo *bo; 192 enum ttm_bo_type type; 193 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 194 size_t acc_size; 195 int r; 196 197 size = ALIGN(size, PAGE_SIZE); 198 199 if (kernel) { 200 type = ttm_bo_type_kernel; 201 } else if (sg) { 202 type = ttm_bo_type_sg; 203 } else { 204 type = ttm_bo_type_device; 205 } 206 *bo_ptr = NULL; 207 208 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 209 sizeof(struct radeon_bo)); 210 211 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 212 if (bo == NULL) 213 return -ENOMEM; 214 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 215 if (unlikely(r)) { 216 kfree(bo); 217 return r; 218 } 219 bo->rdev = rdev; 220 bo->surface_reg = -1; 221 INIT_LIST_HEAD(&bo->list); 222 INIT_LIST_HEAD(&bo->va); 223 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 224 RADEON_GEM_DOMAIN_GTT | 225 RADEON_GEM_DOMAIN_CPU); 226 227 bo->flags = flags; 228 /* PCI GART is always snooped */ 229 if (!(rdev->flags & RADEON_IS_PCIE)) 230 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 231 232 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx 233 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 234 */ 235 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) 236 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 237 238 #ifdef CONFIG_X86_32 239 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 240 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 241 */ 242 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 243 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 244 /* Don't try to enable write-combining when it can't work, or things 245 * may be slow 246 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 247 */ 248 #ifndef CONFIG_COMPILE_TEST 249 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 250 thanks to write-combining 251 #endif 252 253 if (bo->flags & RADEON_GEM_GTT_WC) 254 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 255 "better performance thanks to write-combining\n"); 256 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 257 #else 258 /* For architectures that don't support WC memory, 259 * mask out the WC flag from the BO 260 */ 261 if (!drm_arch_can_wc_memory()) 262 bo->flags &= ~RADEON_GEM_GTT_WC; 263 #endif 264 265 radeon_ttm_placement_from_domain(bo, domain); 266 /* Kernel allocation are uninterruptible */ 267 down_read(&rdev->pm.mclk_lock); 268 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 269 &bo->placement, page_align, !kernel, NULL, 270 acc_size, sg, resv, &radeon_ttm_bo_destroy); 271 up_read(&rdev->pm.mclk_lock); 272 if (unlikely(r != 0)) { 273 return r; 274 } 275 *bo_ptr = bo; 276 277 trace_radeon_bo_create(bo); 278 279 return 0; 280 } 281 282 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 283 { 284 bool is_iomem; 285 int r; 286 287 if (bo->kptr) { 288 if (ptr) { 289 *ptr = bo->kptr; 290 } 291 return 0; 292 } 293 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 294 if (r) { 295 return r; 296 } 297 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 298 if (ptr) { 299 *ptr = bo->kptr; 300 } 301 radeon_bo_check_tiling(bo, 0, 0); 302 return 0; 303 } 304 305 void radeon_bo_kunmap(struct radeon_bo *bo) 306 { 307 if (bo->kptr == NULL) 308 return; 309 bo->kptr = NULL; 310 radeon_bo_check_tiling(bo, 0, 0); 311 ttm_bo_kunmap(&bo->kmap); 312 } 313 314 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 315 { 316 if (bo == NULL) 317 return NULL; 318 319 ttm_bo_reference(&bo->tbo); 320 return bo; 321 } 322 323 void radeon_bo_unref(struct radeon_bo **bo) 324 { 325 struct ttm_buffer_object *tbo; 326 struct radeon_device *rdev __unused; 327 328 if ((*bo) == NULL) 329 return; 330 rdev = (*bo)->rdev; 331 tbo = &((*bo)->tbo); 332 ttm_bo_unref(&tbo); 333 if (tbo == NULL) 334 *bo = NULL; 335 } 336 337 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 338 u64 *gpu_addr) 339 { 340 int r, i; 341 342 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) 343 return -EPERM; 344 345 if (bo->pin_count) { 346 bo->pin_count++; 347 if (gpu_addr) 348 *gpu_addr = radeon_bo_gpu_offset(bo); 349 350 if (max_offset != 0) { 351 u64 domain_start; 352 353 if (domain == RADEON_GEM_DOMAIN_VRAM) 354 domain_start = bo->rdev->mc.vram_start; 355 else 356 domain_start = bo->rdev->mc.gtt_start; 357 WARN_ON_ONCE(max_offset < 358 (radeon_bo_gpu_offset(bo) - domain_start)); 359 } 360 361 return 0; 362 } 363 radeon_ttm_placement_from_domain(bo, domain); 364 for (i = 0; i < bo->placement.num_placement; i++) { 365 /* force to pin into visible video ram */ 366 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 367 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 368 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 369 bo->placements[i].lpfn = 370 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 371 else 372 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 373 374 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 375 } 376 377 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 378 if (likely(r == 0)) { 379 bo->pin_count = 1; 380 if (gpu_addr != NULL) 381 *gpu_addr = radeon_bo_gpu_offset(bo); 382 if (domain == RADEON_GEM_DOMAIN_VRAM) 383 bo->rdev->vram_pin_size += radeon_bo_size(bo); 384 else 385 bo->rdev->gart_pin_size += radeon_bo_size(bo); 386 } else { 387 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 388 } 389 return r; 390 } 391 392 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 393 { 394 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 395 } 396 397 int radeon_bo_unpin(struct radeon_bo *bo) 398 { 399 int r, i; 400 401 if (!bo->pin_count) { 402 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 403 return 0; 404 } 405 bo->pin_count--; 406 if (bo->pin_count) 407 return 0; 408 for (i = 0; i < bo->placement.num_placement; i++) { 409 bo->placements[i].lpfn = 0; 410 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 411 } 412 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 413 if (likely(r == 0)) { 414 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 415 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 416 else 417 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 418 } else { 419 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 420 } 421 return r; 422 } 423 424 int radeon_bo_evict_vram(struct radeon_device *rdev) 425 { 426 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 427 if (0 && (rdev->flags & RADEON_IS_IGP)) { 428 if (rdev->mc.igp_sideport_enabled == false) 429 /* Useless to evict on IGP chips */ 430 return 0; 431 } 432 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 433 } 434 435 void radeon_bo_force_delete(struct radeon_device *rdev) 436 { 437 struct radeon_bo *bo, *n; 438 439 if (list_empty(&rdev->gem.objects)) { 440 return; 441 } 442 dev_err(rdev->dev, "Userspace still has active objects !\n"); 443 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 444 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 445 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 446 *((unsigned long *)&bo->gem_base.refcount)); 447 mutex_lock(&bo->rdev->gem.mutex); 448 list_del_init(&bo->list); 449 mutex_unlock(&bo->rdev->gem.mutex); 450 /* this should unref the ttm bo */ 451 drm_gem_object_unreference_unlocked(&bo->gem_base); 452 } 453 } 454 455 int radeon_bo_init(struct radeon_device *rdev) 456 { 457 /* Add an MTRR for the VRAM */ 458 if (!rdev->fastfb_working) { 459 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 460 rdev->mc.aper_size); 461 } 462 #ifdef __NetBSD__ 463 if (rdev->mc.aper_base) 464 pmap_pv_track(rdev->mc.aper_base, rdev->mc.aper_size); 465 #endif 466 DRM_INFO("Detected VRAM RAM=%"PRIx64"M, BAR=%lluM\n", 467 rdev->mc.mc_vram_size >> 20, 468 (unsigned long long)rdev->mc.aper_size >> 20); 469 DRM_INFO("RAM width %dbits %cDR\n", 470 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 471 return radeon_ttm_init(rdev); 472 } 473 474 void radeon_bo_fini(struct radeon_device *rdev) 475 { 476 radeon_ttm_fini(rdev); 477 #ifdef __NetBSD__ 478 if (rdev->mc.aper_base) 479 pmap_pv_untrack(rdev->mc.aper_base, rdev->mc.aper_size); 480 #endif 481 arch_phys_wc_del(rdev->mc.vram_mtrr); 482 } 483 484 /* Returns how many bytes TTM can move per IB. 485 */ 486 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 487 { 488 u64 real_vram_size = rdev->mc.real_vram_size; 489 u64 vram_usage = atomic64_read(&rdev->vram_usage); 490 491 /* This function is based on the current VRAM usage. 492 * 493 * - If all of VRAM is free, allow relocating the number of bytes that 494 * is equal to 1/4 of the size of VRAM for this IB. 495 496 * - If more than one half of VRAM is occupied, only allow relocating 497 * 1 MB of data for this IB. 498 * 499 * - From 0 to one half of used VRAM, the threshold decreases 500 * linearly. 501 * __________________ 502 * 1/4 of -|\ | 503 * VRAM | \ | 504 * | \ | 505 * | \ | 506 * | \ | 507 * | \ | 508 * | \ | 509 * | \________|1 MB 510 * |----------------| 511 * VRAM 0 % 100 % 512 * used used 513 * 514 * Note: It's a threshold, not a limit. The threshold must be crossed 515 * for buffer relocations to stop, so any buffer of an arbitrary size 516 * can be moved as long as the threshold isn't crossed before 517 * the relocation takes place. We don't want to disable buffer 518 * relocations completely. 519 * 520 * The idea is that buffers should be placed in VRAM at creation time 521 * and TTM should only do a minimum number of relocations during 522 * command submission. In practice, you need to submit at least 523 * a dozen IBs to move all buffers to VRAM if they are in GTT. 524 * 525 * Also, things can get pretty crazy under memory pressure and actual 526 * VRAM usage can change a lot, so playing safe even at 50% does 527 * consistently increase performance. 528 */ 529 530 u64 half_vram = real_vram_size >> 1; 531 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 532 u64 bytes_moved_threshold = half_free_vram >> 1; 533 return max(bytes_moved_threshold, 1024*1024ull); 534 } 535 536 int radeon_bo_list_validate(struct radeon_device *rdev, 537 struct ww_acquire_ctx *ticket, 538 struct list_head *head, int ring) 539 { 540 struct radeon_bo_list *lobj; 541 struct list_head duplicates; 542 int r; 543 u64 bytes_moved = 0, initial_bytes_moved; 544 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 545 546 INIT_LIST_HEAD(&duplicates); 547 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); 548 if (unlikely(r != 0)) { 549 return r; 550 } 551 552 list_for_each_entry(lobj, head, tv.head) { 553 struct radeon_bo *bo = lobj->robj; 554 if (!bo->pin_count) { 555 u32 domain = lobj->prefered_domains; 556 u32 allowed = lobj->allowed_domains; 557 u32 current_domain = 558 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 559 560 /* Check if this buffer will be moved and don't move it 561 * if we have moved too many buffers for this IB already. 562 * 563 * Note that this allows moving at least one buffer of 564 * any size, because it doesn't take the current "bo" 565 * into account. We don't want to disallow buffer moves 566 * completely. 567 */ 568 if ((allowed & current_domain) != 0 && 569 (domain & current_domain) == 0 && /* will be moved */ 570 bytes_moved > bytes_moved_threshold) { 571 /* don't move it */ 572 domain = current_domain; 573 } 574 575 retry: 576 radeon_ttm_placement_from_domain(bo, domain); 577 if (ring == R600_RING_TYPE_UVD_INDEX) 578 radeon_uvd_force_into_uvd_segment(bo, allowed); 579 580 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 581 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 582 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 583 initial_bytes_moved; 584 585 if (unlikely(r)) { 586 if (r != -ERESTARTSYS && 587 domain != lobj->allowed_domains) { 588 domain = lobj->allowed_domains; 589 goto retry; 590 } 591 ttm_eu_backoff_reservation(ticket, head); 592 return r; 593 } 594 } 595 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 596 lobj->tiling_flags = bo->tiling_flags; 597 } 598 599 list_for_each_entry(lobj, &duplicates, tv.head) { 600 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); 601 lobj->tiling_flags = lobj->robj->tiling_flags; 602 } 603 604 return 0; 605 } 606 607 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 608 { 609 struct radeon_device *rdev = bo->rdev; 610 struct radeon_surface_reg *reg; 611 struct radeon_bo *old_object; 612 int steal; 613 int i; 614 615 lockdep_assert_held(&bo->tbo.resv->lock.base); 616 617 if (!bo->tiling_flags) 618 return 0; 619 620 if (bo->surface_reg >= 0) { 621 reg = &rdev->surface_regs[bo->surface_reg]; 622 i = bo->surface_reg; 623 goto out; 624 } 625 626 steal = -1; 627 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 628 629 reg = &rdev->surface_regs[i]; 630 if (!reg->bo) 631 break; 632 633 old_object = reg->bo; 634 if (old_object->pin_count == 0) 635 steal = i; 636 } 637 638 /* if we are all out */ 639 if (i == RADEON_GEM_MAX_SURFACES) { 640 if (steal == -1) 641 return -ENOMEM; 642 /* find someone with a surface reg and nuke their BO */ 643 reg = &rdev->surface_regs[steal]; 644 old_object = reg->bo; 645 /* blow away the mapping */ 646 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 647 ttm_bo_unmap_virtual(&old_object->tbo); 648 old_object->surface_reg = -1; 649 i = steal; 650 } 651 652 bo->surface_reg = i; 653 reg->bo = bo; 654 655 out: 656 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 657 bo->tbo.mem.start << PAGE_SHIFT, 658 bo->tbo.num_pages << PAGE_SHIFT); 659 return 0; 660 } 661 662 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 663 { 664 struct radeon_device *rdev = bo->rdev; 665 struct radeon_surface_reg *reg; 666 667 if (bo->surface_reg == -1) 668 return; 669 670 reg = &rdev->surface_regs[bo->surface_reg]; 671 radeon_clear_surface_reg(rdev, bo->surface_reg); 672 673 reg->bo = NULL; 674 bo->surface_reg = -1; 675 } 676 677 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 678 uint32_t tiling_flags, uint32_t pitch) 679 { 680 struct radeon_device *rdev = bo->rdev; 681 int r; 682 683 if (rdev->family >= CHIP_CEDAR) { 684 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 685 686 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 687 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 688 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 689 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 690 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 691 switch (bankw) { 692 case 0: 693 case 1: 694 case 2: 695 case 4: 696 case 8: 697 break; 698 default: 699 return -EINVAL; 700 } 701 switch (bankh) { 702 case 0: 703 case 1: 704 case 2: 705 case 4: 706 case 8: 707 break; 708 default: 709 return -EINVAL; 710 } 711 switch (mtaspect) { 712 case 0: 713 case 1: 714 case 2: 715 case 4: 716 case 8: 717 break; 718 default: 719 return -EINVAL; 720 } 721 if (tilesplit > 6) { 722 return -EINVAL; 723 } 724 if (stilesplit > 6) { 725 return -EINVAL; 726 } 727 } 728 r = radeon_bo_reserve(bo, false); 729 if (unlikely(r != 0)) 730 return r; 731 bo->tiling_flags = tiling_flags; 732 bo->pitch = pitch; 733 radeon_bo_unreserve(bo); 734 return 0; 735 } 736 737 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 738 uint32_t *tiling_flags, 739 uint32_t *pitch) 740 { 741 lockdep_assert_held(&bo->tbo.resv->lock.base); 742 743 if (tiling_flags) 744 *tiling_flags = bo->tiling_flags; 745 if (pitch) 746 *pitch = bo->pitch; 747 } 748 749 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 750 bool force_drop) 751 { 752 if (!force_drop) 753 lockdep_assert_held(&bo->tbo.resv->lock.base); 754 755 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 756 return 0; 757 758 if (force_drop) { 759 radeon_bo_clear_surface_reg(bo); 760 return 0; 761 } 762 763 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 764 if (!has_moved) 765 return 0; 766 767 if (bo->surface_reg >= 0) 768 radeon_bo_clear_surface_reg(bo); 769 return 0; 770 } 771 772 if ((bo->surface_reg >= 0) && !has_moved) 773 return 0; 774 775 return radeon_bo_get_surface_reg(bo); 776 } 777 778 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 779 struct ttm_mem_reg *new_mem) 780 { 781 struct radeon_bo *rbo; 782 783 if (!radeon_ttm_bo_is_radeon_bo(bo)) 784 return; 785 786 rbo = container_of(bo, struct radeon_bo, tbo); 787 radeon_bo_check_tiling(rbo, 0, 1); 788 radeon_vm_bo_invalidate(rbo->rdev, rbo); 789 790 /* update statistics */ 791 if (!new_mem) 792 return; 793 794 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 795 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 796 } 797 798 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 799 { 800 struct radeon_device *rdev; 801 struct radeon_bo *rbo; 802 unsigned long offset, size, lpfn; 803 int i, r; 804 805 if (!radeon_ttm_bo_is_radeon_bo(bo)) 806 return 0; 807 rbo = container_of(bo, struct radeon_bo, tbo); 808 radeon_bo_check_tiling(rbo, 0, 0); 809 rdev = rbo->rdev; 810 if (bo->mem.mem_type != TTM_PL_VRAM) 811 return 0; 812 813 size = bo->mem.num_pages << PAGE_SHIFT; 814 offset = bo->mem.start << PAGE_SHIFT; 815 if ((offset + size) <= rdev->mc.visible_vram_size) 816 return 0; 817 818 /* hurrah the memory is not visible ! */ 819 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 820 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 821 for (i = 0; i < rbo->placement.num_placement; i++) { 822 /* Force into visible VRAM */ 823 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 824 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 825 rbo->placements[i].lpfn = lpfn; 826 } 827 r = ttm_bo_validate(bo, &rbo->placement, false, false); 828 if (unlikely(r == -ENOMEM)) { 829 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 830 return ttm_bo_validate(bo, &rbo->placement, false, false); 831 } else if (unlikely(r != 0)) { 832 return r; 833 } 834 835 offset = bo->mem.start << PAGE_SHIFT; 836 /* this should never happen */ 837 if ((offset + size) > rdev->mc.visible_vram_size) 838 return -EINVAL; 839 840 return 0; 841 } 842 843 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 844 { 845 int r; 846 847 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); 848 if (unlikely(r != 0)) 849 return r; 850 if (mem_type) 851 *mem_type = bo->tbo.mem.mem_type; 852 853 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 854 ttm_bo_unreserve(&bo->tbo); 855 return r; 856 } 857 858 /** 859 * radeon_bo_fence - add fence to buffer object 860 * 861 * @bo: buffer object in question 862 * @fence: fence to add 863 * @shared: true if fence should be added shared 864 * 865 */ 866 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 867 bool shared) 868 { 869 struct reservation_object *resv = bo->tbo.resv; 870 871 if (shared) 872 reservation_object_add_shared_fence(resv, &fence->base); 873 else 874 reservation_object_add_excl_fence(resv, &fence->base); 875 } 876