1 /* $NetBSD: radeon_ni.c,v 1.2 2020/02/14 04:35:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_ni.c,v 1.2 2020/02/14 04:35:20 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <drm/drmP.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_audio.h" 36 #include <drm/radeon_drm.h> 37 #include "nid.h" 38 #include "atom.h" 39 #include "ni_reg.h" 40 #include "cayman_blit_shaders.h" 41 #include "radeon_ucode.h" 42 #include "clearstate_cayman.h" 43 44 #include <linux/nbsd-namespace.h> 45 46 /* 47 * Indirect registers accessor 48 */ 49 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 50 { 51 unsigned long flags; 52 u32 r; 53 54 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 55 WREG32(TN_SMC_IND_INDEX_0, (reg)); 56 r = RREG32(TN_SMC_IND_DATA_0); 57 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 58 return r; 59 } 60 61 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 62 { 63 unsigned long flags; 64 65 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 66 WREG32(TN_SMC_IND_INDEX_0, (reg)); 67 WREG32(TN_SMC_IND_DATA_0, (v)); 68 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 69 } 70 71 static const u32 tn_rlc_save_restore_register_list[] = 72 { 73 0x98fc, 74 0x98f0, 75 0x9834, 76 0x9838, 77 0x9870, 78 0x9874, 79 0x8a14, 80 0x8b24, 81 0x8bcc, 82 0x8b10, 83 0x8c30, 84 0x8d00, 85 0x8d04, 86 0x8c00, 87 0x8c04, 88 0x8c10, 89 0x8c14, 90 0x8d8c, 91 0x8cf0, 92 0x8e38, 93 0x9508, 94 0x9688, 95 0x9608, 96 0x960c, 97 0x9610, 98 0x9614, 99 0x88c4, 100 0x8978, 101 0x88d4, 102 0x900c, 103 0x9100, 104 0x913c, 105 0x90e8, 106 0x9354, 107 0xa008, 108 0x98f8, 109 0x9148, 110 0x914c, 111 0x3f94, 112 0x98f4, 113 0x9b7c, 114 0x3f8c, 115 0x8950, 116 0x8954, 117 0x8a18, 118 0x8b28, 119 0x9144, 120 0x3f90, 121 0x915c, 122 0x9160, 123 0x9178, 124 0x917c, 125 0x9180, 126 0x918c, 127 0x9190, 128 0x9194, 129 0x9198, 130 0x919c, 131 0x91a8, 132 0x91ac, 133 0x91b0, 134 0x91b4, 135 0x91b8, 136 0x91c4, 137 0x91c8, 138 0x91cc, 139 0x91d0, 140 0x91d4, 141 0x91e0, 142 0x91e4, 143 0x91ec, 144 0x91f0, 145 0x91f4, 146 0x9200, 147 0x9204, 148 0x929c, 149 0x8030, 150 0x9150, 151 0x9a60, 152 0x920c, 153 0x9210, 154 0x9228, 155 0x922c, 156 0x9244, 157 0x9248, 158 0x91e8, 159 0x9294, 160 0x9208, 161 0x9224, 162 0x9240, 163 0x9220, 164 0x923c, 165 0x9258, 166 0x9744, 167 0xa200, 168 0xa204, 169 0xa208, 170 0xa20c, 171 0x8d58, 172 0x9030, 173 0x9034, 174 0x9038, 175 0x903c, 176 0x9040, 177 0x9654, 178 0x897c, 179 0xa210, 180 0xa214, 181 0x9868, 182 0xa02c, 183 0x9664, 184 0x9698, 185 0x949c, 186 0x8e10, 187 0x8e18, 188 0x8c50, 189 0x8c58, 190 0x8c60, 191 0x8c68, 192 0x89b4, 193 0x9830, 194 0x802c, 195 }; 196 197 extern bool evergreen_is_display_hung(struct radeon_device *rdev); 198 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 199 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 200 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 201 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 202 extern void evergreen_mc_program(struct radeon_device *rdev); 203 extern void evergreen_irq_suspend(struct radeon_device *rdev); 204 extern int evergreen_mc_init(struct radeon_device *rdev); 205 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 206 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 207 extern void evergreen_program_aspm(struct radeon_device *rdev); 208 extern void sumo_rlc_fini(struct radeon_device *rdev); 209 extern int sumo_rlc_init(struct radeon_device *rdev); 210 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); 211 212 /* Firmware Names */ 213 MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 214 MODULE_FIRMWARE("radeon/BARTS_me.bin"); 215 MODULE_FIRMWARE("radeon/BARTS_mc.bin"); 216 MODULE_FIRMWARE("radeon/BARTS_smc.bin"); 217 MODULE_FIRMWARE("radeon/BTC_rlc.bin"); 218 MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); 219 MODULE_FIRMWARE("radeon/TURKS_me.bin"); 220 MODULE_FIRMWARE("radeon/TURKS_mc.bin"); 221 MODULE_FIRMWARE("radeon/TURKS_smc.bin"); 222 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 223 MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 224 MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 225 MODULE_FIRMWARE("radeon/CAICOS_smc.bin"); 226 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); 227 MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); 228 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); 229 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); 230 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin"); 231 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); 232 MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 233 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 234 235 236 static const u32 cayman_golden_registers2[] = 237 { 238 0x3e5c, 0xffffffff, 0x00000000, 239 0x3e48, 0xffffffff, 0x00000000, 240 0x3e4c, 0xffffffff, 0x00000000, 241 0x3e64, 0xffffffff, 0x00000000, 242 0x3e50, 0xffffffff, 0x00000000, 243 0x3e60, 0xffffffff, 0x00000000 244 }; 245 246 static const u32 cayman_golden_registers[] = 247 { 248 0x5eb4, 0xffffffff, 0x00000002, 249 0x5e78, 0x8f311ff1, 0x001000f0, 250 0x3f90, 0xffff0000, 0xff000000, 251 0x9148, 0xffff0000, 0xff000000, 252 0x3f94, 0xffff0000, 0xff000000, 253 0x914c, 0xffff0000, 0xff000000, 254 0xc78, 0x00000080, 0x00000080, 255 0xbd4, 0x70073777, 0x00011003, 256 0xd02c, 0xbfffff1f, 0x08421000, 257 0xd0b8, 0x73773777, 0x02011003, 258 0x5bc0, 0x00200000, 0x50100000, 259 0x98f8, 0x33773777, 0x02011003, 260 0x98fc, 0xffffffff, 0x76541032, 261 0x7030, 0x31000311, 0x00000011, 262 0x2f48, 0x33773777, 0x42010001, 263 0x6b28, 0x00000010, 0x00000012, 264 0x7728, 0x00000010, 0x00000012, 265 0x10328, 0x00000010, 0x00000012, 266 0x10f28, 0x00000010, 0x00000012, 267 0x11b28, 0x00000010, 0x00000012, 268 0x12728, 0x00000010, 0x00000012, 269 0x240c, 0x000007ff, 0x00000000, 270 0x8a14, 0xf000001f, 0x00000007, 271 0x8b24, 0x3fff3fff, 0x00ff0fff, 272 0x8b10, 0x0000ff0f, 0x00000000, 273 0x28a4c, 0x07ffffff, 0x06000000, 274 0x10c, 0x00000001, 0x00010003, 275 0xa02c, 0xffffffff, 0x0000009b, 276 0x913c, 0x0000010f, 0x01000100, 277 0x8c04, 0xf8ff00ff, 0x40600060, 278 0x28350, 0x00000f01, 0x00000000, 279 0x9508, 0x3700001f, 0x00000002, 280 0x960c, 0xffffffff, 0x54763210, 281 0x88c4, 0x001f3ae3, 0x00000082, 282 0x88d0, 0xffffffff, 0x0f40df40, 283 0x88d4, 0x0000001f, 0x00000010, 284 0x8974, 0xffffffff, 0x00000000 285 }; 286 287 static const u32 dvst_golden_registers2[] = 288 { 289 0x8f8, 0xffffffff, 0, 290 0x8fc, 0x00380000, 0, 291 0x8f8, 0xffffffff, 1, 292 0x8fc, 0x0e000000, 0 293 }; 294 295 static const u32 dvst_golden_registers[] = 296 { 297 0x690, 0x3fff3fff, 0x20c00033, 298 0x918c, 0x0fff0fff, 0x00010006, 299 0x91a8, 0x0fff0fff, 0x00010006, 300 0x9150, 0xffffdfff, 0x6e944040, 301 0x917c, 0x0fff0fff, 0x00030002, 302 0x9198, 0x0fff0fff, 0x00030002, 303 0x915c, 0x0fff0fff, 0x00010000, 304 0x3f90, 0xffff0001, 0xff000000, 305 0x9178, 0x0fff0fff, 0x00070000, 306 0x9194, 0x0fff0fff, 0x00070000, 307 0x9148, 0xffff0001, 0xff000000, 308 0x9190, 0x0fff0fff, 0x00090008, 309 0x91ac, 0x0fff0fff, 0x00090008, 310 0x3f94, 0xffff0000, 0xff000000, 311 0x914c, 0xffff0000, 0xff000000, 312 0x929c, 0x00000fff, 0x00000001, 313 0x55e4, 0xff607fff, 0xfc000100, 314 0x8a18, 0xff000fff, 0x00000100, 315 0x8b28, 0xff000fff, 0x00000100, 316 0x9144, 0xfffc0fff, 0x00000100, 317 0x6ed8, 0x00010101, 0x00010000, 318 0x9830, 0xffffffff, 0x00000000, 319 0x9834, 0xf00fffff, 0x00000400, 320 0x9838, 0xfffffffe, 0x00000000, 321 0xd0c0, 0xff000fff, 0x00000100, 322 0xd02c, 0xbfffff1f, 0x08421000, 323 0xd0b8, 0x73773777, 0x12010001, 324 0x5bb0, 0x000000f0, 0x00000070, 325 0x98f8, 0x73773777, 0x12010001, 326 0x98fc, 0xffffffff, 0x00000010, 327 0x9b7c, 0x00ff0000, 0x00fc0000, 328 0x8030, 0x00001f0f, 0x0000100a, 329 0x2f48, 0x73773777, 0x12010001, 330 0x2408, 0x00030000, 0x000c007f, 331 0x8a14, 0xf000003f, 0x00000007, 332 0x8b24, 0x3fff3fff, 0x00ff0fff, 333 0x8b10, 0x0000ff0f, 0x00000000, 334 0x28a4c, 0x07ffffff, 0x06000000, 335 0x4d8, 0x00000fff, 0x00000100, 336 0xa008, 0xffffffff, 0x00010000, 337 0x913c, 0xffff03ff, 0x01000100, 338 0x8c00, 0x000000ff, 0x00000003, 339 0x8c04, 0xf8ff00ff, 0x40600060, 340 0x8cf0, 0x1fff1fff, 0x08e00410, 341 0x28350, 0x00000f01, 0x00000000, 342 0x9508, 0xf700071f, 0x00000002, 343 0x960c, 0xffffffff, 0x54763210, 344 0x20ef8, 0x01ff01ff, 0x00000002, 345 0x20e98, 0xfffffbff, 0x00200000, 346 0x2015c, 0xffffffff, 0x00000f40, 347 0x88c4, 0x001f3ae3, 0x00000082, 348 0x8978, 0x3fffffff, 0x04050140, 349 0x88d4, 0x0000001f, 0x00000010, 350 0x8974, 0xffffffff, 0x00000000 351 }; 352 353 static const u32 scrapper_golden_registers[] = 354 { 355 0x690, 0x3fff3fff, 0x20c00033, 356 0x918c, 0x0fff0fff, 0x00010006, 357 0x918c, 0x0fff0fff, 0x00010006, 358 0x91a8, 0x0fff0fff, 0x00010006, 359 0x91a8, 0x0fff0fff, 0x00010006, 360 0x9150, 0xffffdfff, 0x6e944040, 361 0x9150, 0xffffdfff, 0x6e944040, 362 0x917c, 0x0fff0fff, 0x00030002, 363 0x917c, 0x0fff0fff, 0x00030002, 364 0x9198, 0x0fff0fff, 0x00030002, 365 0x9198, 0x0fff0fff, 0x00030002, 366 0x915c, 0x0fff0fff, 0x00010000, 367 0x915c, 0x0fff0fff, 0x00010000, 368 0x3f90, 0xffff0001, 0xff000000, 369 0x3f90, 0xffff0001, 0xff000000, 370 0x9178, 0x0fff0fff, 0x00070000, 371 0x9178, 0x0fff0fff, 0x00070000, 372 0x9194, 0x0fff0fff, 0x00070000, 373 0x9194, 0x0fff0fff, 0x00070000, 374 0x9148, 0xffff0001, 0xff000000, 375 0x9148, 0xffff0001, 0xff000000, 376 0x9190, 0x0fff0fff, 0x00090008, 377 0x9190, 0x0fff0fff, 0x00090008, 378 0x91ac, 0x0fff0fff, 0x00090008, 379 0x91ac, 0x0fff0fff, 0x00090008, 380 0x3f94, 0xffff0000, 0xff000000, 381 0x3f94, 0xffff0000, 0xff000000, 382 0x914c, 0xffff0000, 0xff000000, 383 0x914c, 0xffff0000, 0xff000000, 384 0x929c, 0x00000fff, 0x00000001, 385 0x929c, 0x00000fff, 0x00000001, 386 0x55e4, 0xff607fff, 0xfc000100, 387 0x8a18, 0xff000fff, 0x00000100, 388 0x8a18, 0xff000fff, 0x00000100, 389 0x8b28, 0xff000fff, 0x00000100, 390 0x8b28, 0xff000fff, 0x00000100, 391 0x9144, 0xfffc0fff, 0x00000100, 392 0x9144, 0xfffc0fff, 0x00000100, 393 0x6ed8, 0x00010101, 0x00010000, 394 0x9830, 0xffffffff, 0x00000000, 395 0x9830, 0xffffffff, 0x00000000, 396 0x9834, 0xf00fffff, 0x00000400, 397 0x9834, 0xf00fffff, 0x00000400, 398 0x9838, 0xfffffffe, 0x00000000, 399 0x9838, 0xfffffffe, 0x00000000, 400 0xd0c0, 0xff000fff, 0x00000100, 401 0xd02c, 0xbfffff1f, 0x08421000, 402 0xd02c, 0xbfffff1f, 0x08421000, 403 0xd0b8, 0x73773777, 0x12010001, 404 0xd0b8, 0x73773777, 0x12010001, 405 0x5bb0, 0x000000f0, 0x00000070, 406 0x98f8, 0x73773777, 0x12010001, 407 0x98f8, 0x73773777, 0x12010001, 408 0x98fc, 0xffffffff, 0x00000010, 409 0x98fc, 0xffffffff, 0x00000010, 410 0x9b7c, 0x00ff0000, 0x00fc0000, 411 0x9b7c, 0x00ff0000, 0x00fc0000, 412 0x8030, 0x00001f0f, 0x0000100a, 413 0x8030, 0x00001f0f, 0x0000100a, 414 0x2f48, 0x73773777, 0x12010001, 415 0x2f48, 0x73773777, 0x12010001, 416 0x2408, 0x00030000, 0x000c007f, 417 0x8a14, 0xf000003f, 0x00000007, 418 0x8a14, 0xf000003f, 0x00000007, 419 0x8b24, 0x3fff3fff, 0x00ff0fff, 420 0x8b24, 0x3fff3fff, 0x00ff0fff, 421 0x8b10, 0x0000ff0f, 0x00000000, 422 0x8b10, 0x0000ff0f, 0x00000000, 423 0x28a4c, 0x07ffffff, 0x06000000, 424 0x28a4c, 0x07ffffff, 0x06000000, 425 0x4d8, 0x00000fff, 0x00000100, 426 0x4d8, 0x00000fff, 0x00000100, 427 0xa008, 0xffffffff, 0x00010000, 428 0xa008, 0xffffffff, 0x00010000, 429 0x913c, 0xffff03ff, 0x01000100, 430 0x913c, 0xffff03ff, 0x01000100, 431 0x90e8, 0x001fffff, 0x010400c0, 432 0x8c00, 0x000000ff, 0x00000003, 433 0x8c00, 0x000000ff, 0x00000003, 434 0x8c04, 0xf8ff00ff, 0x40600060, 435 0x8c04, 0xf8ff00ff, 0x40600060, 436 0x8c30, 0x0000000f, 0x00040005, 437 0x8cf0, 0x1fff1fff, 0x08e00410, 438 0x8cf0, 0x1fff1fff, 0x08e00410, 439 0x900c, 0x00ffffff, 0x0017071f, 440 0x28350, 0x00000f01, 0x00000000, 441 0x28350, 0x00000f01, 0x00000000, 442 0x9508, 0xf700071f, 0x00000002, 443 0x9508, 0xf700071f, 0x00000002, 444 0x9688, 0x00300000, 0x0017000f, 445 0x960c, 0xffffffff, 0x54763210, 446 0x960c, 0xffffffff, 0x54763210, 447 0x20ef8, 0x01ff01ff, 0x00000002, 448 0x20e98, 0xfffffbff, 0x00200000, 449 0x2015c, 0xffffffff, 0x00000f40, 450 0x88c4, 0x001f3ae3, 0x00000082, 451 0x88c4, 0x001f3ae3, 0x00000082, 452 0x8978, 0x3fffffff, 0x04050140, 453 0x8978, 0x3fffffff, 0x04050140, 454 0x88d4, 0x0000001f, 0x00000010, 455 0x88d4, 0x0000001f, 0x00000010, 456 0x8974, 0xffffffff, 0x00000000, 457 0x8974, 0xffffffff, 0x00000000 458 }; 459 460 static void ni_init_golden_registers(struct radeon_device *rdev) 461 { 462 switch (rdev->family) { 463 case CHIP_CAYMAN: 464 radeon_program_register_sequence(rdev, 465 cayman_golden_registers, 466 (const u32)ARRAY_SIZE(cayman_golden_registers)); 467 radeon_program_register_sequence(rdev, 468 cayman_golden_registers2, 469 (const u32)ARRAY_SIZE(cayman_golden_registers2)); 470 break; 471 case CHIP_ARUBA: 472 if ((rdev->pdev->device == 0x9900) || 473 (rdev->pdev->device == 0x9901) || 474 (rdev->pdev->device == 0x9903) || 475 (rdev->pdev->device == 0x9904) || 476 (rdev->pdev->device == 0x9905) || 477 (rdev->pdev->device == 0x9906) || 478 (rdev->pdev->device == 0x9907) || 479 (rdev->pdev->device == 0x9908) || 480 (rdev->pdev->device == 0x9909) || 481 (rdev->pdev->device == 0x990A) || 482 (rdev->pdev->device == 0x990B) || 483 (rdev->pdev->device == 0x990C) || 484 (rdev->pdev->device == 0x990D) || 485 (rdev->pdev->device == 0x990E) || 486 (rdev->pdev->device == 0x990F) || 487 (rdev->pdev->device == 0x9910) || 488 (rdev->pdev->device == 0x9913) || 489 (rdev->pdev->device == 0x9917) || 490 (rdev->pdev->device == 0x9918)) { 491 radeon_program_register_sequence(rdev, 492 dvst_golden_registers, 493 (const u32)ARRAY_SIZE(dvst_golden_registers)); 494 radeon_program_register_sequence(rdev, 495 dvst_golden_registers2, 496 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 497 } else { 498 radeon_program_register_sequence(rdev, 499 scrapper_golden_registers, 500 (const u32)ARRAY_SIZE(scrapper_golden_registers)); 501 radeon_program_register_sequence(rdev, 502 dvst_golden_registers2, 503 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 504 } 505 break; 506 default: 507 break; 508 } 509 } 510 511 #define BTC_IO_MC_REGS_SIZE 29 512 513 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 514 {0x00000077, 0xff010100}, 515 {0x00000078, 0x00000000}, 516 {0x00000079, 0x00001434}, 517 {0x0000007a, 0xcc08ec08}, 518 {0x0000007b, 0x00040000}, 519 {0x0000007c, 0x000080c0}, 520 {0x0000007d, 0x09000000}, 521 {0x0000007e, 0x00210404}, 522 {0x00000081, 0x08a8e800}, 523 {0x00000082, 0x00030444}, 524 {0x00000083, 0x00000000}, 525 {0x00000085, 0x00000001}, 526 {0x00000086, 0x00000002}, 527 {0x00000087, 0x48490000}, 528 {0x00000088, 0x20244647}, 529 {0x00000089, 0x00000005}, 530 {0x0000008b, 0x66030000}, 531 {0x0000008c, 0x00006603}, 532 {0x0000008d, 0x00000100}, 533 {0x0000008f, 0x00001c0a}, 534 {0x00000090, 0xff000001}, 535 {0x00000094, 0x00101101}, 536 {0x00000095, 0x00000fff}, 537 {0x00000096, 0x00116fff}, 538 {0x00000097, 0x60010000}, 539 {0x00000098, 0x10010000}, 540 {0x00000099, 0x00006000}, 541 {0x0000009a, 0x00001000}, 542 {0x0000009f, 0x00946a00} 543 }; 544 545 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 546 {0x00000077, 0xff010100}, 547 {0x00000078, 0x00000000}, 548 {0x00000079, 0x00001434}, 549 {0x0000007a, 0xcc08ec08}, 550 {0x0000007b, 0x00040000}, 551 {0x0000007c, 0x000080c0}, 552 {0x0000007d, 0x09000000}, 553 {0x0000007e, 0x00210404}, 554 {0x00000081, 0x08a8e800}, 555 {0x00000082, 0x00030444}, 556 {0x00000083, 0x00000000}, 557 {0x00000085, 0x00000001}, 558 {0x00000086, 0x00000002}, 559 {0x00000087, 0x48490000}, 560 {0x00000088, 0x20244647}, 561 {0x00000089, 0x00000005}, 562 {0x0000008b, 0x66030000}, 563 {0x0000008c, 0x00006603}, 564 {0x0000008d, 0x00000100}, 565 {0x0000008f, 0x00001c0a}, 566 {0x00000090, 0xff000001}, 567 {0x00000094, 0x00101101}, 568 {0x00000095, 0x00000fff}, 569 {0x00000096, 0x00116fff}, 570 {0x00000097, 0x60010000}, 571 {0x00000098, 0x10010000}, 572 {0x00000099, 0x00006000}, 573 {0x0000009a, 0x00001000}, 574 {0x0000009f, 0x00936a00} 575 }; 576 577 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 578 {0x00000077, 0xff010100}, 579 {0x00000078, 0x00000000}, 580 {0x00000079, 0x00001434}, 581 {0x0000007a, 0xcc08ec08}, 582 {0x0000007b, 0x00040000}, 583 {0x0000007c, 0x000080c0}, 584 {0x0000007d, 0x09000000}, 585 {0x0000007e, 0x00210404}, 586 {0x00000081, 0x08a8e800}, 587 {0x00000082, 0x00030444}, 588 {0x00000083, 0x00000000}, 589 {0x00000085, 0x00000001}, 590 {0x00000086, 0x00000002}, 591 {0x00000087, 0x48490000}, 592 {0x00000088, 0x20244647}, 593 {0x00000089, 0x00000005}, 594 {0x0000008b, 0x66030000}, 595 {0x0000008c, 0x00006603}, 596 {0x0000008d, 0x00000100}, 597 {0x0000008f, 0x00001c0a}, 598 {0x00000090, 0xff000001}, 599 {0x00000094, 0x00101101}, 600 {0x00000095, 0x00000fff}, 601 {0x00000096, 0x00116fff}, 602 {0x00000097, 0x60010000}, 603 {0x00000098, 0x10010000}, 604 {0x00000099, 0x00006000}, 605 {0x0000009a, 0x00001000}, 606 {0x0000009f, 0x00916a00} 607 }; 608 609 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 610 {0x00000077, 0xff010100}, 611 {0x00000078, 0x00000000}, 612 {0x00000079, 0x00001434}, 613 {0x0000007a, 0xcc08ec08}, 614 {0x0000007b, 0x00040000}, 615 {0x0000007c, 0x000080c0}, 616 {0x0000007d, 0x09000000}, 617 {0x0000007e, 0x00210404}, 618 {0x00000081, 0x08a8e800}, 619 {0x00000082, 0x00030444}, 620 {0x00000083, 0x00000000}, 621 {0x00000085, 0x00000001}, 622 {0x00000086, 0x00000002}, 623 {0x00000087, 0x48490000}, 624 {0x00000088, 0x20244647}, 625 {0x00000089, 0x00000005}, 626 {0x0000008b, 0x66030000}, 627 {0x0000008c, 0x00006603}, 628 {0x0000008d, 0x00000100}, 629 {0x0000008f, 0x00001c0a}, 630 {0x00000090, 0xff000001}, 631 {0x00000094, 0x00101101}, 632 {0x00000095, 0x00000fff}, 633 {0x00000096, 0x00116fff}, 634 {0x00000097, 0x60010000}, 635 {0x00000098, 0x10010000}, 636 {0x00000099, 0x00006000}, 637 {0x0000009a, 0x00001000}, 638 {0x0000009f, 0x00976b00} 639 }; 640 641 int ni_mc_load_microcode(struct radeon_device *rdev) 642 { 643 const __be32 *fw_data; 644 u32 mem_type, running, blackout = 0; 645 const u32 *io_mc_regs; 646 int i, ucode_size, regs_size; 647 648 if (!rdev->mc_fw) 649 return -EINVAL; 650 651 switch (rdev->family) { 652 case CHIP_BARTS: 653 io_mc_regs = &barts_io_mc_regs[0][0]; 654 ucode_size = BTC_MC_UCODE_SIZE; 655 regs_size = BTC_IO_MC_REGS_SIZE; 656 break; 657 case CHIP_TURKS: 658 io_mc_regs = &turks_io_mc_regs[0][0]; 659 ucode_size = BTC_MC_UCODE_SIZE; 660 regs_size = BTC_IO_MC_REGS_SIZE; 661 break; 662 case CHIP_CAICOS: 663 default: 664 io_mc_regs = &caicos_io_mc_regs[0][0]; 665 ucode_size = BTC_MC_UCODE_SIZE; 666 regs_size = BTC_IO_MC_REGS_SIZE; 667 break; 668 case CHIP_CAYMAN: 669 io_mc_regs = &cayman_io_mc_regs[0][0]; 670 ucode_size = CAYMAN_MC_UCODE_SIZE; 671 regs_size = BTC_IO_MC_REGS_SIZE; 672 break; 673 } 674 675 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; 676 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 677 678 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { 679 if (running) { 680 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 681 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); 682 } 683 684 /* reset the engine and set to writable */ 685 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 686 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 687 688 /* load mc io regs */ 689 for (i = 0; i < regs_size; i++) { 690 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 691 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 692 } 693 /* load the MC ucode */ 694 fw_data = (const __be32 *)rdev->mc_fw->data; 695 for (i = 0; i < ucode_size; i++) 696 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 697 698 /* put the engine back into the active state */ 699 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 700 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 701 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 702 703 /* wait for training to complete */ 704 for (i = 0; i < rdev->usec_timeout; i++) { 705 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) 706 break; 707 udelay(1); 708 } 709 710 if (running) 711 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 712 } 713 714 return 0; 715 } 716 717 int ni_init_microcode(struct radeon_device *rdev) 718 { 719 const char *chip_name; 720 const char *rlc_chip_name; 721 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; 722 size_t smc_req_size = 0; 723 char fw_name[30]; 724 int err; 725 726 DRM_DEBUG("\n"); 727 728 switch (rdev->family) { 729 case CHIP_BARTS: 730 chip_name = "BARTS"; 731 rlc_chip_name = "BTC"; 732 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 733 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 734 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 735 mc_req_size = BTC_MC_UCODE_SIZE * 4; 736 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4); 737 break; 738 case CHIP_TURKS: 739 chip_name = "TURKS"; 740 rlc_chip_name = "BTC"; 741 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 742 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 743 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 744 mc_req_size = BTC_MC_UCODE_SIZE * 4; 745 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4); 746 break; 747 case CHIP_CAICOS: 748 chip_name = "CAICOS"; 749 rlc_chip_name = "BTC"; 750 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 751 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 752 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 753 mc_req_size = BTC_MC_UCODE_SIZE * 4; 754 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4); 755 break; 756 case CHIP_CAYMAN: 757 chip_name = "CAYMAN"; 758 rlc_chip_name = "CAYMAN"; 759 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 760 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 761 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; 762 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; 763 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4); 764 break; 765 case CHIP_ARUBA: 766 chip_name = "ARUBA"; 767 rlc_chip_name = "ARUBA"; 768 /* pfp/me same size as CAYMAN */ 769 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 770 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 771 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; 772 mc_req_size = 0; 773 break; 774 default: BUG(); 775 } 776 777 DRM_INFO("Loading %s Microcode\n", chip_name); 778 779 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 780 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 781 if (err) 782 goto out; 783 if (rdev->pfp_fw->size != pfp_req_size) { 784 printk(KERN_ERR 785 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 786 rdev->pfp_fw->size, fw_name); 787 err = -EINVAL; 788 goto out; 789 } 790 791 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 792 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 793 if (err) 794 goto out; 795 if (rdev->me_fw->size != me_req_size) { 796 printk(KERN_ERR 797 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 798 rdev->me_fw->size, fw_name); 799 err = -EINVAL; 800 } 801 802 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 803 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 804 if (err) 805 goto out; 806 if (rdev->rlc_fw->size != rlc_req_size) { 807 printk(KERN_ERR 808 "ni_rlc: Bogus length %zu in firmware \"%s\"\n", 809 rdev->rlc_fw->size, fw_name); 810 err = -EINVAL; 811 } 812 813 /* no MC ucode on TN */ 814 if (!(rdev->flags & RADEON_IS_IGP)) { 815 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 816 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 817 if (err) 818 goto out; 819 if (rdev->mc_fw->size != mc_req_size) { 820 printk(KERN_ERR 821 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 822 rdev->mc_fw->size, fw_name); 823 err = -EINVAL; 824 } 825 } 826 827 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { 828 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 829 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 830 if (err) { 831 printk(KERN_ERR 832 "smc: error loading firmware \"%s\"\n", 833 fw_name); 834 release_firmware(rdev->smc_fw); 835 rdev->smc_fw = NULL; 836 err = 0; 837 } else if (rdev->smc_fw->size != smc_req_size) { 838 printk(KERN_ERR 839 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 840 rdev->mc_fw->size, fw_name); 841 err = -EINVAL; 842 } 843 } 844 845 out: 846 if (err) { 847 if (err != -EINVAL) 848 printk(KERN_ERR 849 "ni_cp: Failed to load firmware \"%s\"\n", 850 fw_name); 851 release_firmware(rdev->pfp_fw); 852 rdev->pfp_fw = NULL; 853 release_firmware(rdev->me_fw); 854 rdev->me_fw = NULL; 855 release_firmware(rdev->rlc_fw); 856 rdev->rlc_fw = NULL; 857 release_firmware(rdev->mc_fw); 858 rdev->mc_fw = NULL; 859 } 860 return err; 861 } 862 863 /** 864 * cayman_get_allowed_info_register - fetch the register for the info ioctl 865 * 866 * @rdev: radeon_device pointer 867 * @reg: register offset in bytes 868 * @val: register value 869 * 870 * Returns 0 for success or -EINVAL for an invalid register 871 * 872 */ 873 int cayman_get_allowed_info_register(struct radeon_device *rdev, 874 u32 reg, u32 *val) 875 { 876 switch (reg) { 877 case GRBM_STATUS: 878 case GRBM_STATUS_SE0: 879 case GRBM_STATUS_SE1: 880 case SRBM_STATUS: 881 case SRBM_STATUS2: 882 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): 883 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): 884 case UVD_STATUS: 885 *val = RREG32(reg); 886 return 0; 887 default: 888 return -EINVAL; 889 } 890 } 891 892 int tn_get_temp(struct radeon_device *rdev) 893 { 894 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; 895 int actual_temp = (temp / 8) - 49; 896 897 return actual_temp * 1000; 898 } 899 900 /* 901 * Core functions 902 */ 903 static void cayman_gpu_init(struct radeon_device *rdev) 904 { 905 u32 gb_addr_config = 0; 906 u32 mc_shared_chmap __unused, mc_arb_ramcfg; 907 u32 cgts_tcc_disable; 908 u32 sx_debug_1; 909 u32 smx_dc_ctl0; 910 u32 cgts_sm_ctrl_reg; 911 u32 hdp_host_path_cntl; 912 u32 tmp; 913 u32 disabled_rb_mask; 914 int i, j; 915 916 switch (rdev->family) { 917 case CHIP_CAYMAN: 918 rdev->config.cayman.max_shader_engines = 2; 919 rdev->config.cayman.max_pipes_per_simd = 4; 920 rdev->config.cayman.max_tile_pipes = 8; 921 rdev->config.cayman.max_simds_per_se = 12; 922 rdev->config.cayman.max_backends_per_se = 4; 923 rdev->config.cayman.max_texture_channel_caches = 8; 924 rdev->config.cayman.max_gprs = 256; 925 rdev->config.cayman.max_threads = 256; 926 rdev->config.cayman.max_gs_threads = 32; 927 rdev->config.cayman.max_stack_entries = 512; 928 rdev->config.cayman.sx_num_of_sets = 8; 929 rdev->config.cayman.sx_max_export_size = 256; 930 rdev->config.cayman.sx_max_export_pos_size = 64; 931 rdev->config.cayman.sx_max_export_smx_size = 192; 932 rdev->config.cayman.max_hw_contexts = 8; 933 rdev->config.cayman.sq_num_cf_insts = 2; 934 935 rdev->config.cayman.sc_prim_fifo_size = 0x100; 936 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 937 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 938 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; 939 break; 940 case CHIP_ARUBA: 941 default: 942 rdev->config.cayman.max_shader_engines = 1; 943 rdev->config.cayman.max_pipes_per_simd = 4; 944 rdev->config.cayman.max_tile_pipes = 2; 945 if ((rdev->pdev->device == 0x9900) || 946 (rdev->pdev->device == 0x9901) || 947 (rdev->pdev->device == 0x9905) || 948 (rdev->pdev->device == 0x9906) || 949 (rdev->pdev->device == 0x9907) || 950 (rdev->pdev->device == 0x9908) || 951 (rdev->pdev->device == 0x9909) || 952 (rdev->pdev->device == 0x990B) || 953 (rdev->pdev->device == 0x990C) || 954 (rdev->pdev->device == 0x990F) || 955 (rdev->pdev->device == 0x9910) || 956 (rdev->pdev->device == 0x9917) || 957 (rdev->pdev->device == 0x9999) || 958 (rdev->pdev->device == 0x999C)) { 959 rdev->config.cayman.max_simds_per_se = 6; 960 rdev->config.cayman.max_backends_per_se = 2; 961 rdev->config.cayman.max_hw_contexts = 8; 962 rdev->config.cayman.sx_max_export_size = 256; 963 rdev->config.cayman.sx_max_export_pos_size = 64; 964 rdev->config.cayman.sx_max_export_smx_size = 192; 965 } else if ((rdev->pdev->device == 0x9903) || 966 (rdev->pdev->device == 0x9904) || 967 (rdev->pdev->device == 0x990A) || 968 (rdev->pdev->device == 0x990D) || 969 (rdev->pdev->device == 0x990E) || 970 (rdev->pdev->device == 0x9913) || 971 (rdev->pdev->device == 0x9918) || 972 (rdev->pdev->device == 0x999D)) { 973 rdev->config.cayman.max_simds_per_se = 4; 974 rdev->config.cayman.max_backends_per_se = 2; 975 rdev->config.cayman.max_hw_contexts = 8; 976 rdev->config.cayman.sx_max_export_size = 256; 977 rdev->config.cayman.sx_max_export_pos_size = 64; 978 rdev->config.cayman.sx_max_export_smx_size = 192; 979 } else if ((rdev->pdev->device == 0x9919) || 980 (rdev->pdev->device == 0x9990) || 981 (rdev->pdev->device == 0x9991) || 982 (rdev->pdev->device == 0x9994) || 983 (rdev->pdev->device == 0x9995) || 984 (rdev->pdev->device == 0x9996) || 985 (rdev->pdev->device == 0x999A) || 986 (rdev->pdev->device == 0x99A0)) { 987 rdev->config.cayman.max_simds_per_se = 3; 988 rdev->config.cayman.max_backends_per_se = 1; 989 rdev->config.cayman.max_hw_contexts = 4; 990 rdev->config.cayman.sx_max_export_size = 128; 991 rdev->config.cayman.sx_max_export_pos_size = 32; 992 rdev->config.cayman.sx_max_export_smx_size = 96; 993 } else { 994 rdev->config.cayman.max_simds_per_se = 2; 995 rdev->config.cayman.max_backends_per_se = 1; 996 rdev->config.cayman.max_hw_contexts = 4; 997 rdev->config.cayman.sx_max_export_size = 128; 998 rdev->config.cayman.sx_max_export_pos_size = 32; 999 rdev->config.cayman.sx_max_export_smx_size = 96; 1000 } 1001 rdev->config.cayman.max_texture_channel_caches = 2; 1002 rdev->config.cayman.max_gprs = 256; 1003 rdev->config.cayman.max_threads = 256; 1004 rdev->config.cayman.max_gs_threads = 32; 1005 rdev->config.cayman.max_stack_entries = 512; 1006 rdev->config.cayman.sx_num_of_sets = 8; 1007 rdev->config.cayman.sq_num_cf_insts = 2; 1008 1009 rdev->config.cayman.sc_prim_fifo_size = 0x40; 1010 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 1011 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 1012 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; 1013 break; 1014 } 1015 1016 /* Initialize HDP */ 1017 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1018 WREG32((0x2c14 + j), 0x00000000); 1019 WREG32((0x2c18 + j), 0x00000000); 1020 WREG32((0x2c1c + j), 0x00000000); 1021 WREG32((0x2c20 + j), 0x00000000); 1022 WREG32((0x2c24 + j), 0x00000000); 1023 } 1024 1025 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1026 WREG32(SRBM_INT_CNTL, 0x1); 1027 WREG32(SRBM_INT_ACK, 0x1); 1028 1029 evergreen_fix_pci_max_read_req_size(rdev); 1030 1031 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1032 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1033 1034 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1035 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1036 if (rdev->config.cayman.mem_row_size_in_kb > 4) 1037 rdev->config.cayman.mem_row_size_in_kb = 4; 1038 /* XXX use MC settings? */ 1039 rdev->config.cayman.shader_engine_tile_size = 32; 1040 rdev->config.cayman.num_gpus = 1; 1041 rdev->config.cayman.multi_gpu_tile_size = 64; 1042 1043 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 1044 rdev->config.cayman.num_tile_pipes = (1 << tmp); 1045 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 1046 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 1047 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; 1048 rdev->config.cayman.num_shader_engines = tmp + 1; 1049 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; 1050 rdev->config.cayman.num_gpus = tmp + 1; 1051 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; 1052 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; 1053 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 1054 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 1055 1056 1057 /* setup tiling info dword. gb_addr_config is not adequate since it does 1058 * not have bank info, so create a custom tiling dword. 1059 * bits 3:0 num_pipes 1060 * bits 7:4 num_banks 1061 * bits 11:8 group_size 1062 * bits 15:12 row_size 1063 */ 1064 rdev->config.cayman.tile_config = 0; 1065 switch (rdev->config.cayman.num_tile_pipes) { 1066 case 1: 1067 default: 1068 rdev->config.cayman.tile_config |= (0 << 0); 1069 break; 1070 case 2: 1071 rdev->config.cayman.tile_config |= (1 << 0); 1072 break; 1073 case 4: 1074 rdev->config.cayman.tile_config |= (2 << 0); 1075 break; 1076 case 8: 1077 rdev->config.cayman.tile_config |= (3 << 0); 1078 break; 1079 } 1080 1081 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 1082 if (rdev->flags & RADEON_IS_IGP) 1083 rdev->config.cayman.tile_config |= 1 << 4; 1084 else { 1085 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1086 case 0: /* four banks */ 1087 rdev->config.cayman.tile_config |= 0 << 4; 1088 break; 1089 case 1: /* eight banks */ 1090 rdev->config.cayman.tile_config |= 1 << 4; 1091 break; 1092 case 2: /* sixteen banks */ 1093 default: 1094 rdev->config.cayman.tile_config |= 2 << 4; 1095 break; 1096 } 1097 } 1098 rdev->config.cayman.tile_config |= 1099 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1100 rdev->config.cayman.tile_config |= 1101 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1102 1103 tmp = 0; 1104 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { 1105 u32 rb_disable_bitmap; 1106 1107 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1108 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1109 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 1110 tmp <<= 4; 1111 tmp |= rb_disable_bitmap; 1112 } 1113 /* enabled rb are just the one not disabled :) */ 1114 disabled_rb_mask = tmp; 1115 tmp = 0; 1116 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1117 tmp |= (1 << i); 1118 /* if all the backends are disabled, fix it up here */ 1119 if ((disabled_rb_mask & tmp) == tmp) { 1120 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1121 disabled_rb_mask &= ~(1 << i); 1122 } 1123 1124 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { 1125 u32 simd_disable_bitmap; 1126 1127 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1128 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1129 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; 1130 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; 1131 tmp <<= 16; 1132 tmp |= simd_disable_bitmap; 1133 } 1134 rdev->config.cayman.active_simds = hweight32(~tmp); 1135 1136 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1137 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1138 1139 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1140 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1141 if (ASIC_IS_DCE6(rdev)) 1142 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1143 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1144 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1145 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1146 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 1147 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1148 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1149 1150 if ((rdev->config.cayman.max_backends_per_se == 1) && 1151 (rdev->flags & RADEON_IS_IGP)) { 1152 if ((disabled_rb_mask & 3) == 2) { 1153 /* RB1 disabled, RB0 enabled */ 1154 tmp = 0x00000000; 1155 } else { 1156 /* RB0 disabled, RB1 enabled */ 1157 tmp = 0x11111111; 1158 } 1159 } else { 1160 tmp = gb_addr_config & NUM_PIPES_MASK; 1161 tmp = r6xx_remap_render_backend(rdev, tmp, 1162 rdev->config.cayman.max_backends_per_se * 1163 rdev->config.cayman.max_shader_engines, 1164 CAYMAN_MAX_BACKENDS, disabled_rb_mask); 1165 } 1166 WREG32(GB_BACKEND_MAP, tmp); 1167 1168 cgts_tcc_disable = 0xffff0000; 1169 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 1170 cgts_tcc_disable &= ~(1 << (16 + i)); 1171 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 1172 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 1173 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 1174 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 1175 1176 /* reprogram the shader complex */ 1177 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); 1178 for (i = 0; i < 16; i++) 1179 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); 1180 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 1181 1182 /* set HW defaults for 3D engine */ 1183 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1184 1185 sx_debug_1 = RREG32(SX_DEBUG_1); 1186 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1187 WREG32(SX_DEBUG_1, sx_debug_1); 1188 1189 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1190 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 1191 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); 1192 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1193 1194 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); 1195 1196 /* need to be explicitly zero-ed */ 1197 WREG32(VGT_OFFCHIP_LDS_BASE, 0); 1198 WREG32(SQ_LSTMP_RING_BASE, 0); 1199 WREG32(SQ_HSTMP_RING_BASE, 0); 1200 WREG32(SQ_ESTMP_RING_BASE, 0); 1201 WREG32(SQ_GSTMP_RING_BASE, 0); 1202 WREG32(SQ_VSTMP_RING_BASE, 0); 1203 WREG32(SQ_PSTMP_RING_BASE, 0); 1204 1205 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); 1206 1207 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | 1208 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | 1209 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); 1210 1211 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | 1212 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | 1213 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); 1214 1215 1216 WREG32(VGT_NUM_INSTANCES, 1); 1217 1218 WREG32(CP_PERFMON_CNTL, 0); 1219 1220 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | 1221 FETCH_FIFO_HIWATER(0x4) | 1222 DONE_FIFO_HIWATER(0xe0) | 1223 ALU_UPDATE_FIFO_HIWATER(0x8))); 1224 1225 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); 1226 WREG32(SQ_CONFIG, (VC_ENABLE | 1227 EXPORT_SRC_C | 1228 GFX_PRIO(0) | 1229 CS1_PRIO(0) | 1230 CS2_PRIO(1))); 1231 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); 1232 1233 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1234 FORCE_EOV_MAX_REZ_CNT(255))); 1235 1236 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1237 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1238 1239 WREG32(VGT_GS_VERTEX_REUSE, 16); 1240 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1241 1242 WREG32(CB_PERF_CTR0_SEL_0, 0); 1243 WREG32(CB_PERF_CTR0_SEL_1, 0); 1244 WREG32(CB_PERF_CTR1_SEL_0, 0); 1245 WREG32(CB_PERF_CTR1_SEL_1, 0); 1246 WREG32(CB_PERF_CTR2_SEL_0, 0); 1247 WREG32(CB_PERF_CTR2_SEL_1, 0); 1248 WREG32(CB_PERF_CTR3_SEL_0, 0); 1249 WREG32(CB_PERF_CTR3_SEL_1, 0); 1250 1251 tmp = RREG32(HDP_MISC_CNTL); 1252 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1253 WREG32(HDP_MISC_CNTL, tmp); 1254 1255 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1256 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1257 1258 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1259 1260 udelay(50); 1261 1262 /* set clockgating golden values on TN */ 1263 if (rdev->family == CHIP_ARUBA) { 1264 tmp = RREG32_CG(CG_CGTT_LOCAL_0); 1265 tmp &= ~0x00380000; 1266 WREG32_CG(CG_CGTT_LOCAL_0, tmp); 1267 tmp = RREG32_CG(CG_CGTT_LOCAL_1); 1268 tmp &= ~0x0e000000; 1269 WREG32_CG(CG_CGTT_LOCAL_1, tmp); 1270 } 1271 } 1272 1273 /* 1274 * GART 1275 */ 1276 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) 1277 { 1278 /* flush hdp cache */ 1279 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1280 1281 /* bits 0-7 are the VM contexts0-7 */ 1282 WREG32(VM_INVALIDATE_REQUEST, 1); 1283 } 1284 1285 static int cayman_pcie_gart_enable(struct radeon_device *rdev) 1286 { 1287 int i, r; 1288 1289 if (rdev->gart.robj == NULL) { 1290 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1291 return -EINVAL; 1292 } 1293 r = radeon_gart_table_vram_pin(rdev); 1294 if (r) 1295 return r; 1296 /* Setup TLB control */ 1297 WREG32(MC_VM_MX_L1_TLB_CNTL, 1298 (0xA << 7) | 1299 ENABLE_L1_TLB | 1300 ENABLE_L1_FRAGMENT_PROCESSING | 1301 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1302 ENABLE_ADVANCED_DRIVER_MODEL | 1303 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1304 /* Setup L2 cache */ 1305 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 1306 ENABLE_L2_FRAGMENT_PROCESSING | 1307 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1308 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1309 EFFECTIVE_L2_QUEUE_SIZE(7) | 1310 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1311 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 1312 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1313 BANK_SELECT(6) | 1314 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1315 /* setup context0 */ 1316 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1317 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1318 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1319 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1320 (u32)(rdev->dummy_page.addr >> 12)); 1321 WREG32(VM_CONTEXT0_CNTL2, 0); 1322 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1323 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1324 1325 WREG32(0x15D4, 0); 1326 WREG32(0x15D8, 0); 1327 WREG32(0x15DC, 0); 1328 1329 /* empty context1-7 */ 1330 /* Assign the pt base to something valid for now; the pts used for 1331 * the VMs are determined by the application and setup and assigned 1332 * on the fly in the vm part of radeon_gart.c 1333 */ 1334 for (i = 1; i < 8; i++) { 1335 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 1336 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 1337 rdev->vm_manager.max_pfn - 1); 1338 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 1339 rdev->vm_manager.saved_table_addr[i]); 1340 } 1341 1342 /* enable context1-7 */ 1343 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 1344 (u32)(rdev->dummy_page.addr >> 12)); 1345 WREG32(VM_CONTEXT1_CNTL2, 4); 1346 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 1347 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | 1348 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1349 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1350 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1351 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1352 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 1353 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 1354 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 1355 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 1356 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 1357 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 1358 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1359 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 1360 1361 cayman_pcie_gart_tlb_flush(rdev); 1362 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1363 (unsigned)(rdev->mc.gtt_size >> 20), 1364 (unsigned long long)rdev->gart.table_addr); 1365 rdev->gart.ready = true; 1366 return 0; 1367 } 1368 1369 static void cayman_pcie_gart_disable(struct radeon_device *rdev) 1370 { 1371 unsigned i; 1372 1373 for (i = 1; i < 8; ++i) { 1374 rdev->vm_manager.saved_table_addr[i] = RREG32( 1375 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); 1376 } 1377 1378 /* Disable all tables */ 1379 WREG32(VM_CONTEXT0_CNTL, 0); 1380 WREG32(VM_CONTEXT1_CNTL, 0); 1381 /* Setup TLB control */ 1382 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | 1383 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1384 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1385 /* Setup L2 cache */ 1386 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1387 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1388 EFFECTIVE_L2_QUEUE_SIZE(7) | 1389 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1390 WREG32(VM_L2_CNTL2, 0); 1391 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1392 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1393 radeon_gart_table_vram_unpin(rdev); 1394 } 1395 1396 static void cayman_pcie_gart_fini(struct radeon_device *rdev) 1397 { 1398 cayman_pcie_gart_disable(rdev); 1399 radeon_gart_table_vram_free(rdev); 1400 radeon_gart_fini(rdev); 1401 } 1402 1403 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 1404 int ring, u32 cp_int_cntl) 1405 { 1406 WREG32(SRBM_GFX_CNTL, RINGID(ring)); 1407 WREG32(CP_INT_CNTL, cp_int_cntl); 1408 } 1409 1410 /* 1411 * CP. 1412 */ 1413 void cayman_fence_ring_emit(struct radeon_device *rdev, 1414 struct radeon_fence *fence) 1415 { 1416 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1417 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1418 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1419 PACKET3_SH_ACTION_ENA; 1420 1421 /* flush read cache over gart for this vmid */ 1422 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1423 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1424 radeon_ring_write(ring, 0xFFFFFFFF); 1425 radeon_ring_write(ring, 0); 1426 radeon_ring_write(ring, 10); /* poll interval */ 1427 /* EVENT_WRITE_EOP - flush caches, send int */ 1428 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1429 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 1430 radeon_ring_write(ring, lower_32_bits(addr)); 1431 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1432 radeon_ring_write(ring, fence->seq); 1433 radeon_ring_write(ring, 0); 1434 } 1435 1436 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1437 { 1438 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1439 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; 1440 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1441 PACKET3_SH_ACTION_ENA; 1442 1443 /* set to DX10/11 mode */ 1444 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1445 radeon_ring_write(ring, 1); 1446 1447 if (ring->rptr_save_reg) { 1448 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; 1449 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1450 radeon_ring_write(ring, ((ring->rptr_save_reg - 1451 PACKET3_SET_CONFIG_REG_START) >> 2)); 1452 radeon_ring_write(ring, next_rptr); 1453 } 1454 1455 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1456 radeon_ring_write(ring, 1457 #ifdef __BIG_ENDIAN 1458 (2 << 0) | 1459 #endif 1460 (ib->gpu_addr & 0xFFFFFFFC)); 1461 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1462 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); 1463 1464 /* flush read cache over gart for this vmid */ 1465 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1466 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1467 radeon_ring_write(ring, 0xFFFFFFFF); 1468 radeon_ring_write(ring, 0); 1469 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ 1470 } 1471 1472 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1473 { 1474 if (enable) 1475 WREG32(CP_ME_CNTL, 0); 1476 else { 1477 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1478 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1479 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1480 WREG32(SCRATCH_UMSK, 0); 1481 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1482 } 1483 } 1484 1485 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 1486 struct radeon_ring *ring) 1487 { 1488 u32 rptr; 1489 1490 if (rdev->wb.enabled) 1491 rptr = rdev->wb.wb[ring->rptr_offs/4]; 1492 else { 1493 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1494 rptr = RREG32(CP_RB0_RPTR); 1495 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1496 rptr = RREG32(CP_RB1_RPTR); 1497 else 1498 rptr = RREG32(CP_RB2_RPTR); 1499 } 1500 1501 return rptr; 1502 } 1503 1504 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 1505 struct radeon_ring *ring) 1506 { 1507 u32 wptr; 1508 1509 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1510 wptr = RREG32(CP_RB0_WPTR); 1511 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1512 wptr = RREG32(CP_RB1_WPTR); 1513 else 1514 wptr = RREG32(CP_RB2_WPTR); 1515 1516 return wptr; 1517 } 1518 1519 void cayman_gfx_set_wptr(struct radeon_device *rdev, 1520 struct radeon_ring *ring) 1521 { 1522 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { 1523 WREG32(CP_RB0_WPTR, ring->wptr); 1524 (void)RREG32(CP_RB0_WPTR); 1525 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { 1526 WREG32(CP_RB1_WPTR, ring->wptr); 1527 (void)RREG32(CP_RB1_WPTR); 1528 } else { 1529 WREG32(CP_RB2_WPTR, ring->wptr); 1530 (void)RREG32(CP_RB2_WPTR); 1531 } 1532 } 1533 1534 static int cayman_cp_load_microcode(struct radeon_device *rdev) 1535 { 1536 const __be32 *fw_data; 1537 int i; 1538 1539 if (!rdev->me_fw || !rdev->pfp_fw) 1540 return -EINVAL; 1541 1542 cayman_cp_enable(rdev, false); 1543 1544 fw_data = (const __be32 *)rdev->pfp_fw->data; 1545 WREG32(CP_PFP_UCODE_ADDR, 0); 1546 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) 1547 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1548 WREG32(CP_PFP_UCODE_ADDR, 0); 1549 1550 fw_data = (const __be32 *)rdev->me_fw->data; 1551 WREG32(CP_ME_RAM_WADDR, 0); 1552 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) 1553 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1554 1555 WREG32(CP_PFP_UCODE_ADDR, 0); 1556 WREG32(CP_ME_RAM_WADDR, 0); 1557 WREG32(CP_ME_RAM_RADDR, 0); 1558 return 0; 1559 } 1560 1561 static int cayman_cp_start(struct radeon_device *rdev) 1562 { 1563 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1564 int r, i; 1565 1566 r = radeon_ring_lock(rdev, ring, 7); 1567 if (r) { 1568 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1569 return r; 1570 } 1571 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1572 radeon_ring_write(ring, 0x1); 1573 radeon_ring_write(ring, 0x0); 1574 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); 1575 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1576 radeon_ring_write(ring, 0); 1577 radeon_ring_write(ring, 0); 1578 radeon_ring_unlock_commit(rdev, ring, false); 1579 1580 cayman_cp_enable(rdev, true); 1581 1582 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); 1583 if (r) { 1584 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1585 return r; 1586 } 1587 1588 /* setup clear context state */ 1589 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1590 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1591 1592 for (i = 0; i < cayman_default_size; i++) 1593 radeon_ring_write(ring, cayman_default_state[i]); 1594 1595 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1596 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1597 1598 /* set clear context state */ 1599 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1600 radeon_ring_write(ring, 0); 1601 1602 /* SQ_VTX_BASE_VTX_LOC */ 1603 radeon_ring_write(ring, 0xc0026f00); 1604 radeon_ring_write(ring, 0x00000000); 1605 radeon_ring_write(ring, 0x00000000); 1606 radeon_ring_write(ring, 0x00000000); 1607 1608 /* Clear consts */ 1609 radeon_ring_write(ring, 0xc0036f00); 1610 radeon_ring_write(ring, 0x00000bc4); 1611 radeon_ring_write(ring, 0xffffffff); 1612 radeon_ring_write(ring, 0xffffffff); 1613 radeon_ring_write(ring, 0xffffffff); 1614 1615 radeon_ring_write(ring, 0xc0026900); 1616 radeon_ring_write(ring, 0x00000316); 1617 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1618 radeon_ring_write(ring, 0x00000010); /* */ 1619 1620 radeon_ring_unlock_commit(rdev, ring, false); 1621 1622 /* XXX init other rings */ 1623 1624 return 0; 1625 } 1626 1627 static void cayman_cp_fini(struct radeon_device *rdev) 1628 { 1629 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1630 cayman_cp_enable(rdev, false); 1631 radeon_ring_fini(rdev, ring); 1632 radeon_scratch_free(rdev, ring->rptr_save_reg); 1633 } 1634 1635 static int cayman_cp_resume(struct radeon_device *rdev) 1636 { 1637 static const int ridx[] = { 1638 RADEON_RING_TYPE_GFX_INDEX, 1639 CAYMAN_RING_TYPE_CP1_INDEX, 1640 CAYMAN_RING_TYPE_CP2_INDEX 1641 }; 1642 static const unsigned cp_rb_cntl[] = { 1643 CP_RB0_CNTL, 1644 CP_RB1_CNTL, 1645 CP_RB2_CNTL, 1646 }; 1647 static const unsigned cp_rb_rptr_addr[] = { 1648 CP_RB0_RPTR_ADDR, 1649 CP_RB1_RPTR_ADDR, 1650 CP_RB2_RPTR_ADDR 1651 }; 1652 static const unsigned cp_rb_rptr_addr_hi[] = { 1653 CP_RB0_RPTR_ADDR_HI, 1654 CP_RB1_RPTR_ADDR_HI, 1655 CP_RB2_RPTR_ADDR_HI 1656 }; 1657 static const unsigned cp_rb_base[] = { 1658 CP_RB0_BASE, 1659 CP_RB1_BASE, 1660 CP_RB2_BASE 1661 }; 1662 static const unsigned cp_rb_rptr[] = { 1663 CP_RB0_RPTR, 1664 CP_RB1_RPTR, 1665 CP_RB2_RPTR 1666 }; 1667 static const unsigned cp_rb_wptr[] = { 1668 CP_RB0_WPTR, 1669 CP_RB1_WPTR, 1670 CP_RB2_WPTR 1671 }; 1672 struct radeon_ring *ring; 1673 int i, r; 1674 1675 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1676 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1677 SOFT_RESET_PA | 1678 SOFT_RESET_SH | 1679 SOFT_RESET_VGT | 1680 SOFT_RESET_SPI | 1681 SOFT_RESET_SX)); 1682 RREG32(GRBM_SOFT_RESET); 1683 mdelay(15); 1684 WREG32(GRBM_SOFT_RESET, 0); 1685 RREG32(GRBM_SOFT_RESET); 1686 1687 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1688 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1689 1690 /* Set the write pointer delay */ 1691 WREG32(CP_RB_WPTR_DELAY, 0); 1692 1693 WREG32(CP_DEBUG, (1 << 27)); 1694 1695 /* set the wb address whether it's enabled or not */ 1696 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1697 WREG32(SCRATCH_UMSK, 0xff); 1698 1699 for (i = 0; i < 3; ++i) { 1700 uint32_t rb_cntl; 1701 uint64_t addr; 1702 1703 /* Set ring buffer size */ 1704 ring = &rdev->ring[ridx[i]]; 1705 rb_cntl = order_base_2(ring->ring_size / 8); 1706 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; 1707 #ifdef __BIG_ENDIAN 1708 rb_cntl |= BUF_SWAP_32BIT; 1709 #endif 1710 WREG32(cp_rb_cntl[i], rb_cntl); 1711 1712 /* set the wb address whether it's enabled or not */ 1713 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; 1714 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); 1715 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); 1716 } 1717 1718 /* set the rb base addr, this causes an internal reset of ALL rings */ 1719 for (i = 0; i < 3; ++i) { 1720 ring = &rdev->ring[ridx[i]]; 1721 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); 1722 } 1723 1724 for (i = 0; i < 3; ++i) { 1725 /* Initialize the ring buffer's read and write pointers */ 1726 ring = &rdev->ring[ridx[i]]; 1727 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1728 1729 ring->wptr = 0; 1730 WREG32(cp_rb_rptr[i], 0); 1731 WREG32(cp_rb_wptr[i], ring->wptr); 1732 1733 mdelay(1); 1734 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1735 } 1736 1737 /* start the rings */ 1738 cayman_cp_start(rdev); 1739 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 1740 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1741 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1742 /* this only test cp0 */ 1743 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1744 if (r) { 1745 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1746 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1747 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1748 return r; 1749 } 1750 1751 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1752 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1753 1754 return 0; 1755 } 1756 1757 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) 1758 { 1759 u32 reset_mask = 0; 1760 u32 tmp; 1761 1762 /* GRBM_STATUS */ 1763 tmp = RREG32(GRBM_STATUS); 1764 if (tmp & (PA_BUSY | SC_BUSY | 1765 SH_BUSY | SX_BUSY | 1766 TA_BUSY | VGT_BUSY | 1767 DB_BUSY | CB_BUSY | 1768 GDS_BUSY | SPI_BUSY | 1769 IA_BUSY | IA_BUSY_NO_DMA)) 1770 reset_mask |= RADEON_RESET_GFX; 1771 1772 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | 1773 CP_BUSY | CP_COHERENCY_BUSY)) 1774 reset_mask |= RADEON_RESET_CP; 1775 1776 if (tmp & GRBM_EE_BUSY) 1777 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1778 1779 /* DMA_STATUS_REG 0 */ 1780 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); 1781 if (!(tmp & DMA_IDLE)) 1782 reset_mask |= RADEON_RESET_DMA; 1783 1784 /* DMA_STATUS_REG 1 */ 1785 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); 1786 if (!(tmp & DMA_IDLE)) 1787 reset_mask |= RADEON_RESET_DMA1; 1788 1789 /* SRBM_STATUS2 */ 1790 tmp = RREG32(SRBM_STATUS2); 1791 if (tmp & DMA_BUSY) 1792 reset_mask |= RADEON_RESET_DMA; 1793 1794 if (tmp & DMA1_BUSY) 1795 reset_mask |= RADEON_RESET_DMA1; 1796 1797 /* SRBM_STATUS */ 1798 tmp = RREG32(SRBM_STATUS); 1799 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) 1800 reset_mask |= RADEON_RESET_RLC; 1801 1802 if (tmp & IH_BUSY) 1803 reset_mask |= RADEON_RESET_IH; 1804 1805 if (tmp & SEM_BUSY) 1806 reset_mask |= RADEON_RESET_SEM; 1807 1808 if (tmp & GRBM_RQ_PENDING) 1809 reset_mask |= RADEON_RESET_GRBM; 1810 1811 if (tmp & VMC_BUSY) 1812 reset_mask |= RADEON_RESET_VMC; 1813 1814 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | 1815 MCC_BUSY | MCD_BUSY)) 1816 reset_mask |= RADEON_RESET_MC; 1817 1818 if (evergreen_is_display_hung(rdev)) 1819 reset_mask |= RADEON_RESET_DISPLAY; 1820 1821 /* VM_L2_STATUS */ 1822 tmp = RREG32(VM_L2_STATUS); 1823 if (tmp & L2_BUSY) 1824 reset_mask |= RADEON_RESET_VMC; 1825 1826 /* Skip MC reset as it's mostly likely not hung, just busy */ 1827 if (reset_mask & RADEON_RESET_MC) { 1828 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1829 reset_mask &= ~RADEON_RESET_MC; 1830 } 1831 1832 return reset_mask; 1833 } 1834 1835 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1836 { 1837 struct evergreen_mc_save save; 1838 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1839 u32 tmp; 1840 1841 if (reset_mask == 0) 1842 return; 1843 1844 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1845 1846 evergreen_print_gpu_status_regs(rdev); 1847 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", 1848 RREG32(0x14F8)); 1849 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", 1850 RREG32(0x14D8)); 1851 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1852 RREG32(0x14FC)); 1853 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1854 RREG32(0x14DC)); 1855 1856 /* Disable CP parsing/prefetching */ 1857 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1858 1859 if (reset_mask & RADEON_RESET_DMA) { 1860 /* dma0 */ 1861 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 1862 tmp &= ~DMA_RB_ENABLE; 1863 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 1864 } 1865 1866 if (reset_mask & RADEON_RESET_DMA1) { 1867 /* dma1 */ 1868 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 1869 tmp &= ~DMA_RB_ENABLE; 1870 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 1871 } 1872 1873 udelay(50); 1874 1875 evergreen_mc_stop(rdev, &save); 1876 if (evergreen_mc_wait_for_idle(rdev)) { 1877 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1878 } 1879 1880 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1881 grbm_soft_reset = SOFT_RESET_CB | 1882 SOFT_RESET_DB | 1883 SOFT_RESET_GDS | 1884 SOFT_RESET_PA | 1885 SOFT_RESET_SC | 1886 SOFT_RESET_SPI | 1887 SOFT_RESET_SH | 1888 SOFT_RESET_SX | 1889 SOFT_RESET_TC | 1890 SOFT_RESET_TA | 1891 SOFT_RESET_VGT | 1892 SOFT_RESET_IA; 1893 } 1894 1895 if (reset_mask & RADEON_RESET_CP) { 1896 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT; 1897 1898 srbm_soft_reset |= SOFT_RESET_GRBM; 1899 } 1900 1901 if (reset_mask & RADEON_RESET_DMA) 1902 srbm_soft_reset |= SOFT_RESET_DMA; 1903 1904 if (reset_mask & RADEON_RESET_DMA1) 1905 srbm_soft_reset |= SOFT_RESET_DMA1; 1906 1907 if (reset_mask & RADEON_RESET_DISPLAY) 1908 srbm_soft_reset |= SOFT_RESET_DC; 1909 1910 if (reset_mask & RADEON_RESET_RLC) 1911 srbm_soft_reset |= SOFT_RESET_RLC; 1912 1913 if (reset_mask & RADEON_RESET_SEM) 1914 srbm_soft_reset |= SOFT_RESET_SEM; 1915 1916 if (reset_mask & RADEON_RESET_IH) 1917 srbm_soft_reset |= SOFT_RESET_IH; 1918 1919 if (reset_mask & RADEON_RESET_GRBM) 1920 srbm_soft_reset |= SOFT_RESET_GRBM; 1921 1922 if (reset_mask & RADEON_RESET_VMC) 1923 srbm_soft_reset |= SOFT_RESET_VMC; 1924 1925 if (!(rdev->flags & RADEON_IS_IGP)) { 1926 if (reset_mask & RADEON_RESET_MC) 1927 srbm_soft_reset |= SOFT_RESET_MC; 1928 } 1929 1930 if (grbm_soft_reset) { 1931 tmp = RREG32(GRBM_SOFT_RESET); 1932 tmp |= grbm_soft_reset; 1933 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1934 WREG32(GRBM_SOFT_RESET, tmp); 1935 tmp = RREG32(GRBM_SOFT_RESET); 1936 1937 udelay(50); 1938 1939 tmp &= ~grbm_soft_reset; 1940 WREG32(GRBM_SOFT_RESET, tmp); 1941 tmp = RREG32(GRBM_SOFT_RESET); 1942 } 1943 1944 if (srbm_soft_reset) { 1945 tmp = RREG32(SRBM_SOFT_RESET); 1946 tmp |= srbm_soft_reset; 1947 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1948 WREG32(SRBM_SOFT_RESET, tmp); 1949 tmp = RREG32(SRBM_SOFT_RESET); 1950 1951 udelay(50); 1952 1953 tmp &= ~srbm_soft_reset; 1954 WREG32(SRBM_SOFT_RESET, tmp); 1955 tmp = RREG32(SRBM_SOFT_RESET); 1956 } 1957 1958 /* Wait a little for things to settle down */ 1959 udelay(50); 1960 1961 evergreen_mc_resume(rdev, &save); 1962 udelay(50); 1963 1964 evergreen_print_gpu_status_regs(rdev); 1965 } 1966 1967 int cayman_asic_reset(struct radeon_device *rdev) 1968 { 1969 u32 reset_mask; 1970 1971 reset_mask = cayman_gpu_check_soft_reset(rdev); 1972 1973 if (reset_mask) 1974 r600_set_bios_scratch_engine_hung(rdev, true); 1975 1976 cayman_gpu_soft_reset(rdev, reset_mask); 1977 1978 reset_mask = cayman_gpu_check_soft_reset(rdev); 1979 1980 if (reset_mask) 1981 evergreen_gpu_pci_config_reset(rdev); 1982 1983 r600_set_bios_scratch_engine_hung(rdev, false); 1984 1985 return 0; 1986 } 1987 1988 /** 1989 * cayman_gfx_is_lockup - Check if the GFX engine is locked up 1990 * 1991 * @rdev: radeon_device pointer 1992 * @ring: radeon_ring structure holding ring information 1993 * 1994 * Check if the GFX engine is locked up. 1995 * Returns true if the engine appears to be locked up, false if not. 1996 */ 1997 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1998 { 1999 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); 2000 2001 if (!(reset_mask & (RADEON_RESET_GFX | 2002 RADEON_RESET_COMPUTE | 2003 RADEON_RESET_CP))) { 2004 radeon_ring_lockup_update(rdev, ring); 2005 return false; 2006 } 2007 return radeon_ring_test_lockup(rdev, ring); 2008 } 2009 2010 static int cayman_startup(struct radeon_device *rdev) 2011 { 2012 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2013 int r; 2014 2015 /* enable pcie gen2 link */ 2016 evergreen_pcie_gen2_enable(rdev); 2017 /* enable aspm */ 2018 evergreen_program_aspm(rdev); 2019 2020 /* scratch needs to be initialized before MC */ 2021 r = r600_vram_scratch_init(rdev); 2022 if (r) 2023 return r; 2024 2025 evergreen_mc_program(rdev); 2026 2027 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { 2028 r = ni_mc_load_microcode(rdev); 2029 if (r) { 2030 DRM_ERROR("Failed to load MC firmware!\n"); 2031 return r; 2032 } 2033 } 2034 2035 r = cayman_pcie_gart_enable(rdev); 2036 if (r) 2037 return r; 2038 cayman_gpu_init(rdev); 2039 2040 /* allocate rlc buffers */ 2041 if (rdev->flags & RADEON_IS_IGP) { 2042 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; 2043 rdev->rlc.reg_list_size = 2044 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list); 2045 rdev->rlc.cs_data = cayman_cs_data; 2046 r = sumo_rlc_init(rdev); 2047 if (r) { 2048 DRM_ERROR("Failed to init rlc BOs!\n"); 2049 return r; 2050 } 2051 } 2052 2053 /* allocate wb buffer */ 2054 r = radeon_wb_init(rdev); 2055 if (r) 2056 return r; 2057 2058 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2059 if (r) { 2060 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2061 return r; 2062 } 2063 2064 r = uvd_v2_2_resume(rdev); 2065 if (!r) { 2066 r = radeon_fence_driver_start_ring(rdev, 2067 R600_RING_TYPE_UVD_INDEX); 2068 if (r) 2069 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 2070 } 2071 if (r) 2072 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 2073 2074 if (rdev->family == CHIP_ARUBA) { 2075 r = radeon_vce_resume(rdev); 2076 if (!r) 2077 r = vce_v1_0_resume(rdev); 2078 2079 if (!r) 2080 r = radeon_fence_driver_start_ring(rdev, 2081 TN_RING_TYPE_VCE1_INDEX); 2082 if (!r) 2083 r = radeon_fence_driver_start_ring(rdev, 2084 TN_RING_TYPE_VCE2_INDEX); 2085 2086 if (r) { 2087 dev_err(rdev->dev, "VCE init error (%d).\n", r); 2088 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; 2089 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; 2090 } 2091 } 2092 2093 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 2094 if (r) { 2095 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2096 return r; 2097 } 2098 2099 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 2100 if (r) { 2101 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2102 return r; 2103 } 2104 2105 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2106 if (r) { 2107 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2108 return r; 2109 } 2110 2111 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 2112 if (r) { 2113 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2114 return r; 2115 } 2116 2117 /* Enable IRQ */ 2118 if (!rdev->irq.installed) { 2119 r = radeon_irq_kms_init(rdev); 2120 if (r) 2121 return r; 2122 } 2123 2124 r = r600_irq_init(rdev); 2125 if (r) { 2126 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2127 radeon_irq_kms_fini(rdev); 2128 return r; 2129 } 2130 evergreen_irq_set(rdev); 2131 2132 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2133 RADEON_CP_PACKET2); 2134 if (r) 2135 return r; 2136 2137 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2138 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2139 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2140 if (r) 2141 return r; 2142 2143 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2144 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 2145 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2146 if (r) 2147 return r; 2148 2149 r = cayman_cp_load_microcode(rdev); 2150 if (r) 2151 return r; 2152 r = cayman_cp_resume(rdev); 2153 if (r) 2154 return r; 2155 2156 r = cayman_dma_resume(rdev); 2157 if (r) 2158 return r; 2159 2160 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2161 if (ring->ring_size) { 2162 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 2163 RADEON_CP_PACKET2); 2164 if (!r) 2165 r = uvd_v1_0_init(rdev); 2166 if (r) 2167 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 2168 } 2169 2170 if (rdev->family == CHIP_ARUBA) { 2171 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2172 if (ring->ring_size) 2173 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2174 2175 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2176 if (ring->ring_size) 2177 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2178 2179 if (!r) 2180 r = vce_v1_0_init(rdev); 2181 if (r) 2182 DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); 2183 } 2184 2185 r = radeon_ib_pool_init(rdev); 2186 if (r) { 2187 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2188 return r; 2189 } 2190 2191 r = radeon_vm_manager_init(rdev); 2192 if (r) { 2193 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 2194 return r; 2195 } 2196 2197 r = radeon_audio_init(rdev); 2198 if (r) 2199 return r; 2200 2201 return 0; 2202 } 2203 2204 int cayman_resume(struct radeon_device *rdev) 2205 { 2206 int r; 2207 2208 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 2209 * posting will perform necessary task to bring back GPU into good 2210 * shape. 2211 */ 2212 /* post card */ 2213 atom_asic_init(rdev->mode_info.atom_context); 2214 2215 /* init golden registers */ 2216 ni_init_golden_registers(rdev); 2217 2218 if (rdev->pm.pm_method == PM_METHOD_DPM) 2219 radeon_pm_resume(rdev); 2220 2221 rdev->accel_working = true; 2222 r = cayman_startup(rdev); 2223 if (r) { 2224 DRM_ERROR("cayman startup failed on resume\n"); 2225 rdev->accel_working = false; 2226 return r; 2227 } 2228 return r; 2229 } 2230 2231 int cayman_suspend(struct radeon_device *rdev) 2232 { 2233 radeon_pm_suspend(rdev); 2234 radeon_audio_fini(rdev); 2235 radeon_vm_manager_fini(rdev); 2236 cayman_cp_enable(rdev, false); 2237 cayman_dma_stop(rdev); 2238 uvd_v1_0_fini(rdev); 2239 radeon_uvd_suspend(rdev); 2240 evergreen_irq_suspend(rdev); 2241 radeon_wb_disable(rdev); 2242 cayman_pcie_gart_disable(rdev); 2243 return 0; 2244 } 2245 2246 /* Plan is to move initialization in that function and use 2247 * helper function so that radeon_device_init pretty much 2248 * do nothing more than calling asic specific function. This 2249 * should also allow to remove a bunch of callback function 2250 * like vram_info. 2251 */ 2252 int cayman_init(struct radeon_device *rdev) 2253 { 2254 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2255 int r; 2256 2257 /* Read BIOS */ 2258 if (!radeon_get_bios(rdev)) { 2259 if (ASIC_IS_AVIVO(rdev)) 2260 return -EINVAL; 2261 } 2262 /* Must be an ATOMBIOS */ 2263 if (!rdev->is_atom_bios) { 2264 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 2265 return -EINVAL; 2266 } 2267 r = radeon_atombios_init(rdev); 2268 if (r) 2269 return r; 2270 2271 /* Post card if necessary */ 2272 if (!radeon_card_posted(rdev)) { 2273 if (!rdev->bios) { 2274 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2275 return -EINVAL; 2276 } 2277 DRM_INFO("GPU not posted. posting now...\n"); 2278 atom_asic_init(rdev->mode_info.atom_context); 2279 } 2280 /* init golden registers */ 2281 ni_init_golden_registers(rdev); 2282 /* Initialize scratch registers */ 2283 r600_scratch_init(rdev); 2284 /* Initialize surface registers */ 2285 radeon_surface_init(rdev); 2286 /* Initialize clocks */ 2287 radeon_get_clock_info(rdev->ddev); 2288 /* Fence driver */ 2289 r = radeon_fence_driver_init(rdev); 2290 if (r) 2291 return r; 2292 /* initialize memory controller */ 2293 r = evergreen_mc_init(rdev); 2294 if (r) 2295 return r; 2296 /* Memory manager */ 2297 r = radeon_bo_init(rdev); 2298 if (r) 2299 return r; 2300 2301 if (rdev->flags & RADEON_IS_IGP) { 2302 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2303 r = ni_init_microcode(rdev); 2304 if (r) { 2305 DRM_ERROR("Failed to load firmware!\n"); 2306 return r; 2307 } 2308 } 2309 } else { 2310 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 2311 r = ni_init_microcode(rdev); 2312 if (r) { 2313 DRM_ERROR("Failed to load firmware!\n"); 2314 return r; 2315 } 2316 } 2317 } 2318 2319 /* Initialize power management */ 2320 radeon_pm_init(rdev); 2321 2322 ring->ring_obj = NULL; 2323 r600_ring_init(rdev, ring, 1024 * 1024); 2324 2325 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2326 ring->ring_obj = NULL; 2327 r600_ring_init(rdev, ring, 64 * 1024); 2328 2329 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2330 ring->ring_obj = NULL; 2331 r600_ring_init(rdev, ring, 64 * 1024); 2332 2333 r = radeon_uvd_init(rdev); 2334 if (!r) { 2335 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2336 ring->ring_obj = NULL; 2337 r600_ring_init(rdev, ring, 4096); 2338 } 2339 2340 if (rdev->family == CHIP_ARUBA) { 2341 r = radeon_vce_init(rdev); 2342 if (!r) { 2343 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2344 ring->ring_obj = NULL; 2345 r600_ring_init(rdev, ring, 4096); 2346 2347 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2348 ring->ring_obj = NULL; 2349 r600_ring_init(rdev, ring, 4096); 2350 } 2351 } 2352 2353 rdev->ih.ring_obj = NULL; 2354 r600_ih_ring_init(rdev, 64 * 1024); 2355 2356 r = r600_pcie_gart_init(rdev); 2357 if (r) 2358 return r; 2359 2360 rdev->accel_working = true; 2361 r = cayman_startup(rdev); 2362 if (r) { 2363 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2364 cayman_cp_fini(rdev); 2365 cayman_dma_fini(rdev); 2366 r600_irq_fini(rdev); 2367 if (rdev->flags & RADEON_IS_IGP) 2368 sumo_rlc_fini(rdev); 2369 radeon_wb_fini(rdev); 2370 radeon_ib_pool_fini(rdev); 2371 radeon_vm_manager_fini(rdev); 2372 radeon_irq_kms_fini(rdev); 2373 cayman_pcie_gart_fini(rdev); 2374 rdev->accel_working = false; 2375 } 2376 2377 /* Don't start up if the MC ucode is missing. 2378 * The default clocks and voltages before the MC ucode 2379 * is loaded are not suffient for advanced operations. 2380 * 2381 * We can skip this check for TN, because there is no MC 2382 * ucode. 2383 */ 2384 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 2385 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 2386 return -EINVAL; 2387 } 2388 2389 return 0; 2390 } 2391 2392 void cayman_fini(struct radeon_device *rdev) 2393 { 2394 radeon_pm_fini(rdev); 2395 cayman_cp_fini(rdev); 2396 cayman_dma_fini(rdev); 2397 r600_irq_fini(rdev); 2398 if (rdev->flags & RADEON_IS_IGP) 2399 sumo_rlc_fini(rdev); 2400 radeon_wb_fini(rdev); 2401 radeon_vm_manager_fini(rdev); 2402 radeon_ib_pool_fini(rdev); 2403 radeon_irq_kms_fini(rdev); 2404 uvd_v1_0_fini(rdev); 2405 radeon_uvd_fini(rdev); 2406 if (rdev->family == CHIP_ARUBA) 2407 radeon_vce_fini(rdev); 2408 cayman_pcie_gart_fini(rdev); 2409 r600_vram_scratch_fini(rdev); 2410 radeon_gem_fini(rdev); 2411 radeon_fence_driver_fini(rdev); 2412 radeon_bo_fini(rdev); 2413 radeon_atombios_fini(rdev); 2414 kfree(rdev->bios); 2415 rdev->bios = NULL; 2416 } 2417 2418 /* 2419 * vm 2420 */ 2421 int cayman_vm_init(struct radeon_device *rdev) 2422 { 2423 /* number of VMs */ 2424 rdev->vm_manager.nvm = 8; 2425 /* base offset of vram pages */ 2426 if (rdev->flags & RADEON_IS_IGP) { 2427 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); 2428 tmp <<= 22; 2429 rdev->vm_manager.vram_base_offset = tmp; 2430 } else 2431 rdev->vm_manager.vram_base_offset = 0; 2432 return 0; 2433 } 2434 2435 void cayman_vm_fini(struct radeon_device *rdev) 2436 { 2437 } 2438 2439 /** 2440 * cayman_vm_decode_fault - print human readable fault info 2441 * 2442 * @rdev: radeon_device pointer 2443 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 2444 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 2445 * 2446 * Print human readable fault information (cayman/TN). 2447 */ 2448 void cayman_vm_decode_fault(struct radeon_device *rdev, 2449 u32 status, u32 addr) 2450 { 2451 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 2452 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 2453 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 2454 const char *block; 2455 2456 switch (mc_id) { 2457 case 32: 2458 case 16: 2459 case 96: 2460 case 80: 2461 case 160: 2462 case 144: 2463 case 224: 2464 case 208: 2465 block = "CB"; 2466 break; 2467 case 33: 2468 case 17: 2469 case 97: 2470 case 81: 2471 case 161: 2472 case 145: 2473 case 225: 2474 case 209: 2475 block = "CB_FMASK"; 2476 break; 2477 case 34: 2478 case 18: 2479 case 98: 2480 case 82: 2481 case 162: 2482 case 146: 2483 case 226: 2484 case 210: 2485 block = "CB_CMASK"; 2486 break; 2487 case 35: 2488 case 19: 2489 case 99: 2490 case 83: 2491 case 163: 2492 case 147: 2493 case 227: 2494 case 211: 2495 block = "CB_IMMED"; 2496 break; 2497 case 36: 2498 case 20: 2499 case 100: 2500 case 84: 2501 case 164: 2502 case 148: 2503 case 228: 2504 case 212: 2505 block = "DB"; 2506 break; 2507 case 37: 2508 case 21: 2509 case 101: 2510 case 85: 2511 case 165: 2512 case 149: 2513 case 229: 2514 case 213: 2515 block = "DB_HTILE"; 2516 break; 2517 case 38: 2518 case 22: 2519 case 102: 2520 case 86: 2521 case 166: 2522 case 150: 2523 case 230: 2524 case 214: 2525 block = "SX"; 2526 break; 2527 case 39: 2528 case 23: 2529 case 103: 2530 case 87: 2531 case 167: 2532 case 151: 2533 case 231: 2534 case 215: 2535 block = "DB_STEN"; 2536 break; 2537 case 40: 2538 case 24: 2539 case 104: 2540 case 88: 2541 case 232: 2542 case 216: 2543 case 168: 2544 case 152: 2545 block = "TC_TFETCH"; 2546 break; 2547 case 41: 2548 case 25: 2549 case 105: 2550 case 89: 2551 case 233: 2552 case 217: 2553 case 169: 2554 case 153: 2555 block = "TC_VFETCH"; 2556 break; 2557 case 42: 2558 case 26: 2559 case 106: 2560 case 90: 2561 case 234: 2562 case 218: 2563 case 170: 2564 case 154: 2565 block = "VC"; 2566 break; 2567 case 112: 2568 block = "CP"; 2569 break; 2570 case 113: 2571 case 114: 2572 block = "SH"; 2573 break; 2574 case 115: 2575 block = "VGT"; 2576 break; 2577 case 178: 2578 block = "IH"; 2579 break; 2580 case 51: 2581 block = "RLC"; 2582 break; 2583 case 55: 2584 block = "DMA"; 2585 break; 2586 case 56: 2587 block = "HDP"; 2588 break; 2589 default: 2590 block = "unknown"; 2591 break; 2592 } 2593 2594 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", 2595 protections, vmid, addr, 2596 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", 2597 block, mc_id); 2598 } 2599 2600 /** 2601 * cayman_vm_flush - vm flush using the CP 2602 * 2603 * @rdev: radeon_device pointer 2604 * 2605 * Update the page table base and flush the VM TLB 2606 * using the CP (cayman-si). 2607 */ 2608 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 2609 unsigned vm_id, uint64_t pd_addr) 2610 { 2611 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); 2612 radeon_ring_write(ring, pd_addr >> 12); 2613 2614 /* flush hdp cache */ 2615 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 2616 radeon_ring_write(ring, 0x1); 2617 2618 /* bits 0-7 are the VM contexts0-7 */ 2619 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); 2620 radeon_ring_write(ring, 1 << vm_id); 2621 2622 /* wait for the invalidate to complete */ 2623 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2624 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2625 WAIT_REG_MEM_ENGINE(0))); /* me */ 2626 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 2627 radeon_ring_write(ring, 0); 2628 radeon_ring_write(ring, 0); /* ref */ 2629 radeon_ring_write(ring, 0); /* mask */ 2630 radeon_ring_write(ring, 0x20); /* poll interval */ 2631 2632 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2633 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2634 radeon_ring_write(ring, 0x0); 2635 } 2636 2637 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) 2638 { 2639 struct atom_clock_dividers dividers; 2640 int r, i; 2641 2642 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 2643 ecclk, false, ÷rs); 2644 if (r) 2645 return r; 2646 2647 for (i = 0; i < 100; i++) { 2648 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2649 break; 2650 mdelay(10); 2651 } 2652 if (i == 100) 2653 return -ETIMEDOUT; 2654 2655 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); 2656 2657 for (i = 0; i < 100; i++) { 2658 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2659 break; 2660 mdelay(10); 2661 } 2662 if (i == 100) 2663 return -ETIMEDOUT; 2664 2665 return 0; 2666 } 2667