1 /* $NetBSD: radeon_mode.h,v 1.5 2019/08/09 06:27:21 msaitoh Exp $ */ 2 3 /* 4 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 5 * VA Linux Systems Inc., Fremont, California. 6 * Copyright 2008 Red Hat Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Original Authors: 27 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 28 * 29 * Kernel port Author: Dave Airlie 30 */ 31 32 #ifndef RADEON_MODE_H 33 #define RADEON_MODE_H 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_dp_mst_helper.h> 39 #include <drm/drm_fixed.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <linux/i2c.h> 42 #include <linux/i2c-algo-bit.h> 43 44 struct radeon_bo; 45 struct radeon_device; 46 47 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 48 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 49 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 50 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 51 52 #define RADEON_MAX_HPD_PINS 7 53 #define RADEON_MAX_CRTCS 6 54 #define RADEON_MAX_AFMT_BLOCKS 7 55 56 enum radeon_rmx_type { 57 RMX_OFF, 58 RMX_FULL, 59 RMX_CENTER, 60 RMX_ASPECT 61 }; 62 63 enum radeon_tv_std { 64 TV_STD_NTSC, 65 TV_STD_PAL, 66 TV_STD_PAL_M, 67 TV_STD_PAL_60, 68 TV_STD_NTSC_J, 69 TV_STD_SCART_PAL, 70 TV_STD_SECAM, 71 TV_STD_PAL_CN, 72 TV_STD_PAL_N, 73 }; 74 75 enum radeon_underscan_type { 76 UNDERSCAN_OFF, 77 UNDERSCAN_ON, 78 UNDERSCAN_AUTO, 79 }; 80 81 enum radeon_hpd_id { 82 RADEON_HPD_1 = 0, 83 RADEON_HPD_2, 84 RADEON_HPD_3, 85 RADEON_HPD_4, 86 RADEON_HPD_5, 87 RADEON_HPD_6, 88 RADEON_HPD_NONE = 0xff, 89 }; 90 91 enum radeon_output_csc { 92 RADEON_OUTPUT_CSC_BYPASS = 0, 93 RADEON_OUTPUT_CSC_TVRGB = 1, 94 RADEON_OUTPUT_CSC_YCBCR601 = 2, 95 RADEON_OUTPUT_CSC_YCBCR709 = 3, 96 }; 97 98 #define RADEON_MAX_I2C_BUS 16 99 100 /* radeon gpio-based i2c 101 * 1. "mask" reg and bits 102 * grabs the gpio pins for software use 103 * 0=not held 1=held 104 * 2. "a" reg and bits 105 * output pin value 106 * 0=low 1=high 107 * 3. "en" reg and bits 108 * sets the pin direction 109 * 0=input 1=output 110 * 4. "y" reg and bits 111 * input pin value 112 * 0=low 1=high 113 */ 114 struct radeon_i2c_bus_rec { 115 bool valid; 116 /* id used by atom */ 117 uint8_t i2c_id; 118 /* id used by atom */ 119 enum radeon_hpd_id hpd; 120 /* can be used with hw i2c engine */ 121 bool hw_capable; 122 /* uses multi-media i2c engine */ 123 bool mm_i2c; 124 /* regs and bits */ 125 uint32_t mask_clk_reg; 126 uint32_t mask_data_reg; 127 uint32_t a_clk_reg; 128 uint32_t a_data_reg; 129 uint32_t en_clk_reg; 130 uint32_t en_data_reg; 131 uint32_t y_clk_reg; 132 uint32_t y_data_reg; 133 uint32_t mask_clk_mask; 134 uint32_t mask_data_mask; 135 uint32_t a_clk_mask; 136 uint32_t a_data_mask; 137 uint32_t en_clk_mask; 138 uint32_t en_data_mask; 139 uint32_t y_clk_mask; 140 uint32_t y_data_mask; 141 }; 142 143 struct radeon_tmds_pll { 144 uint32_t freq; 145 uint32_t value; 146 }; 147 148 #define RADEON_MAX_BIOS_CONNECTOR 16 149 150 /* pll flags */ 151 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 152 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 153 #define RADEON_PLL_USE_REF_DIV (1 << 2) 154 #define RADEON_PLL_LEGACY (1 << 3) 155 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 156 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 157 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 158 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 159 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 160 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 161 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 162 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 163 #define RADEON_PLL_USE_POST_DIV (1 << 12) 164 #define RADEON_PLL_IS_LCD (1 << 13) 165 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 166 167 struct radeon_pll { 168 /* reference frequency */ 169 uint32_t reference_freq; 170 171 /* fixed dividers */ 172 uint32_t reference_div; 173 uint32_t post_div; 174 175 /* pll in/out limits */ 176 uint32_t pll_in_min; 177 uint32_t pll_in_max; 178 uint32_t pll_out_min; 179 uint32_t pll_out_max; 180 uint32_t lcd_pll_out_min; 181 uint32_t lcd_pll_out_max; 182 uint32_t best_vco; 183 184 /* divider limits */ 185 uint32_t min_ref_div; 186 uint32_t max_ref_div; 187 uint32_t min_post_div; 188 uint32_t max_post_div; 189 uint32_t min_feedback_div; 190 uint32_t max_feedback_div; 191 uint32_t min_frac_feedback_div; 192 uint32_t max_frac_feedback_div; 193 194 /* flags for the current clock */ 195 uint32_t flags; 196 197 /* pll id */ 198 uint32_t id; 199 }; 200 201 struct radeon_i2c_chan { 202 struct i2c_adapter adapter; 203 struct drm_device *dev; 204 struct i2c_algo_bit_data bit; 205 struct radeon_i2c_bus_rec rec; 206 struct drm_dp_aux aux; 207 bool has_aux; 208 struct mutex mutex; 209 }; 210 211 /* mostly for macs, but really any system without connector tables */ 212 enum radeon_connector_table { 213 CT_NONE = 0, 214 CT_GENERIC, 215 CT_IBOOK, 216 CT_POWERBOOK_EXTERNAL, 217 CT_POWERBOOK_INTERNAL, 218 CT_POWERBOOK_VGA, 219 CT_MINI_EXTERNAL, 220 CT_MINI_INTERNAL, 221 CT_IMAC_G5_ISIGHT, 222 CT_EMAC, 223 CT_RN50_POWER, 224 CT_MAC_X800, 225 CT_MAC_G5_9600, 226 CT_SAM440EP, 227 CT_MAC_G4_SILVER 228 }; 229 230 enum radeon_dvo_chip { 231 DVO_SIL164, 232 DVO_SIL1178, 233 }; 234 235 struct radeon_fbdev; 236 237 struct radeon_afmt { 238 bool enabled; 239 int offset; 240 bool last_buffer_filled_status; 241 int id; 242 }; 243 244 struct radeon_mode_info { 245 struct atom_context *atom_context; 246 struct card_info *atom_card_info; 247 enum radeon_connector_table connector_table; 248 bool mode_config_initialized; 249 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 250 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 251 /* DVI-I properties */ 252 struct drm_property *coherent_mode_property; 253 /* DAC enable load detect */ 254 struct drm_property *load_detect_property; 255 /* TV standard */ 256 struct drm_property *tv_std_property; 257 /* legacy TMDS PLL detect */ 258 struct drm_property *tmds_pll_property; 259 /* underscan */ 260 struct drm_property *underscan_property; 261 struct drm_property *underscan_hborder_property; 262 struct drm_property *underscan_vborder_property; 263 /* audio */ 264 struct drm_property *audio_property; 265 /* FMT dithering */ 266 struct drm_property *dither_property; 267 /* Output CSC */ 268 struct drm_property *output_csc_property; 269 /* hardcoded DFP edid from BIOS */ 270 struct edid *bios_hardcoded_edid; 271 int bios_hardcoded_edid_size; 272 273 /* pointer to fbdev info structure */ 274 struct radeon_fbdev *rfbdev; 275 /* firmware flags */ 276 u16 firmware_flags; 277 /* pointer to backlight encoder */ 278 struct radeon_encoder *bl_encoder; 279 280 /* bitmask for active encoder frontends */ 281 uint32_t active_encoders; 282 }; 283 284 #define RADEON_MAX_BL_LEVEL 0xFF 285 286 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 287 288 struct radeon_backlight_privdata { 289 struct radeon_encoder *encoder; 290 uint8_t negative; 291 }; 292 293 #endif 294 295 #define MAX_H_CODE_TIMING_LEN 32 296 #define MAX_V_CODE_TIMING_LEN 32 297 298 /* need to store these as reading 299 back code tables is excessive */ 300 struct radeon_tv_regs { 301 uint32_t tv_uv_adr; 302 uint32_t timing_cntl; 303 uint32_t hrestart; 304 uint32_t vrestart; 305 uint32_t frestart; 306 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 307 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 308 }; 309 310 struct radeon_atom_ss { 311 uint16_t percentage; 312 uint16_t percentage_divider; 313 uint8_t type; 314 uint16_t step; 315 uint8_t delay; 316 uint8_t range; 317 uint8_t refdiv; 318 /* asic_ss */ 319 uint16_t rate; 320 uint16_t amount; 321 }; 322 323 enum radeon_flip_status { 324 RADEON_FLIP_NONE, 325 RADEON_FLIP_PENDING, 326 RADEON_FLIP_SUBMITTED 327 }; 328 329 struct radeon_crtc { 330 struct drm_crtc base; 331 int crtc_id; 332 u16 lut_r[256], lut_g[256], lut_b[256]; 333 bool enabled; 334 bool can_tile; 335 bool cursor_out_of_bounds; 336 uint32_t crtc_offset; 337 struct drm_gem_object *cursor_bo; 338 uint64_t cursor_addr; 339 int cursor_x; 340 int cursor_y; 341 int cursor_hot_x; 342 int cursor_hot_y; 343 int cursor_width; 344 int cursor_height; 345 int max_cursor_width; 346 int max_cursor_height; 347 uint32_t legacy_display_base_addr; 348 enum radeon_rmx_type rmx_type; 349 u8 h_border; 350 u8 v_border; 351 fixed20_12 vsc; 352 fixed20_12 hsc; 353 struct drm_display_mode native_mode; 354 int pll_id; 355 /* page flipping */ 356 struct workqueue_struct *flip_queue; 357 struct radeon_flip_work *flip_work; 358 enum radeon_flip_status flip_status; 359 /* pll sharing */ 360 struct radeon_atom_ss ss; 361 bool ss_enabled; 362 u32 adjusted_clock; 363 int bpc; 364 u32 pll_reference_div; 365 u32 pll_post_div; 366 u32 pll_flags; 367 struct drm_encoder *encoder; 368 struct drm_connector *connector; 369 /* for dpm */ 370 u32 line_time; 371 u32 wm_low; 372 u32 wm_high; 373 u32 lb_vblank_lead_lines; 374 struct drm_display_mode hw_mode; 375 enum radeon_output_csc output_csc; 376 }; 377 378 struct radeon_encoder_primary_dac { 379 /* legacy primary dac */ 380 uint32_t ps2_pdac_adj; 381 }; 382 383 struct radeon_encoder_lvds { 384 /* legacy lvds */ 385 uint16_t panel_vcc_delay; 386 uint8_t panel_pwr_delay; 387 uint8_t panel_digon_delay; 388 uint8_t panel_blon_delay; 389 uint16_t panel_ref_divider; 390 uint8_t panel_post_divider; 391 uint16_t panel_fb_divider; 392 bool use_bios_dividers; 393 uint32_t lvds_gen_cntl; 394 /* panel mode */ 395 struct drm_display_mode native_mode; 396 struct backlight_device *bl_dev; 397 int dpms_mode; 398 uint8_t backlight_level; 399 }; 400 401 struct radeon_encoder_tv_dac { 402 /* legacy tv dac */ 403 uint32_t ps2_tvdac_adj; 404 uint32_t ntsc_tvdac_adj; 405 uint32_t pal_tvdac_adj; 406 407 int h_pos; 408 int v_pos; 409 int h_size; 410 int supported_tv_stds; 411 bool tv_on; 412 enum radeon_tv_std tv_std; 413 struct radeon_tv_regs tv; 414 }; 415 416 struct radeon_encoder_int_tmds { 417 /* legacy int tmds */ 418 struct radeon_tmds_pll tmds_pll[4]; 419 }; 420 421 struct radeon_encoder_ext_tmds { 422 /* tmds over dvo */ 423 struct radeon_i2c_chan *i2c_bus; 424 uint8_t slave_addr; 425 enum radeon_dvo_chip dvo_chip; 426 }; 427 428 /* spread spectrum */ 429 struct radeon_encoder_atom_dig { 430 bool linkb; 431 /* atom dig */ 432 bool coherent_mode; 433 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 434 /* atom lvds/edp */ 435 uint32_t lcd_misc; 436 uint16_t panel_pwr_delay; 437 uint32_t lcd_ss_id; 438 /* panel mode */ 439 struct drm_display_mode native_mode; 440 struct backlight_device *bl_dev; 441 int dpms_mode; 442 uint8_t backlight_level; 443 int panel_mode; 444 struct radeon_afmt *afmt; 445 struct r600_audio_pin *pin; 446 int active_mst_links; 447 }; 448 449 struct radeon_encoder_atom_dac { 450 enum radeon_tv_std tv_std; 451 }; 452 453 struct radeon_encoder_mst { 454 int crtc; 455 struct radeon_encoder *primary; 456 struct radeon_connector *connector; 457 struct drm_dp_mst_port *port; 458 int pbn; 459 int fe; 460 bool fe_from_be; 461 bool enc_active; 462 }; 463 464 struct radeon_encoder { 465 struct drm_encoder base; 466 uint32_t encoder_enum; 467 uint32_t encoder_id; 468 uint32_t devices; 469 uint32_t active_device; 470 uint32_t flags; 471 uint32_t pixel_clock; 472 enum radeon_rmx_type rmx_type; 473 enum radeon_underscan_type underscan_type; 474 uint32_t underscan_hborder; 475 uint32_t underscan_vborder; 476 struct drm_display_mode native_mode; 477 void *enc_priv; 478 int audio_polling_active; 479 bool is_ext_encoder; 480 u16 caps; 481 struct radeon_audio_funcs *audio; 482 enum radeon_output_csc output_csc; 483 bool can_mst; 484 uint32_t offset; 485 bool is_mst_encoder; 486 /* front end for this mst encoder */ 487 }; 488 489 struct radeon_connector_atom_dig { 490 uint32_t igp_lane_info; 491 /* displayport */ 492 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 493 u8 dp_sink_type; 494 int dp_clock; 495 int dp_lane_count; 496 bool edp_on; 497 bool is_mst; 498 }; 499 500 struct radeon_gpio_rec { 501 bool valid; 502 u8 id; 503 u32 reg; 504 u32 mask; 505 u32 shift; 506 }; 507 508 struct radeon_hpd { 509 enum radeon_hpd_id hpd; 510 u8 plugged_state; 511 struct radeon_gpio_rec gpio; 512 }; 513 514 struct radeon_router { 515 u32 router_id; 516 struct radeon_i2c_bus_rec i2c_info; 517 u8 i2c_addr; 518 /* i2c mux */ 519 bool ddc_valid; 520 u8 ddc_mux_type; 521 u8 ddc_mux_control_pin; 522 u8 ddc_mux_state; 523 /* clock/data mux */ 524 bool cd_valid; 525 u8 cd_mux_type; 526 u8 cd_mux_control_pin; 527 u8 cd_mux_state; 528 }; 529 530 enum radeon_connector_audio { 531 RADEON_AUDIO_DISABLE = 0, 532 RADEON_AUDIO_ENABLE = 1, 533 RADEON_AUDIO_AUTO = 2 534 }; 535 536 enum radeon_connector_dither { 537 RADEON_FMT_DITHER_DISABLE = 0, 538 RADEON_FMT_DITHER_ENABLE = 1, 539 }; 540 541 struct stream_attribs { 542 uint16_t fe; 543 uint16_t slots; 544 }; 545 546 struct radeon_connector { 547 struct drm_connector base; 548 uint32_t connector_id; 549 uint32_t devices; 550 struct radeon_i2c_chan *ddc_bus; 551 /* some systems have an hdmi and vga port with a shared ddc line */ 552 bool shared_ddc; 553 bool use_digital; 554 /* we need to mind the EDID between detect 555 and get modes due to analog/digital/tvencoder */ 556 struct edid *edid; 557 void *con_priv; 558 bool dac_load_detect; 559 bool detected_by_load; /* if the connection status was determined by load */ 560 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 561 uint16_t connector_object_id; 562 struct radeon_hpd hpd; 563 struct radeon_router router; 564 struct radeon_i2c_chan *router_bus; 565 enum radeon_connector_audio audio; 566 enum radeon_connector_dither dither; 567 int pixelclock_for_modeset; 568 bool is_mst_connector; 569 struct radeon_connector *mst_port; 570 struct drm_dp_mst_port *port; 571 struct drm_dp_mst_topology_mgr mst_mgr; 572 573 struct radeon_encoder *mst_encoder; 574 struct stream_attribs cur_stream_attribs[6]; 575 int enabled_attribs; 576 }; 577 578 struct radeon_framebuffer { 579 struct drm_framebuffer base; 580 struct drm_gem_object *obj; 581 }; 582 583 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 584 ((em) == ATOM_ENCODER_MODE_DP_MST)) 585 586 struct atom_clock_dividers { 587 u32 post_div; 588 union { 589 struct { 590 #ifdef __BIG_ENDIAN 591 u32 reserved : 6; 592 u32 whole_fb_div : 12; 593 u32 frac_fb_div : 14; 594 #else 595 u32 frac_fb_div : 14; 596 u32 whole_fb_div : 12; 597 u32 reserved : 6; 598 #endif 599 }; 600 u32 fb_div; 601 }; 602 u32 ref_div; 603 bool enable_post_div; 604 bool enable_dithen; 605 u32 vco_mode; 606 u32 real_clock; 607 /* added for CI */ 608 u32 post_divider; 609 u32 flags; 610 }; 611 612 struct atom_mpll_param { 613 union { 614 struct { 615 #ifdef __BIG_ENDIAN 616 u32 reserved : 8; 617 u32 clkfrac : 12; 618 u32 clkf : 12; 619 #else 620 u32 clkf : 12; 621 u32 clkfrac : 12; 622 u32 reserved : 8; 623 #endif 624 }; 625 u32 fb_div; 626 }; 627 u32 post_div; 628 u32 bwcntl; 629 u32 dll_speed; 630 u32 vco_mode; 631 u32 yclk_sel; 632 u32 qdr; 633 u32 half_rate; 634 }; 635 636 #define MEM_TYPE_GDDR5 0x50 637 #define MEM_TYPE_GDDR4 0x40 638 #define MEM_TYPE_GDDR3 0x30 639 #define MEM_TYPE_DDR2 0x20 640 #define MEM_TYPE_GDDR1 0x10 641 #define MEM_TYPE_DDR3 0xb0 642 #define MEM_TYPE_MASK 0xf0 643 644 struct atom_memory_info { 645 u8 mem_vendor; 646 u8 mem_type; 647 }; 648 649 #define MAX_AC_TIMING_ENTRIES 16 650 651 struct atom_memory_clock_range_table 652 { 653 u8 num_entries; 654 u8 rsv[3]; 655 u32 mclk[MAX_AC_TIMING_ENTRIES]; 656 }; 657 658 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 659 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 660 661 struct atom_mc_reg_entry { 662 u32 mclk_max; 663 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 664 }; 665 666 struct atom_mc_register_address { 667 u16 s1; 668 u8 pre_reg_data; 669 }; 670 671 struct atom_mc_reg_table { 672 u8 last; 673 u8 num_entries; 674 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 675 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 676 }; 677 678 #define MAX_VOLTAGE_ENTRIES 32 679 680 struct atom_voltage_table_entry 681 { 682 u16 value; 683 u32 smio_low; 684 }; 685 686 struct atom_voltage_table 687 { 688 u32 count; 689 u32 mask_low; 690 u32 phase_delay; 691 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 692 }; 693 694 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 695 #define USE_REAL_VBLANKSTART (1 << 30) 696 #define GET_DISTANCE_TO_VBLANKSTART (1U << 31) 697 698 extern void 699 radeon_add_atom_connector(struct drm_device *dev, 700 uint32_t connector_id, 701 uint32_t supported_device, 702 int connector_type, 703 struct radeon_i2c_bus_rec *i2c_bus, 704 uint32_t igp_lane_info, 705 uint16_t connector_object_id, 706 struct radeon_hpd *hpd, 707 struct radeon_router *router); 708 extern void 709 radeon_add_legacy_connector(struct drm_device *dev, 710 uint32_t connector_id, 711 uint32_t supported_device, 712 int connector_type, 713 struct radeon_i2c_bus_rec *i2c_bus, 714 uint16_t connector_object_id, 715 struct radeon_hpd *hpd); 716 extern uint32_t 717 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 718 uint8_t dac); 719 extern void radeon_link_encoder_connector(struct drm_device *dev); 720 721 extern enum radeon_tv_std 722 radeon_combios_get_tv_info(struct radeon_device *rdev); 723 extern enum radeon_tv_std 724 radeon_atombios_get_tv_info(struct radeon_device *rdev); 725 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 726 u16 *vddc, u16 *vddci, u16 *mvdd); 727 728 extern void 729 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 730 struct drm_encoder *encoder, 731 bool connected); 732 extern void 733 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 734 struct drm_encoder *encoder, 735 bool connected); 736 737 extern struct drm_connector * 738 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 739 extern struct drm_connector * 740 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 741 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 742 u32 pixel_clock); 743 744 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 745 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 746 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 747 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 748 749 extern struct edid *radeon_connector_edid(struct drm_connector *connector); 750 751 extern void radeon_connector_hotplug(struct drm_connector *connector); 752 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 753 struct drm_display_mode *mode); 754 extern void radeon_dp_set_link_config(struct drm_connector *connector, 755 const struct drm_display_mode *mode); 756 extern void radeon_dp_link_train(struct drm_encoder *encoder, 757 struct drm_connector *connector); 758 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 759 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 760 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 761 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 762 struct drm_connector *connector); 763 extern int radeon_dp_get_dp_link_config(struct drm_connector *connector, 764 const u8 *dpcd, 765 unsigned pix_clock, 766 unsigned *dp_lanes, unsigned *dp_rate); 767 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 768 u8 power_state); 769 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 770 extern ssize_t 771 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 772 773 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 774 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 775 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 776 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 777 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 778 int action, uint8_t lane_num, 779 uint8_t lane_set); 780 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 781 int action, uint8_t lane_num, 782 uint8_t lane_set, int fe); 783 extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, 784 int fe); 785 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 786 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 787 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 788 789 extern void radeon_i2c_init(struct radeon_device *rdev); 790 extern void radeon_i2c_fini(struct radeon_device *rdev); 791 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 792 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 793 extern void radeon_i2c_add(struct radeon_device *rdev, 794 struct radeon_i2c_bus_rec *rec, 795 const char *name); 796 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 797 struct radeon_i2c_bus_rec *i2c_bus); 798 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 799 struct radeon_i2c_bus_rec *rec, 800 const char *name); 801 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 802 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 803 u8 slave_addr, 804 u8 addr, 805 u8 *val); 806 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 807 u8 slave_addr, 808 u8 addr, 809 u8 val); 810 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 811 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 812 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 813 814 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 815 struct radeon_atom_ss *ss, 816 int id); 817 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 818 struct radeon_atom_ss *ss, 819 int id, u32 clock); 820 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 821 u8 id); 822 823 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 824 uint64_t freq, 825 uint32_t *dot_clock_p, 826 uint32_t *fb_div_p, 827 uint32_t *frac_fb_div_p, 828 uint32_t *ref_div_p, 829 uint32_t *post_div_p); 830 831 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 832 u32 freq, 833 u32 *dot_clock_p, 834 u32 *fb_div_p, 835 u32 *frac_fb_div_p, 836 u32 *ref_div_p, 837 u32 *post_div_p); 838 839 extern void radeon_setup_encoder_clones(struct drm_device *dev); 840 841 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 842 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 843 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 844 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 845 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 846 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 847 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 848 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 849 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 850 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 851 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 852 853 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 854 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 855 struct drm_framebuffer *old_fb); 856 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 857 struct drm_framebuffer *fb, 858 int x, int y, 859 enum mode_set_atomic state); 860 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 861 struct drm_display_mode *mode, 862 struct drm_display_mode *adjusted_mode, 863 int x, int y, 864 struct drm_framebuffer *old_fb); 865 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 866 867 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 868 struct drm_framebuffer *old_fb); 869 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 870 struct drm_framebuffer *fb, 871 int x, int y, 872 enum mode_set_atomic state); 873 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 874 struct drm_framebuffer *fb, 875 int x, int y, int atomic); 876 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 877 struct drm_file *file_priv, 878 uint32_t handle, 879 uint32_t width, 880 uint32_t height, 881 int32_t hot_x, 882 int32_t hot_y); 883 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 884 int x, int y); 885 extern void radeon_cursor_reset(struct drm_crtc *crtc); 886 887 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 888 unsigned int flags, int *vpos, int *hpos, 889 ktime_t *stime, ktime_t *etime, 890 const struct drm_display_mode *mode); 891 892 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 893 extern struct edid * 894 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 895 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 896 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 897 extern struct radeon_encoder_atom_dig * 898 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 899 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 900 struct radeon_encoder_int_tmds *tmds); 901 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 902 struct radeon_encoder_int_tmds *tmds); 903 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 904 struct radeon_encoder_int_tmds *tmds); 905 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 906 struct radeon_encoder_ext_tmds *tmds); 907 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 908 struct radeon_encoder_ext_tmds *tmds); 909 extern struct radeon_encoder_primary_dac * 910 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 911 extern struct radeon_encoder_tv_dac * 912 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 913 extern struct radeon_encoder_lvds * 914 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 915 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 916 extern struct radeon_encoder_tv_dac * 917 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 918 extern struct radeon_encoder_primary_dac * 919 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 920 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 921 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 922 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 923 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 924 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 925 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 926 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 927 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 928 extern void 929 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 930 extern void 931 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 932 extern void 933 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 934 extern void 935 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 936 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 937 u16 blue, int regno); 938 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 939 u16 *blue, int regno); 940 int radeon_framebuffer_init(struct drm_device *dev, 941 struct radeon_framebuffer *rfb, 942 struct drm_mode_fb_cmd2 *mode_cmd, 943 struct drm_gem_object *obj); 944 945 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 946 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 947 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 948 void radeon_atombios_init_crtc(struct drm_device *dev, 949 struct radeon_crtc *radeon_crtc); 950 void radeon_legacy_init_crtc(struct drm_device *dev, 951 struct radeon_crtc *radeon_crtc); 952 953 void radeon_get_clock_info(struct drm_device *dev); 954 955 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 956 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 957 958 void radeon_enc_destroy(struct drm_encoder *encoder); 959 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 960 void radeon_combios_asic_init(struct drm_device *dev); 961 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 962 const struct drm_display_mode *mode, 963 struct drm_display_mode *adjusted_mode); 964 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 965 struct drm_display_mode *adjusted_mode); 966 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 967 968 /* legacy tv */ 969 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 970 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 971 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 972 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 973 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 974 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 975 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 976 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 977 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 978 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 979 struct drm_display_mode *mode, 980 struct drm_display_mode *adjusted_mode); 981 982 /* fmt blocks */ 983 void avivo_program_fmt(struct drm_encoder *encoder); 984 void dce3_program_fmt(struct drm_encoder *encoder); 985 void dce4_program_fmt(struct drm_encoder *encoder); 986 void dce8_program_fmt(struct drm_encoder *encoder); 987 988 /* fbdev layer */ 989 int radeon_fbdev_init(struct radeon_device *rdev); 990 void radeon_fbdev_fini(struct radeon_device *rdev); 991 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 992 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 993 void radeon_fbdev_restore_mode(struct radeon_device *rdev); 994 995 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 996 997 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 998 999 void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); 1000 void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); 1001 1002 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 1003 1004 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 1005 1006 /* mst */ 1007 int radeon_dp_mst_init(struct radeon_connector *radeon_connector); 1008 int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); 1009 int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); 1010 int radeon_mst_debugfs_init(struct radeon_device *rdev); 1011 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); 1012 1013 void radeon_setup_mst_connector(struct drm_device *dev); 1014 1015 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 1016 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 1017 #endif 1018