xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/radeon_legacy_crtc.c (revision 33881f779a77dce6440bdc44610d94de75bebefe)
1 /*	$NetBSD: radeon_legacy_crtc.c,v 1.3 2018/08/27 04:58:36 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2007-8 Advanced Micro Devices, Inc.
5  * Copyright 2008 Red Hat Inc.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the "Software"),
9  * to deal in the Software without restriction, including without limitation
10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11  * and/or sell copies of the Software, and to permit persons to whom the
12  * Software is furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23  * OTHER DEALINGS IN THE SOFTWARE.
24  *
25  * Authors: Dave Airlie
26  *          Alex Deucher
27  */
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_crtc.c,v 1.3 2018/08/27 04:58:36 riastradh Exp $");
30 
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/radeon_drm.h>
34 #include <drm/drm_fixed.h>
35 #include "radeon.h"
36 #include "atom.h"
37 
38 static void radeon_overscan_setup(struct drm_crtc *crtc,
39 				  struct drm_display_mode *mode)
40 {
41 	struct drm_device *dev = crtc->dev;
42 	struct radeon_device *rdev = dev->dev_private;
43 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
44 
45 	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
46 	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
47 	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
48 }
49 
50 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
51 				       struct drm_display_mode *mode)
52 {
53 	struct drm_device *dev = crtc->dev;
54 	struct radeon_device *rdev = dev->dev_private;
55 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
56 	int xres = mode->hdisplay;
57 	int yres = mode->vdisplay;
58 	bool hscale = true, vscale = true;
59 	int hsync_wid;
60 	int vsync_wid;
61 	int hsync_start;
62 	int blank_width;
63 	u32 scale, inc, crtc_more_cntl;
64 	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
65 	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
66 	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
67 	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
68 
69 	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
70 		(RADEON_VERT_STRETCH_RESERVED |
71 		 RADEON_VERT_AUTO_RATIO_INC);
72 	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
73 		(RADEON_HORZ_FP_LOOP_STRETCH |
74 		 RADEON_HORZ_AUTO_RATIO_INC);
75 
76 	crtc_more_cntl = 0;
77 	if ((rdev->family == CHIP_RS100) ||
78 	    (rdev->family == CHIP_RS200)) {
79 		/* This is to workaround the asic bug for RMX, some versions
80 		   of BIOS dosen't have this register initialized correctly. */
81 		crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
82 	}
83 
84 
85 	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
86 				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
87 
88 	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
89 	if (!hsync_wid)
90 		hsync_wid = 1;
91 	hsync_start = mode->crtc_hsync_start - 8;
92 
93 	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
94 			      | ((hsync_wid & 0x3f) << 16)
95 			      | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
96 				 ? RADEON_CRTC_H_SYNC_POL
97 				 : 0));
98 
99 	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
100 				| ((mode->crtc_vdisplay - 1) << 16));
101 
102 	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
103 	if (!vsync_wid)
104 		vsync_wid = 1;
105 
106 	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
107 			      | ((vsync_wid & 0x1f) << 16)
108 			      | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
109 				 ? RADEON_CRTC_V_SYNC_POL
110 				 : 0));
111 
112 	fp_horz_vert_active = 0;
113 
114 	if (native_mode->hdisplay == 0 ||
115 	    native_mode->vdisplay == 0) {
116 		hscale = false;
117 		vscale = false;
118 	} else {
119 		if (xres > native_mode->hdisplay)
120 			xres = native_mode->hdisplay;
121 		if (yres > native_mode->vdisplay)
122 			yres = native_mode->vdisplay;
123 
124 		if (xres == native_mode->hdisplay)
125 			hscale = false;
126 		if (yres == native_mode->vdisplay)
127 			vscale = false;
128 	}
129 
130 	switch (radeon_crtc->rmx_type) {
131 	case RMX_FULL:
132 	case RMX_ASPECT:
133 		if (!hscale)
134 			fp_horz_stretch |= ((xres/8-1) << 16);
135 		else {
136 			inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
137 			scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
138 				/ native_mode->hdisplay + 1;
139 			fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
140 					RADEON_HORZ_STRETCH_BLEND |
141 					RADEON_HORZ_STRETCH_ENABLE |
142 					((native_mode->hdisplay/8-1) << 16));
143 		}
144 
145 		if (!vscale)
146 			fp_vert_stretch |= ((yres-1) << 12);
147 		else {
148 			inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
149 			scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
150 				/ native_mode->vdisplay + 1;
151 			fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
152 					RADEON_VERT_STRETCH_ENABLE |
153 					RADEON_VERT_STRETCH_BLEND |
154 					((native_mode->vdisplay-1) << 12));
155 		}
156 		break;
157 	case RMX_CENTER:
158 		fp_horz_stretch |= ((xres/8-1) << 16);
159 		fp_vert_stretch |= ((yres-1) << 12);
160 
161 		crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
162 				RADEON_CRTC_AUTO_VERT_CENTER_EN);
163 
164 		blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
165 		if (blank_width > 110)
166 			blank_width = 110;
167 
168 		fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
169 				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
170 
171 		hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
172 		if (!hsync_wid)
173 			hsync_wid = 1;
174 
175 		fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
176 				| ((hsync_wid & 0x3f) << 16)
177 				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
178 					? RADEON_CRTC_H_SYNC_POL
179 					: 0));
180 
181 		fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
182 				| ((mode->crtc_vdisplay - 1) << 16));
183 
184 		vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
185 		if (!vsync_wid)
186 			vsync_wid = 1;
187 
188 		fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
189 					| ((vsync_wid & 0x1f) << 16)
190 					| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
191 						? RADEON_CRTC_V_SYNC_POL
192 						: 0)));
193 
194 		fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
195 				(((native_mode->hdisplay / 8) & 0x1ff) << 16));
196 		break;
197 	case RMX_OFF:
198 	default:
199 		fp_horz_stretch |= ((xres/8-1) << 16);
200 		fp_vert_stretch |= ((yres-1) << 12);
201 		break;
202 	}
203 
204 	WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
205 	WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
206 	WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
207 	WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
208 	WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
209 	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
210 	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
211 	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
212 }
213 
214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
215 {
216 	struct radeon_device *rdev = dev->dev_private;
217 	int i = 0;
218 
219 	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
220 	   the cause yet, but this workaround will mask the problem for now.
221 	   Other chips usually will pass at the very first test, so the
222 	   workaround shouldn't have any effect on them. */
223 	for (i = 0;
224 	     (i < 10000 &&
225 	      RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
226 	     i++);
227 }
228 
229 static void radeon_pll_write_update(struct drm_device *dev)
230 {
231 	struct radeon_device *rdev = dev->dev_private;
232 
233 	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
234 
235 	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236 			   RADEON_PPLL_ATOMIC_UPDATE_W,
237 			   ~(RADEON_PPLL_ATOMIC_UPDATE_W));
238 }
239 
240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
241 {
242 	struct radeon_device *rdev = dev->dev_private;
243 	int i = 0;
244 
245 
246 	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
247 	   the cause yet, but this workaround will mask the problem for now.
248 	   Other chips usually will pass at the very first test, so the
249 	   workaround shouldn't have any effect on them. */
250 	for (i = 0;
251 	     (i < 10000 &&
252 	      RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
253 	     i++);
254 }
255 
256 static void radeon_pll2_write_update(struct drm_device *dev)
257 {
258 	struct radeon_device *rdev = dev->dev_private;
259 
260 	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
261 
262 	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263 			   RADEON_P2PLL_ATOMIC_UPDATE_W,
264 			   ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
265 }
266 
267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
268 				       uint16_t fb_div)
269 {
270 	unsigned int vcoFreq;
271 
272 	if (!ref_div)
273 		return 1;
274 
275 	vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276 
277 	/*
278 	 * This is horribly crude: the VCO frequency range is divided into
279 	 * 3 parts, each part having a fixed PLL gain value.
280 	 */
281 	if (vcoFreq >= 30000)
282 		/*
283 		 * [300..max] MHz : 7
284 		 */
285 		return 7;
286 	else if (vcoFreq >= 18000)
287 		/*
288 		 * [180..300) MHz : 4
289 		 */
290 		return 4;
291 	else
292 		/*
293 		 * [0..180) MHz : 1
294 		 */
295 		return 1;
296 }
297 
298 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
299 {
300 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 	struct drm_device *dev = crtc->dev;
302 	struct radeon_device *rdev = dev->dev_private;
303 	uint32_t crtc_ext_cntl = 0;
304 	uint32_t mask;
305 
306 	if (radeon_crtc->crtc_id)
307 		mask = (RADEON_CRTC2_DISP_DIS |
308 			RADEON_CRTC2_VSYNC_DIS |
309 			RADEON_CRTC2_HSYNC_DIS |
310 			RADEON_CRTC2_DISP_REQ_EN_B);
311 	else
312 		mask = (RADEON_CRTC_DISPLAY_DIS |
313 			RADEON_CRTC_VSYNC_DIS |
314 			RADEON_CRTC_HSYNC_DIS);
315 
316 	/*
317 	 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
318 	 * Therefore it is set in the DAC DMPS function.
319 	 * This is different for GPU's with a single CRTC but a primary and a
320 	 * TV DAC: here it controls the single CRTC no matter where it is
321 	 * routed. Therefore we set it here.
322 	 */
323 	if (rdev->flags & RADEON_SINGLE_CRTC)
324 		crtc_ext_cntl = RADEON_CRTC_CRT_ON;
325 
326 	switch (mode) {
327 	case DRM_MODE_DPMS_ON:
328 		radeon_crtc->enabled = true;
329 		/* adjust pm to dpms changes BEFORE enabling crtcs */
330 		radeon_pm_compute_clocks(rdev);
331 		if (radeon_crtc->crtc_id)
332 			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
333 		else {
334 			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
335 									 RADEON_CRTC_DISP_REQ_EN_B));
336 			WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
337 		}
338 		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
339 		/* Make sure vblank interrupt is still enabled if needed */
340 		radeon_irq_set(rdev);
341 		radeon_crtc_load_lut(crtc);
342 		break;
343 	case DRM_MODE_DPMS_STANDBY:
344 	case DRM_MODE_DPMS_SUSPEND:
345 	case DRM_MODE_DPMS_OFF:
346 		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
347 		if (radeon_crtc->crtc_id)
348 			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
349 		else {
350 			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
351 										    RADEON_CRTC_DISP_REQ_EN_B));
352 			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
353 		}
354 		radeon_crtc->enabled = false;
355 		/* adjust pm to dpms changes AFTER disabling crtcs */
356 		radeon_pm_compute_clocks(rdev);
357 		break;
358 	}
359 }
360 
361 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
362 			 struct drm_framebuffer *old_fb)
363 {
364 	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
365 }
366 
367 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
368 				struct drm_framebuffer *fb,
369 				int x, int y, enum mode_set_atomic state)
370 {
371 	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
372 }
373 
374 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
375 			 struct drm_framebuffer *fb,
376 			 int x, int y, int atomic)
377 {
378 	struct drm_device *dev = crtc->dev;
379 	struct radeon_device *rdev = dev->dev_private;
380 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
381 	struct radeon_framebuffer *radeon_fb;
382 	struct drm_framebuffer *target_fb;
383 	struct drm_gem_object *obj;
384 	struct radeon_bo *rbo;
385 	uint64_t base;
386 	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
387 	uint32_t crtc_pitch, pitch_pixels;
388 	uint32_t tiling_flags;
389 	int format;
390 	uint32_t gen_cntl_reg, gen_cntl_val;
391 	int r;
392 
393 	DRM_DEBUG_KMS("\n");
394 	/* no fb bound */
395 	if (!atomic && !crtc->primary->fb) {
396 		DRM_DEBUG_KMS("No FB bound\n");
397 		return 0;
398 	}
399 
400 	if (atomic) {
401 		radeon_fb = to_radeon_framebuffer(fb);
402 		target_fb = fb;
403 	}
404 	else {
405 		radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
406 		target_fb = crtc->primary->fb;
407 	}
408 
409 	switch (target_fb->bits_per_pixel) {
410 	case 8:
411 		format = 2;
412 		break;
413 	case 15:      /*  555 */
414 		format = 3;
415 		break;
416 	case 16:      /*  565 */
417 		format = 4;
418 		break;
419 	case 24:      /*  RGB */
420 		format = 5;
421 		break;
422 	case 32:      /* xRGB */
423 		format = 6;
424 		break;
425 	default:
426 		return false;
427 	}
428 
429 	/* Pin framebuffer & get tilling informations */
430 	obj = radeon_fb->obj;
431 	rbo = gem_to_radeon_bo(obj);
432 	if (atomic) {
433 		/*
434 		 * If you want to do this in atomic, better have it
435 		 * pinned ahead of time.
436 		 */
437 		BUG_ON(rbo->pin_count == 0);
438 		base = radeon_bo_gpu_offset(rbo);
439 		tiling_flags = 0;
440 		goto pinned;
441 	}
442 retry:
443 	r = radeon_bo_reserve(rbo, false);
444 	if (unlikely(r != 0))
445 		return r;
446 	/* Only 27 bit offset for legacy CRTC */
447 	r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
448 				     &base);
449 	if (unlikely(r != 0)) {
450 		radeon_bo_unreserve(rbo);
451 
452 		/* On old GPU like RN50 with little vram pining can fails because
453 		 * current fb is taking all space needed. So instead of unpining
454 		 * the old buffer after pining the new one, first unpin old one
455 		 * and then retry pining new one.
456 		 *
457 		 * As only master can set mode only master can pin and it is
458 		 * unlikely the master client will race with itself especialy
459 		 * on those old gpu with single crtc.
460 		 *
461 		 * We don't shutdown the display controller because new buffer
462 		 * will end up in same spot.
463 		 */
464 		if (fb && fb != crtc->primary->fb) {
465 			struct radeon_bo *old_rbo;
466 			unsigned long nsize, osize;
467 
468 			old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj);
469 			osize = radeon_bo_size(old_rbo);
470 			nsize = radeon_bo_size(rbo);
471 			if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
472 				radeon_bo_unpin(old_rbo);
473 				radeon_bo_unreserve(old_rbo);
474 				fb = NULL;
475 				goto retry;
476 			}
477 		}
478 		return -EINVAL;
479 	}
480 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
481 	radeon_bo_unreserve(rbo);
482 pinned:
483 	if (tiling_flags & RADEON_TILING_MICRO)
484 		DRM_ERROR("trying to scanout microtiled buffer\n");
485 
486 	/* if scanout was in GTT this really wouldn't work */
487 	/* crtc offset is from display base addr not FB location */
488 	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
489 
490 	base -= radeon_crtc->legacy_display_base_addr;
491 
492 	crtc_offset_cntl = 0;
493 
494 	pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
495 	crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
496 			((target_fb->bits_per_pixel * 8) - 1)) /
497 		       (target_fb->bits_per_pixel * 8));
498 	crtc_pitch |= crtc_pitch << 16;
499 
500 	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
501 	if (tiling_flags & RADEON_TILING_MACRO) {
502 		if (ASIC_IS_R300(rdev))
503 			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
504 					     R300_CRTC_MICRO_TILE_BUFFER_DIS |
505 					     R300_CRTC_MACRO_TILE_EN);
506 		else
507 			crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
508 	} else {
509 		if (ASIC_IS_R300(rdev))
510 			crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
511 					      R300_CRTC_MICRO_TILE_BUFFER_DIS |
512 					      R300_CRTC_MACRO_TILE_EN);
513 		else
514 			crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
515 	}
516 
517 	if (tiling_flags & RADEON_TILING_MACRO) {
518 		if (ASIC_IS_R300(rdev)) {
519 			crtc_tile_x0_y0 = x | (y << 16);
520 			base &= ~0x7ff;
521 		} else {
522 			int byteshift = target_fb->bits_per_pixel >> 4;
523 			int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
524 			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
525 			crtc_offset_cntl |= (y % 16);
526 		}
527 	} else {
528 		int offset = y * pitch_pixels + x;
529 		switch (target_fb->bits_per_pixel) {
530 		case 8:
531 			offset *= 1;
532 			break;
533 		case 15:
534 		case 16:
535 			offset *= 2;
536 			break;
537 		case 24:
538 			offset *= 3;
539 			break;
540 		case 32:
541 			offset *= 4;
542 			break;
543 		default:
544 			return false;
545 		}
546 		base += offset;
547 	}
548 
549 	base &= ~7;
550 
551 	if (radeon_crtc->crtc_id == 1)
552 		gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
553 	else
554 		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
555 
556 	gen_cntl_val = RREG32(gen_cntl_reg);
557 	gen_cntl_val &= ~(0xf << 8);
558 	gen_cntl_val |= (format << 8);
559 	gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
560 	WREG32(gen_cntl_reg, gen_cntl_val);
561 
562 	crtc_offset = (u32)base;
563 
564 	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
565 
566 	if (ASIC_IS_R300(rdev)) {
567 		if (radeon_crtc->crtc_id)
568 			WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
569 		else
570 			WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
571 	}
572 	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
573 	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
574 	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
575 
576 	if (!atomic && fb && fb != crtc->primary->fb) {
577 		radeon_fb = to_radeon_framebuffer(fb);
578 		rbo = gem_to_radeon_bo(radeon_fb->obj);
579 		r = radeon_bo_reserve(rbo, false);
580 		if (unlikely(r != 0))
581 			return r;
582 		radeon_bo_unpin(rbo);
583 		radeon_bo_unreserve(rbo);
584 	}
585 
586 	/* Bytes per pixel may have changed */
587 	radeon_bandwidth_update(rdev);
588 
589 	return 0;
590 }
591 
592 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
593 {
594 	struct drm_device *dev = crtc->dev;
595 	struct radeon_device *rdev = dev->dev_private;
596 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
597 	struct drm_encoder *encoder;
598 	int format;
599 	int hsync_start;
600 	int hsync_wid;
601 	int vsync_wid;
602 	uint32_t crtc_h_total_disp;
603 	uint32_t crtc_h_sync_strt_wid;
604 	uint32_t crtc_v_total_disp;
605 	uint32_t crtc_v_sync_strt_wid;
606 	bool is_tv = false;
607 
608 	DRM_DEBUG_KMS("\n");
609 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
610 		if (encoder->crtc == crtc) {
611 			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
612 			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
613 				is_tv = true;
614 				DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
615 				break;
616 			}
617 		}
618 	}
619 
620 	switch (crtc->primary->fb->bits_per_pixel) {
621 	case 8:
622 		format = 2;
623 		break;
624 	case 15:      /*  555 */
625 		format = 3;
626 		break;
627 	case 16:      /*  565 */
628 		format = 4;
629 		break;
630 	case 24:      /*  RGB */
631 		format = 5;
632 		break;
633 	case 32:      /* xRGB */
634 		format = 6;
635 		break;
636 	default:
637 		return false;
638 	}
639 
640 	crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
641 			     | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
642 
643 	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
644 	if (!hsync_wid)
645 		hsync_wid = 1;
646 	hsync_start = mode->crtc_hsync_start - 8;
647 
648 	crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
649 				| ((hsync_wid & 0x3f) << 16)
650 				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
651 				   ? RADEON_CRTC_H_SYNC_POL
652 				   : 0));
653 
654 	/* This works for double scan mode. */
655 	crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
656 			     | ((mode->crtc_vdisplay - 1) << 16));
657 
658 	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
659 	if (!vsync_wid)
660 		vsync_wid = 1;
661 
662 	crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
663 				| ((vsync_wid & 0x1f) << 16)
664 				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
665 				   ? RADEON_CRTC_V_SYNC_POL
666 				   : 0));
667 
668 	if (radeon_crtc->crtc_id) {
669 		uint32_t crtc2_gen_cntl;
670 		uint32_t disp2_merge_cntl;
671 
672 		/* if TV DAC is enabled for another crtc and keep it enabled */
673 		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
674 		crtc2_gen_cntl |= ((format << 8)
675 				   | RADEON_CRTC2_VSYNC_DIS
676 				   | RADEON_CRTC2_HSYNC_DIS
677 				   | RADEON_CRTC2_DISP_DIS
678 				   | RADEON_CRTC2_DISP_REQ_EN_B
679 				   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
680 				      ? RADEON_CRTC2_DBL_SCAN_EN
681 				      : 0)
682 				   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
683 				      ? RADEON_CRTC2_CSYNC_EN
684 				      : 0)
685 				   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
686 				      ? RADEON_CRTC2_INTERLACE_EN
687 				      : 0));
688 
689 		/* rs4xx chips seem to like to have the crtc enabled when the timing is set */
690 		if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
691 			crtc2_gen_cntl |= RADEON_CRTC2_EN;
692 
693 		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
694 		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
695 
696 		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
697 		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
698 
699 		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
700 		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
701 	} else {
702 		uint32_t crtc_gen_cntl;
703 		uint32_t crtc_ext_cntl;
704 		uint32_t disp_merge_cntl;
705 
706 		crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
707 		crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
708 				 | (format << 8)
709 				 | RADEON_CRTC_DISP_REQ_EN_B
710 				 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
711 				    ? RADEON_CRTC_DBL_SCAN_EN
712 				    : 0)
713 				 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
714 				    ? RADEON_CRTC_CSYNC_EN
715 				    : 0)
716 				 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
717 				    ? RADEON_CRTC_INTERLACE_EN
718 				    : 0));
719 
720 		/* rs4xx chips seem to like to have the crtc enabled when the timing is set */
721 		if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
722 			crtc_gen_cntl |= RADEON_CRTC_EN;
723 
724 		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
725 		crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
726 				  RADEON_CRTC_VSYNC_DIS |
727 				  RADEON_CRTC_HSYNC_DIS |
728 				  RADEON_CRTC_DISPLAY_DIS);
729 
730 		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
731 		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
732 
733 		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
734 		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
735 		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
736 	}
737 
738 	if (is_tv)
739 		radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
740 						 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
741 						 &crtc_v_sync_strt_wid);
742 
743 	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
744 	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
745 	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
746 	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
747 
748 	return true;
749 }
750 
751 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
752 {
753 	struct drm_device *dev = crtc->dev;
754 	struct radeon_device *rdev = dev->dev_private;
755 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
756 	struct drm_encoder *encoder;
757 	uint32_t feedback_div = 0;
758 	uint32_t frac_fb_div = 0;
759 	uint32_t reference_div = 0;
760 	uint32_t post_divider = 0;
761 	uint32_t freq = 0;
762 	uint8_t pll_gain;
763 	bool use_bios_divs = false;
764 	/* PLL registers */
765 	uint32_t pll_ref_div = 0;
766 	uint32_t pll_fb_post_div = 0;
767 	uint32_t htotal_cntl = 0;
768 	bool is_tv = false;
769 	struct radeon_pll *pll;
770 
771 	struct {
772 		int divider;
773 		int bitvalue;
774 	} *post_div, post_divs[]   = {
775 		/* From RAGE 128 VR/RAGE 128 GL Register
776 		 * Reference Manual (Technical Reference
777 		 * Manual P/N RRG-G04100-C Rev. 0.04), page
778 		 * 3-17 (PLL_DIV_[3:0]).
779 		 */
780 		{  1, 0 },              /* VCLK_SRC                 */
781 		{  2, 1 },              /* VCLK_SRC/2               */
782 		{  4, 2 },              /* VCLK_SRC/4               */
783 		{  8, 3 },              /* VCLK_SRC/8               */
784 		{  3, 4 },              /* VCLK_SRC/3               */
785 		{ 16, 5 },              /* VCLK_SRC/16              */
786 		{  6, 6 },              /* VCLK_SRC/6               */
787 		{ 12, 7 },              /* VCLK_SRC/12              */
788 		{  0, 0 }
789 	};
790 
791 	if (radeon_crtc->crtc_id)
792 		pll = &rdev->clock.p2pll;
793 	else
794 		pll = &rdev->clock.p1pll;
795 
796 	pll->flags = RADEON_PLL_LEGACY;
797 
798 	if (mode->clock > 200000) /* range limits??? */
799 		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
800 	else
801 		pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
802 
803 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
804 		if (encoder->crtc == crtc) {
805 			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
806 
807 			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
808 				is_tv = true;
809 				break;
810 			}
811 
812 			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
813 				pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
814 			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
815 				if (!rdev->is_atom_bios) {
816 					struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
817 					struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
818 					if (lvds) {
819 						if (lvds->use_bios_dividers) {
820 							pll_ref_div = lvds->panel_ref_divider;
821 							pll_fb_post_div   = (lvds->panel_fb_divider |
822 									     (lvds->panel_post_divider << 16));
823 							htotal_cntl  = 0;
824 							use_bios_divs = true;
825 						}
826 					}
827 				}
828 				pll->flags |= RADEON_PLL_USE_REF_DIV;
829 			}
830 		}
831 	}
832 
833 	DRM_DEBUG_KMS("\n");
834 
835 	if (!use_bios_divs) {
836 		radeon_compute_pll_legacy(pll, mode->clock,
837 					  &freq, &feedback_div, &frac_fb_div,
838 					  &reference_div, &post_divider);
839 
840 		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
841 			if (post_div->divider == post_divider)
842 				break;
843 		}
844 
845 		if (!post_div->divider)
846 			post_div = &post_divs[0];
847 
848 		DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
849 			  (unsigned)freq,
850 			  feedback_div,
851 			  reference_div,
852 			  post_divider);
853 
854 		pll_ref_div   = reference_div;
855 #if defined(__powerpc__) && (0) /* TODO */
856 		/* apparently programming this otherwise causes a hang??? */
857 		if (info->MacModel == RADEON_MAC_IBOOK)
858 			pll_fb_post_div = 0x000600ad;
859 		else
860 #endif
861 			pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
862 
863 		htotal_cntl    = mode->htotal & 0x7;
864 
865 	}
866 
867 	pll_gain = radeon_compute_pll_gain(pll->reference_freq,
868 					   pll_ref_div & 0x3ff,
869 					   pll_fb_post_div & 0x7ff);
870 
871 	if (radeon_crtc->crtc_id) {
872 		uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
873 					  ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
874 					 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
875 
876 		if (is_tv) {
877 			radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
878 						     &pll_ref_div, &pll_fb_post_div,
879 						     &pixclks_cntl);
880 		}
881 
882 		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
883 			     RADEON_PIX2CLK_SRC_SEL_CPUCLK,
884 			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
885 
886 		WREG32_PLL_P(RADEON_P2PLL_CNTL,
887 			     RADEON_P2PLL_RESET
888 			     | RADEON_P2PLL_ATOMIC_UPDATE_EN
889 			     | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
890 			     ~(RADEON_P2PLL_RESET
891 			       | RADEON_P2PLL_ATOMIC_UPDATE_EN
892 			       | RADEON_P2PLL_PVG_MASK));
893 
894 		WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
895 			     pll_ref_div,
896 			     ~RADEON_P2PLL_REF_DIV_MASK);
897 
898 		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
899 			     pll_fb_post_div,
900 			     ~RADEON_P2PLL_FB0_DIV_MASK);
901 
902 		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
903 			     pll_fb_post_div,
904 			     ~RADEON_P2PLL_POST0_DIV_MASK);
905 
906 		radeon_pll2_write_update(dev);
907 		radeon_pll2_wait_for_read_update_complete(dev);
908 
909 		WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
910 
911 		WREG32_PLL_P(RADEON_P2PLL_CNTL,
912 			     0,
913 			     ~(RADEON_P2PLL_RESET
914 			       | RADEON_P2PLL_SLEEP
915 			       | RADEON_P2PLL_ATOMIC_UPDATE_EN));
916 
917 		DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
918 			  (unsigned)pll_ref_div,
919 			  (unsigned)pll_fb_post_div,
920 			  (unsigned)htotal_cntl,
921 			  RREG32_PLL(RADEON_P2PLL_CNTL));
922 		DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
923 			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
924 			  (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
925 			  (unsigned)((pll_fb_post_div &
926 				      RADEON_P2PLL_POST0_DIV_MASK) >> 16));
927 
928 		mdelay(50); /* Let the clock to lock */
929 
930 		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
931 			     RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
932 			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
933 
934 		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
935 	} else {
936 		uint32_t pixclks_cntl;
937 
938 
939 		if (is_tv) {
940 			pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
941 			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
942 						     &pll_fb_post_div, &pixclks_cntl);
943 		}
944 
945 		if (rdev->flags & RADEON_IS_MOBILITY) {
946 			/* A temporal workaround for the occasional blanking on certain laptop panels.
947 			   This appears to related to the PLL divider registers (fail to lock?).
948 			   It occurs even when all dividers are the same with their old settings.
949 			   In this case we really don't need to fiddle with PLL registers.
950 			   By doing this we can avoid the blanking problem with some panels.
951 			*/
952 			if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
953 			    (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
954 						 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
955 				WREG32_P(RADEON_CLOCK_CNTL_INDEX,
956 					 RADEON_PLL_DIV_SEL,
957 					 ~(RADEON_PLL_DIV_SEL));
958 				r100_pll_errata_after_index(rdev);
959 				return;
960 			}
961 		}
962 
963 		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
964 			     RADEON_VCLK_SRC_SEL_CPUCLK,
965 			     ~(RADEON_VCLK_SRC_SEL_MASK));
966 		WREG32_PLL_P(RADEON_PPLL_CNTL,
967 			     RADEON_PPLL_RESET
968 			     | RADEON_PPLL_ATOMIC_UPDATE_EN
969 			     | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
970 			     | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
971 			     ~(RADEON_PPLL_RESET
972 			       | RADEON_PPLL_ATOMIC_UPDATE_EN
973 			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
974 			       | RADEON_PPLL_PVG_MASK));
975 
976 		WREG32_P(RADEON_CLOCK_CNTL_INDEX,
977 			 RADEON_PLL_DIV_SEL,
978 			 ~(RADEON_PLL_DIV_SEL));
979 		r100_pll_errata_after_index(rdev);
980 
981 		if (ASIC_IS_R300(rdev) ||
982 		    (rdev->family == CHIP_RS300) ||
983 		    (rdev->family == CHIP_RS400) ||
984 		    (rdev->family == CHIP_RS480)) {
985 			if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
986 				/* When restoring console mode, use saved PPLL_REF_DIV
987 				 * setting.
988 				 */
989 				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
990 					     pll_ref_div,
991 					     0);
992 			} else {
993 				/* R300 uses ref_div_acc field as real ref divider */
994 				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
995 					     (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
996 					     ~R300_PPLL_REF_DIV_ACC_MASK);
997 			}
998 		} else
999 			WREG32_PLL_P(RADEON_PPLL_REF_DIV,
1000 				     pll_ref_div,
1001 				     ~RADEON_PPLL_REF_DIV_MASK);
1002 
1003 		WREG32_PLL_P(RADEON_PPLL_DIV_3,
1004 			     pll_fb_post_div,
1005 			     ~RADEON_PPLL_FB3_DIV_MASK);
1006 
1007 		WREG32_PLL_P(RADEON_PPLL_DIV_3,
1008 			     pll_fb_post_div,
1009 			     ~RADEON_PPLL_POST3_DIV_MASK);
1010 
1011 		radeon_pll_write_update(dev);
1012 		radeon_pll_wait_for_read_update_complete(dev);
1013 
1014 		WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
1015 
1016 		WREG32_PLL_P(RADEON_PPLL_CNTL,
1017 			     0,
1018 			     ~(RADEON_PPLL_RESET
1019 			       | RADEON_PPLL_SLEEP
1020 			       | RADEON_PPLL_ATOMIC_UPDATE_EN
1021 			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1022 
1023 		DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1024 			  pll_ref_div,
1025 			  pll_fb_post_div,
1026 			  (unsigned)htotal_cntl,
1027 			  RREG32_PLL(RADEON_PPLL_CNTL));
1028 		DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1029 			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1030 			  pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1031 			  (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1032 
1033 		mdelay(50); /* Let the clock to lock */
1034 
1035 		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1036 			     RADEON_VCLK_SRC_SEL_PPLLCLK,
1037 			     ~(RADEON_VCLK_SRC_SEL_MASK));
1038 
1039 		if (is_tv)
1040 			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1041 	}
1042 }
1043 
1044 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1045 				   const struct drm_display_mode *mode,
1046 				   struct drm_display_mode *adjusted_mode)
1047 {
1048 	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1049 		return false;
1050 	return true;
1051 }
1052 
1053 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1054 				 struct drm_display_mode *mode,
1055 				 struct drm_display_mode *adjusted_mode,
1056 				 int x, int y, struct drm_framebuffer *old_fb)
1057 {
1058 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1059 
1060 	/* TODO TV */
1061 	radeon_crtc_set_base(crtc, x, y, old_fb);
1062 	radeon_set_crtc_timing(crtc, adjusted_mode);
1063 	radeon_set_pll(crtc, adjusted_mode);
1064 	radeon_overscan_setup(crtc, adjusted_mode);
1065 	if (radeon_crtc->crtc_id == 0) {
1066 		radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1067 	} else {
1068 		if (radeon_crtc->rmx_type != RMX_OFF) {
1069 			/* FIXME: only first crtc has rmx what should we
1070 			 * do ?
1071 			 */
1072 			DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1073 		}
1074 	}
1075 	radeon_cursor_reset(crtc);
1076 	return 0;
1077 }
1078 
1079 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1080 {
1081 	struct drm_device *dev = crtc->dev;
1082 	struct drm_crtc *crtci;
1083 
1084 	/*
1085 	* The hardware wedges sometimes if you reconfigure one CRTC
1086 	* whilst another is running (see fdo bug #24611).
1087 	*/
1088 	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1089 		radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1090 }
1091 
1092 static void radeon_crtc_commit(struct drm_crtc *crtc)
1093 {
1094 	struct drm_device *dev = crtc->dev;
1095 	struct drm_crtc *crtci;
1096 
1097 	/*
1098 	* Reenable the CRTCs that should be running.
1099 	*/
1100 	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1101 		if (crtci->enabled)
1102 			radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1103 	}
1104 }
1105 
1106 static void radeon_crtc_disable(struct drm_crtc *crtc)
1107 {
1108 	radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1109 	if (crtc->primary->fb) {
1110 		int r;
1111 		struct radeon_framebuffer *radeon_fb;
1112 		struct radeon_bo *rbo;
1113 
1114 		radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1115 		rbo = gem_to_radeon_bo(radeon_fb->obj);
1116 		r = radeon_bo_reserve(rbo, false);
1117 		if (unlikely(r))
1118 			DRM_ERROR("failed to reserve rbo before unpin\n");
1119 		else {
1120 			radeon_bo_unpin(rbo);
1121 			radeon_bo_unreserve(rbo);
1122 		}
1123 	}
1124 }
1125 
1126 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1127 	.dpms = radeon_crtc_dpms,
1128 	.mode_fixup = radeon_crtc_mode_fixup,
1129 	.mode_set = radeon_crtc_mode_set,
1130 	.mode_set_base = radeon_crtc_set_base,
1131 	.mode_set_base_atomic = radeon_crtc_set_base_atomic,
1132 	.prepare = radeon_crtc_prepare,
1133 	.commit = radeon_crtc_commit,
1134 	.load_lut = radeon_crtc_load_lut,
1135 	.disable = radeon_crtc_disable
1136 };
1137 
1138 
1139 void radeon_legacy_init_crtc(struct drm_device *dev,
1140 			       struct radeon_crtc *radeon_crtc)
1141 {
1142 	if (radeon_crtc->crtc_id == 1)
1143 		radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1144 	drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1145 }
1146