1 /* $NetBSD: radeon_cursor.c,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: radeon_cursor.c,v 1.2 2018/08/27 04:58:36 riastradh Exp $"); 30 31 #include <drm/drmP.h> 32 #include <drm/radeon_drm.h> 33 #include "radeon.h" 34 35 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) 36 { 37 struct radeon_device *rdev = crtc->dev->dev_private; 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 uint32_t cur_lock; 40 41 if (ASIC_IS_DCE4(rdev)) { 42 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); 43 if (lock) 44 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 45 else 46 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 47 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 48 } else if (ASIC_IS_AVIVO(rdev)) { 49 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); 50 if (lock) 51 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; 52 else 53 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; 54 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 55 } else { 56 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); 57 if (lock) 58 cur_lock |= RADEON_CUR_LOCK; 59 else 60 cur_lock &= ~RADEON_CUR_LOCK; 61 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); 62 } 63 } 64 65 static void radeon_hide_cursor(struct drm_crtc *crtc) 66 { 67 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 68 struct radeon_device *rdev = crtc->dev->dev_private; 69 70 if (ASIC_IS_DCE4(rdev)) { 71 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, 72 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 73 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 74 } else if (ASIC_IS_AVIVO(rdev)) { 75 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 76 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 77 } else { 78 u32 reg; 79 switch (radeon_crtc->crtc_id) { 80 case 0: 81 reg = RADEON_CRTC_GEN_CNTL; 82 break; 83 case 1: 84 reg = RADEON_CRTC2_GEN_CNTL; 85 break; 86 default: 87 return; 88 } 89 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); 90 } 91 } 92 93 static void radeon_show_cursor(struct drm_crtc *crtc) 94 { 95 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 96 struct radeon_device *rdev = crtc->dev->dev_private; 97 98 if (radeon_crtc->cursor_out_of_bounds) 99 return; 100 101 if (ASIC_IS_DCE4(rdev)) { 102 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 103 upper_32_bits(radeon_crtc->cursor_addr)); 104 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 105 lower_32_bits(radeon_crtc->cursor_addr)); 106 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 107 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 108 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 109 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 110 } else if (ASIC_IS_AVIVO(rdev)) { 111 if (rdev->family >= CHIP_RV770) { 112 if (radeon_crtc->crtc_id) 113 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 114 upper_32_bits(radeon_crtc->cursor_addr)); 115 else 116 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 117 upper_32_bits(radeon_crtc->cursor_addr)); 118 } 119 120 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 121 lower_32_bits(radeon_crtc->cursor_addr)); 122 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 123 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 124 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 125 } else { 126 /* offset is from DISP(2)_BASE_ADDRESS */ 127 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, 128 radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr); 129 130 switch (radeon_crtc->crtc_id) { 131 case 0: 132 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 133 break; 134 case 1: 135 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 136 break; 137 default: 138 return; 139 } 140 141 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | 142 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), 143 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); 144 } 145 } 146 147 static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y) 148 { 149 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 150 struct radeon_device *rdev = crtc->dev->dev_private; 151 int xorigin = 0, yorigin = 0; 152 int w = radeon_crtc->cursor_width; 153 154 radeon_crtc->cursor_x = x; 155 radeon_crtc->cursor_y = y; 156 157 if (ASIC_IS_AVIVO(rdev)) { 158 /* avivo cursor are offset into the total surface */ 159 x += crtc->x; 160 y += crtc->y; 161 } 162 163 if (x < 0) 164 xorigin = min(-x, radeon_crtc->max_cursor_width - 1); 165 if (y < 0) 166 yorigin = min(-y, radeon_crtc->max_cursor_height - 1); 167 168 if (!ASIC_IS_AVIVO(rdev)) { 169 x += crtc->x; 170 y += crtc->y; 171 } 172 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 173 174 /* fixed on DCE6 and newer */ 175 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) { 176 int i = 0; 177 struct drm_crtc *crtc_p; 178 179 /* 180 * avivo cursor image can't end on 128 pixel boundary or 181 * go past the end of the frame if both crtcs are enabled 182 * 183 * NOTE: It is safe to access crtc->enabled of other crtcs 184 * without holding either the mode_config lock or the other 185 * crtc's lock as long as write access to this flag _always_ 186 * grabs all locks. 187 */ 188 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { 189 if (crtc_p->enabled) 190 i++; 191 } 192 if (i > 1) { 193 int cursor_end, frame_end; 194 195 cursor_end = x + w; 196 frame_end = crtc->x + crtc->mode.crtc_hdisplay; 197 if (cursor_end >= frame_end) { 198 w = w - (cursor_end - frame_end); 199 if (!(frame_end & 0x7f)) 200 w--; 201 } else if (cursor_end <= 0) { 202 goto out_of_bounds; 203 } else if (!(cursor_end & 0x7f)) { 204 w--; 205 } 206 if (w <= 0) { 207 goto out_of_bounds; 208 } 209 } 210 } 211 212 if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) || 213 x >= (crtc->x + crtc->mode.hdisplay) || 214 y >= (crtc->y + crtc->mode.vdisplay)) 215 goto out_of_bounds; 216 217 x += xorigin; 218 y += yorigin; 219 220 if (ASIC_IS_DCE4(rdev)) { 221 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 222 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 223 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 224 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 225 } else if (ASIC_IS_AVIVO(rdev)) { 226 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 227 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 228 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 229 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 230 } else { 231 x -= crtc->x; 232 y -= crtc->y; 233 234 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 235 y *= 2; 236 237 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, 238 (RADEON_CUR_LOCK 239 | (xorigin << 16) 240 | yorigin)); 241 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 242 (RADEON_CUR_LOCK 243 | (x << 16) 244 | y)); 245 /* offset is from DISP(2)_BASE_ADDRESS */ 246 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, 247 radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr + 248 yorigin * 256); 249 } 250 251 if (radeon_crtc->cursor_out_of_bounds) { 252 radeon_crtc->cursor_out_of_bounds = false; 253 if (radeon_crtc->cursor_bo) 254 radeon_show_cursor(crtc); 255 } 256 257 return 0; 258 259 out_of_bounds: 260 if (!radeon_crtc->cursor_out_of_bounds) { 261 radeon_hide_cursor(crtc); 262 radeon_crtc->cursor_out_of_bounds = true; 263 } 264 return 0; 265 } 266 267 int radeon_crtc_cursor_move(struct drm_crtc *crtc, 268 int x, int y) 269 { 270 int ret; 271 272 radeon_lock_cursor(crtc, true); 273 ret = radeon_cursor_move_locked(crtc, x, y); 274 radeon_lock_cursor(crtc, false); 275 276 return ret; 277 } 278 279 int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 280 struct drm_file *file_priv, 281 uint32_t handle, 282 uint32_t width, 283 uint32_t height, 284 int32_t hot_x, 285 int32_t hot_y) 286 { 287 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 288 struct radeon_device *rdev = crtc->dev->dev_private; 289 struct drm_gem_object *obj; 290 struct radeon_bo *robj; 291 int ret; 292 293 if (!handle) { 294 /* turn off cursor */ 295 radeon_hide_cursor(crtc); 296 obj = NULL; 297 goto unpin; 298 } 299 300 if ((width > radeon_crtc->max_cursor_width) || 301 (height > radeon_crtc->max_cursor_height)) { 302 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 303 return -EINVAL; 304 } 305 306 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 307 if (!obj) { 308 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 309 return -ENOENT; 310 } 311 312 robj = gem_to_radeon_bo(obj); 313 ret = radeon_bo_reserve(robj, false); 314 if (ret != 0) { 315 drm_gem_object_unreference_unlocked(obj); 316 return ret; 317 } 318 /* Only 27 bit offset for legacy cursor */ 319 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, 320 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 321 &radeon_crtc->cursor_addr); 322 radeon_bo_unreserve(robj); 323 if (ret) { 324 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 325 drm_gem_object_unreference_unlocked(obj); 326 return ret; 327 } 328 329 radeon_lock_cursor(crtc, true); 330 331 if (width != radeon_crtc->cursor_width || 332 height != radeon_crtc->cursor_height || 333 hot_x != radeon_crtc->cursor_hot_x || 334 hot_y != radeon_crtc->cursor_hot_y) { 335 int x, y; 336 337 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x; 338 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y; 339 340 radeon_crtc->cursor_width = width; 341 radeon_crtc->cursor_height = height; 342 radeon_crtc->cursor_hot_x = hot_x; 343 radeon_crtc->cursor_hot_y = hot_y; 344 345 radeon_cursor_move_locked(crtc, x, y); 346 } 347 348 radeon_show_cursor(crtc); 349 350 radeon_lock_cursor(crtc, false); 351 352 unpin: 353 if (radeon_crtc->cursor_bo) { 354 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 355 ret = radeon_bo_reserve(robj, false); 356 if (likely(ret == 0)) { 357 radeon_bo_unpin(robj); 358 radeon_bo_unreserve(robj); 359 } 360 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); 361 } 362 363 radeon_crtc->cursor_bo = obj; 364 return 0; 365 } 366 367 /** 368 * radeon_cursor_reset - Re-set the current cursor, if any. 369 * 370 * @crtc: drm crtc 371 * 372 * If the CRTC passed in currently has a cursor assigned, this function 373 * makes sure it's visible. 374 */ 375 void radeon_cursor_reset(struct drm_crtc *crtc) 376 { 377 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 378 379 if (radeon_crtc->cursor_bo) { 380 radeon_lock_cursor(crtc, true); 381 382 radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x, 383 radeon_crtc->cursor_y); 384 385 radeon_show_cursor(crtc); 386 387 radeon_lock_cursor(crtc, false); 388 } 389 } 390