1 /* $NetBSD: radeon_atombios.c,v 1.3 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: radeon_atombios.c,v 1.3 2018/08/27 04:58:36 riastradh Exp $"); 30 31 #include <drm/drmP.h> 32 #include <drm/radeon_drm.h> 33 #include "radeon.h" 34 35 #include "atom.h" 36 #include "atom-bits.h" 37 38 extern void 39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 40 uint32_t supported_device, u16 caps); 41 42 /* from radeon_legacy_encoder.c */ 43 extern void 44 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 45 uint32_t supported_device); 46 47 union atom_supported_devices { 48 struct _ATOM_SUPPORTED_DEVICES_INFO info; 49 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 50 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 51 }; 52 53 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 54 ATOM_GPIO_I2C_ASSIGMENT *gpio, 55 u8 index) 56 { 57 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 58 if ((rdev->family == CHIP_R420) || 59 (rdev->family == CHIP_R423) || 60 (rdev->family == CHIP_RV410)) { 61 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 62 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 63 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 64 gpio->ucClkMaskShift = 0x19; 65 gpio->ucDataMaskShift = 0x18; 66 } 67 } 68 69 /* some evergreen boards have bad data for this entry */ 70 if (ASIC_IS_DCE4(rdev)) { 71 if ((index == 7) && 72 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 73 (gpio->sucI2cId.ucAccess == 0)) { 74 gpio->sucI2cId.ucAccess = 0x97; 75 gpio->ucDataMaskShift = 8; 76 gpio->ucDataEnShift = 8; 77 gpio->ucDataY_Shift = 8; 78 gpio->ucDataA_Shift = 8; 79 } 80 } 81 82 /* some DCE3 boards have bad data for this entry */ 83 if (ASIC_IS_DCE3(rdev)) { 84 if ((index == 4) && 85 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 86 (gpio->sucI2cId.ucAccess == 0x94)) 87 gpio->sucI2cId.ucAccess = 0x14; 88 } 89 } 90 91 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 92 { 93 struct radeon_i2c_bus_rec i2c; 94 95 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 96 97 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 98 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 99 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 100 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 101 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 102 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 103 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 104 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 105 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 106 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 107 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 108 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 109 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 110 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 111 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 112 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 113 114 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 115 i2c.hw_capable = true; 116 else 117 i2c.hw_capable = false; 118 119 if (gpio->sucI2cId.ucAccess == 0xa0) 120 i2c.mm_i2c = true; 121 else 122 i2c.mm_i2c = false; 123 124 i2c.i2c_id = gpio->sucI2cId.ucAccess; 125 126 if (i2c.mask_clk_reg) 127 i2c.valid = true; 128 else 129 i2c.valid = false; 130 131 return i2c; 132 } 133 134 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 135 uint8_t id) 136 { 137 struct atom_context *ctx = rdev->mode_info.atom_context; 138 ATOM_GPIO_I2C_ASSIGMENT *gpio; 139 struct radeon_i2c_bus_rec i2c; 140 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 141 struct _ATOM_GPIO_I2C_INFO *i2c_info; 142 uint16_t data_offset, size; 143 int i, num_indices; 144 145 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 146 i2c.valid = false; 147 148 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 149 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 150 151 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 152 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 153 154 gpio = &i2c_info->asGPIO_Info[0]; 155 for (i = 0; i < num_indices; i++) { 156 157 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 158 159 if (gpio->sucI2cId.ucAccess == id) { 160 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 161 break; 162 } 163 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 164 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 165 } 166 } 167 168 return i2c; 169 } 170 171 void radeon_atombios_i2c_init(struct radeon_device *rdev) 172 { 173 struct atom_context *ctx = rdev->mode_info.atom_context; 174 ATOM_GPIO_I2C_ASSIGMENT *gpio; 175 struct radeon_i2c_bus_rec i2c; 176 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 177 struct _ATOM_GPIO_I2C_INFO *i2c_info; 178 uint16_t data_offset, size; 179 int i, num_indices; 180 char stmp[32]; 181 182 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 183 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 184 185 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 186 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 187 188 gpio = &i2c_info->asGPIO_Info[0]; 189 for (i = 0; i < num_indices; i++) { 190 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 191 192 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 193 194 if (i2c.valid) { 195 snprintf(stmp, sizeof stmp, "0x%x", i2c.i2c_id); 196 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 197 } 198 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 199 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 200 } 201 } 202 } 203 204 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 205 u8 id) 206 { 207 struct atom_context *ctx = rdev->mode_info.atom_context; 208 struct radeon_gpio_rec gpio; 209 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 210 struct _ATOM_GPIO_PIN_LUT *gpio_info; 211 ATOM_GPIO_PIN_ASSIGNMENT *pin; 212 u16 data_offset, size; 213 int i, num_indices; 214 215 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 216 gpio.valid = false; 217 218 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 219 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 220 221 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 222 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 223 224 pin = gpio_info->asGPIO_Pin; 225 for (i = 0; i < num_indices; i++) { 226 if (id == pin->ucGPIO_ID) { 227 gpio.id = pin->ucGPIO_ID; 228 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 229 gpio.shift = pin->ucGpioPinBitShift; 230 gpio.mask = (1 << pin->ucGpioPinBitShift); 231 gpio.valid = true; 232 break; 233 } 234 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 235 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 236 } 237 } 238 239 return gpio; 240 } 241 242 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 243 struct radeon_gpio_rec *gpio) 244 { 245 struct radeon_hpd hpd; 246 u32 reg; 247 248 memset(&hpd, 0, sizeof(struct radeon_hpd)); 249 250 if (ASIC_IS_DCE6(rdev)) 251 reg = SI_DC_GPIO_HPD_A; 252 else if (ASIC_IS_DCE4(rdev)) 253 reg = EVERGREEN_DC_GPIO_HPD_A; 254 else 255 reg = AVIVO_DC_GPIO_HPD_A; 256 257 hpd.gpio = *gpio; 258 if (gpio->reg == reg) { 259 switch(gpio->mask) { 260 case (1 << 0): 261 hpd.hpd = RADEON_HPD_1; 262 break; 263 case (1 << 8): 264 hpd.hpd = RADEON_HPD_2; 265 break; 266 case (1 << 16): 267 hpd.hpd = RADEON_HPD_3; 268 break; 269 case (1 << 24): 270 hpd.hpd = RADEON_HPD_4; 271 break; 272 case (1 << 26): 273 hpd.hpd = RADEON_HPD_5; 274 break; 275 case (1 << 28): 276 hpd.hpd = RADEON_HPD_6; 277 break; 278 default: 279 hpd.hpd = RADEON_HPD_NONE; 280 break; 281 } 282 } else 283 hpd.hpd = RADEON_HPD_NONE; 284 return hpd; 285 } 286 287 static bool radeon_atom_apply_quirks(struct drm_device *dev, 288 uint32_t supported_device, 289 int *connector_type, 290 struct radeon_i2c_bus_rec *i2c_bus, 291 uint16_t *line_mux, 292 struct radeon_hpd *hpd) 293 { 294 295 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 296 if ((dev->pdev->device == 0x791e) && 297 (dev->pdev->subsystem_vendor == 0x1043) && 298 (dev->pdev->subsystem_device == 0x826d)) { 299 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 300 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 301 *connector_type = DRM_MODE_CONNECTOR_DVID; 302 } 303 304 /* Asrock RS600 board lists the DVI port as HDMI */ 305 if ((dev->pdev->device == 0x7941) && 306 (dev->pdev->subsystem_vendor == 0x1849) && 307 (dev->pdev->subsystem_device == 0x7941)) { 308 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 309 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 310 *connector_type = DRM_MODE_CONNECTOR_DVID; 311 } 312 313 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 314 if ((dev->pdev->device == 0x796e) && 315 (dev->pdev->subsystem_vendor == 0x1462) && 316 (dev->pdev->subsystem_device == 0x7302)) { 317 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 318 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 319 return false; 320 } 321 322 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 323 if ((dev->pdev->device == 0x7941) && 324 (dev->pdev->subsystem_vendor == 0x147b) && 325 (dev->pdev->subsystem_device == 0x2412)) { 326 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 327 return false; 328 } 329 330 /* Falcon NW laptop lists vga ddc line for LVDS */ 331 if ((dev->pdev->device == 0x5653) && 332 (dev->pdev->subsystem_vendor == 0x1462) && 333 (dev->pdev->subsystem_device == 0x0291)) { 334 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 335 i2c_bus->valid = false; 336 *line_mux = 53; 337 } 338 } 339 340 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 341 if ((dev->pdev->device == 0x7146) && 342 (dev->pdev->subsystem_vendor == 0x17af) && 343 (dev->pdev->subsystem_device == 0x2058)) { 344 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 345 return false; 346 } 347 348 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 349 if ((dev->pdev->device == 0x7142) && 350 (dev->pdev->subsystem_vendor == 0x1458) && 351 (dev->pdev->subsystem_device == 0x2134)) { 352 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 353 return false; 354 } 355 356 357 /* Funky macbooks */ 358 if ((dev->pdev->device == 0x71C5) && 359 (dev->pdev->subsystem_vendor == 0x106b) && 360 (dev->pdev->subsystem_device == 0x0080)) { 361 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 362 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 363 return false; 364 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 365 *line_mux = 0x90; 366 } 367 368 /* mac rv630, rv730, others */ 369 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 370 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 371 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 372 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 373 } 374 375 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 376 if ((dev->pdev->device == 0x9598) && 377 (dev->pdev->subsystem_vendor == 0x1043) && 378 (dev->pdev->subsystem_device == 0x01da)) { 379 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 380 *connector_type = DRM_MODE_CONNECTOR_DVII; 381 } 382 } 383 384 /* ASUS HD 3600 board lists the DVI port as HDMI */ 385 if ((dev->pdev->device == 0x9598) && 386 (dev->pdev->subsystem_vendor == 0x1043) && 387 (dev->pdev->subsystem_device == 0x01e4)) { 388 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 389 *connector_type = DRM_MODE_CONNECTOR_DVII; 390 } 391 } 392 393 /* ASUS HD 3450 board lists the DVI port as HDMI */ 394 if ((dev->pdev->device == 0x95C5) && 395 (dev->pdev->subsystem_vendor == 0x1043) && 396 (dev->pdev->subsystem_device == 0x01e2)) { 397 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 398 *connector_type = DRM_MODE_CONNECTOR_DVII; 399 } 400 } 401 402 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 403 * HDMI + VGA reporting as HDMI 404 */ 405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 406 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 407 *connector_type = DRM_MODE_CONNECTOR_VGA; 408 *line_mux = 0; 409 } 410 } 411 412 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 413 * on the laptop and a DVI port on the docking station and 414 * both share the same encoder, hpd pin, and ddc line. 415 * So while the bios table is technically correct, 416 * we drop the DVI port here since xrandr has no concept of 417 * encoders and will try and drive both connectors 418 * with different crtcs which isn't possible on the hardware 419 * side and leaves no crtcs for LVDS or VGA. 420 */ 421 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && 422 (dev->pdev->subsystem_vendor == 0x1025) && 423 (dev->pdev->subsystem_device == 0x013c)) { 424 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 425 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 426 /* actually it's a DVI-D port not DVI-I */ 427 *connector_type = DRM_MODE_CONNECTOR_DVID; 428 return false; 429 } 430 } 431 432 /* XFX Pine Group device rv730 reports no VGA DDC lines 433 * even though they are wired up to record 0x93 434 */ 435 if ((dev->pdev->device == 0x9498) && 436 (dev->pdev->subsystem_vendor == 0x1682) && 437 (dev->pdev->subsystem_device == 0x2452) && 438 (i2c_bus->valid == false) && 439 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 440 struct radeon_device *rdev = dev->dev_private; 441 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 442 } 443 444 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 445 if (((dev->pdev->device == 0x9802) || 446 (dev->pdev->device == 0x9805) || 447 (dev->pdev->device == 0x9806)) && 448 (dev->pdev->subsystem_vendor == 0x1734) && 449 (dev->pdev->subsystem_device == 0x11bd)) { 450 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 451 *connector_type = DRM_MODE_CONNECTOR_DVII; 452 *line_mux = 0x3103; 453 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 454 *connector_type = DRM_MODE_CONNECTOR_DVII; 455 } 456 } 457 458 return true; 459 } 460 461 static const int supported_devices_connector_convert[] = { 462 DRM_MODE_CONNECTOR_Unknown, 463 DRM_MODE_CONNECTOR_VGA, 464 DRM_MODE_CONNECTOR_DVII, 465 DRM_MODE_CONNECTOR_DVID, 466 DRM_MODE_CONNECTOR_DVIA, 467 DRM_MODE_CONNECTOR_SVIDEO, 468 DRM_MODE_CONNECTOR_Composite, 469 DRM_MODE_CONNECTOR_LVDS, 470 DRM_MODE_CONNECTOR_Unknown, 471 DRM_MODE_CONNECTOR_Unknown, 472 DRM_MODE_CONNECTOR_HDMIA, 473 DRM_MODE_CONNECTOR_HDMIB, 474 DRM_MODE_CONNECTOR_Unknown, 475 DRM_MODE_CONNECTOR_Unknown, 476 DRM_MODE_CONNECTOR_9PinDIN, 477 DRM_MODE_CONNECTOR_DisplayPort 478 }; 479 480 static const uint16_t supported_devices_connector_object_id_convert[] = { 481 CONNECTOR_OBJECT_ID_NONE, 482 CONNECTOR_OBJECT_ID_VGA, 483 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 484 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 485 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 486 CONNECTOR_OBJECT_ID_COMPOSITE, 487 CONNECTOR_OBJECT_ID_SVIDEO, 488 CONNECTOR_OBJECT_ID_LVDS, 489 CONNECTOR_OBJECT_ID_9PIN_DIN, 490 CONNECTOR_OBJECT_ID_9PIN_DIN, 491 CONNECTOR_OBJECT_ID_DISPLAYPORT, 492 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 493 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 494 CONNECTOR_OBJECT_ID_SVIDEO 495 }; 496 497 static const int object_connector_convert[] = { 498 DRM_MODE_CONNECTOR_Unknown, 499 DRM_MODE_CONNECTOR_DVII, 500 DRM_MODE_CONNECTOR_DVII, 501 DRM_MODE_CONNECTOR_DVID, 502 DRM_MODE_CONNECTOR_DVID, 503 DRM_MODE_CONNECTOR_VGA, 504 DRM_MODE_CONNECTOR_Composite, 505 DRM_MODE_CONNECTOR_SVIDEO, 506 DRM_MODE_CONNECTOR_Unknown, 507 DRM_MODE_CONNECTOR_Unknown, 508 DRM_MODE_CONNECTOR_9PinDIN, 509 DRM_MODE_CONNECTOR_Unknown, 510 DRM_MODE_CONNECTOR_HDMIA, 511 DRM_MODE_CONNECTOR_HDMIB, 512 DRM_MODE_CONNECTOR_LVDS, 513 DRM_MODE_CONNECTOR_9PinDIN, 514 DRM_MODE_CONNECTOR_Unknown, 515 DRM_MODE_CONNECTOR_Unknown, 516 DRM_MODE_CONNECTOR_Unknown, 517 DRM_MODE_CONNECTOR_DisplayPort, 518 DRM_MODE_CONNECTOR_eDP, 519 DRM_MODE_CONNECTOR_Unknown 520 }; 521 522 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 523 { 524 struct radeon_device *rdev = dev->dev_private; 525 struct radeon_mode_info *mode_info = &rdev->mode_info; 526 struct atom_context *ctx = mode_info->atom_context; 527 int index = GetIndexIntoMasterTable(DATA, Object_Header); 528 u16 size, data_offset; 529 u8 frev, crev; 530 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 531 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 532 ATOM_OBJECT_TABLE *router_obj; 533 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 534 ATOM_OBJECT_HEADER *obj_header; 535 int i, j, k, path_size, device_support; 536 int connector_type; 537 u16 igp_lane_info, conn_id, connector_object_id; 538 struct radeon_i2c_bus_rec ddc_bus; 539 struct radeon_router router; 540 struct radeon_gpio_rec gpio; 541 struct radeon_hpd hpd; 542 543 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 544 return false; 545 546 if (crev < 2) 547 return false; 548 549 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 550 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 551 (ctx->bios + data_offset + 552 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 553 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 554 (ctx->bios + data_offset + 555 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 556 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 557 (ctx->bios + data_offset + 558 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 559 router_obj = (ATOM_OBJECT_TABLE *) 560 (ctx->bios + data_offset + 561 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 562 device_support = le16_to_cpu(obj_header->usDeviceSupport); 563 564 path_size = 0; 565 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 566 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 567 ATOM_DISPLAY_OBJECT_PATH *path; 568 addr += path_size; 569 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 570 path_size += le16_to_cpu(path->usSize); 571 572 if (device_support & le16_to_cpu(path->usDeviceTag)) { 573 uint8_t con_obj_id, con_obj_num, con_obj_type __unused; 574 575 con_obj_id = 576 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 577 >> OBJECT_ID_SHIFT; 578 con_obj_num = 579 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 580 >> ENUM_ID_SHIFT; 581 con_obj_type = 582 (le16_to_cpu(path->usConnObjectId) & 583 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 584 585 /* TODO CV support */ 586 if (le16_to_cpu(path->usDeviceTag) == 587 ATOM_DEVICE_CV_SUPPORT) 588 continue; 589 590 /* IGP chips */ 591 if ((rdev->flags & RADEON_IS_IGP) && 592 (con_obj_id == 593 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 594 uint16_t igp_offset = 0; 595 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 596 597 index = 598 GetIndexIntoMasterTable(DATA, 599 IntegratedSystemInfo); 600 601 if (atom_parse_data_header(ctx, index, &size, &frev, 602 &crev, &igp_offset)) { 603 604 if (crev >= 2) { 605 igp_obj = 606 (ATOM_INTEGRATED_SYSTEM_INFO_V2 607 *) (ctx->bios + igp_offset); 608 609 if (igp_obj) { 610 uint32_t slot_config, ct; 611 612 if (con_obj_num == 1) 613 slot_config = 614 igp_obj-> 615 ulDDISlot1Config; 616 else 617 slot_config = 618 igp_obj-> 619 ulDDISlot2Config; 620 621 ct = (slot_config >> 16) & 0xff; 622 connector_type = 623 object_connector_convert 624 [ct]; 625 connector_object_id = ct; 626 igp_lane_info = 627 slot_config & 0xffff; 628 } else 629 continue; 630 } else 631 continue; 632 } else { 633 igp_lane_info = 0; 634 connector_type = 635 object_connector_convert[con_obj_id]; 636 connector_object_id = con_obj_id; 637 } 638 } else { 639 igp_lane_info = 0; 640 connector_type = 641 object_connector_convert[con_obj_id]; 642 connector_object_id = con_obj_id; 643 } 644 645 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 646 continue; 647 648 router.ddc_valid = false; 649 router.cd_valid = false; 650 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 651 uint8_t grph_obj_id __unused, grph_obj_num __unused, grph_obj_type; 652 653 grph_obj_id = 654 (le16_to_cpu(path->usGraphicObjIds[j]) & 655 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 656 grph_obj_num = 657 (le16_to_cpu(path->usGraphicObjIds[j]) & 658 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 659 grph_obj_type = 660 (le16_to_cpu(path->usGraphicObjIds[j]) & 661 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 662 663 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 664 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 665 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 666 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 667 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 668 (ctx->bios + data_offset + 669 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 670 ATOM_ENCODER_CAP_RECORD *cap_record; 671 u16 caps = 0; 672 673 while (record->ucRecordSize > 0 && 674 record->ucRecordType > 0 && 675 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 676 switch (record->ucRecordType) { 677 case ATOM_ENCODER_CAP_RECORD_TYPE: 678 cap_record =(ATOM_ENCODER_CAP_RECORD *) 679 record; 680 caps = le16_to_cpu(cap_record->usEncoderCap); 681 break; 682 } 683 record = (ATOM_COMMON_RECORD_HEADER *) 684 ((char *)record + record->ucRecordSize); 685 } 686 radeon_add_atom_encoder(dev, 687 encoder_obj, 688 le16_to_cpu 689 (path-> 690 usDeviceTag), 691 caps); 692 } 693 } 694 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 695 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 696 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 697 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 698 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 699 (ctx->bios + data_offset + 700 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 701 ATOM_I2C_RECORD *i2c_record; 702 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 703 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 704 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 705 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 706 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 707 (ctx->bios + data_offset + 708 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 709 u8 *num_dst_objs = (u8 *) 710 ((u8 *)router_src_dst_table + 1 + 711 (router_src_dst_table->ucNumberOfSrc * 2)); 712 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 713 int enum_id; 714 715 router.router_id = router_obj_id; 716 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 717 if (le16_to_cpu(path->usConnObjectId) == 718 le16_to_cpu(dst_objs[enum_id])) 719 break; 720 } 721 722 while (record->ucRecordSize > 0 && 723 record->ucRecordType > 0 && 724 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 725 switch (record->ucRecordType) { 726 case ATOM_I2C_RECORD_TYPE: 727 i2c_record = 728 (ATOM_I2C_RECORD *) 729 record; 730 i2c_config = 731 (ATOM_I2C_ID_CONFIG_ACCESS *) 732 &i2c_record->sucI2cId; 733 router.i2c_info = 734 radeon_lookup_i2c_gpio(rdev, 735 i2c_config-> 736 ucAccess); 737 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 738 break; 739 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 740 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 741 record; 742 router.ddc_valid = true; 743 router.ddc_mux_type = ddc_path->ucMuxType; 744 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 745 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 746 break; 747 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 748 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 749 record; 750 router.cd_valid = true; 751 router.cd_mux_type = cd_path->ucMuxType; 752 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 753 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 754 break; 755 } 756 record = (ATOM_COMMON_RECORD_HEADER *) 757 ((char *)record + record->ucRecordSize); 758 } 759 } 760 } 761 } 762 } 763 764 /* look up gpio for ddc, hpd */ 765 ddc_bus.valid = false; 766 hpd.hpd = RADEON_HPD_NONE; 767 if ((le16_to_cpu(path->usDeviceTag) & 768 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 769 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 770 if (le16_to_cpu(path->usConnObjectId) == 771 le16_to_cpu(con_obj->asObjects[j]. 772 usObjectID)) { 773 ATOM_COMMON_RECORD_HEADER 774 *record = 775 (ATOM_COMMON_RECORD_HEADER 776 *) 777 (ctx->bios + data_offset + 778 le16_to_cpu(con_obj-> 779 asObjects[j]. 780 usRecordOffset)); 781 ATOM_I2C_RECORD *i2c_record; 782 ATOM_HPD_INT_RECORD *hpd_record; 783 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 784 785 while (record->ucRecordSize > 0 && 786 record->ucRecordType > 0 && 787 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 788 switch (record->ucRecordType) { 789 case ATOM_I2C_RECORD_TYPE: 790 i2c_record = 791 (ATOM_I2C_RECORD *) 792 record; 793 i2c_config = 794 (ATOM_I2C_ID_CONFIG_ACCESS *) 795 &i2c_record->sucI2cId; 796 ddc_bus = radeon_lookup_i2c_gpio(rdev, 797 i2c_config-> 798 ucAccess); 799 break; 800 case ATOM_HPD_INT_RECORD_TYPE: 801 hpd_record = 802 (ATOM_HPD_INT_RECORD *) 803 record; 804 gpio = radeon_atombios_lookup_gpio(rdev, 805 hpd_record->ucHPDIntGPIOID); 806 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 807 hpd.plugged_state = hpd_record->ucPlugged_PinState; 808 break; 809 } 810 record = 811 (ATOM_COMMON_RECORD_HEADER 812 *) ((char *)record 813 + 814 record-> 815 ucRecordSize); 816 } 817 break; 818 } 819 } 820 } 821 822 /* needed for aux chan transactions */ 823 ddc_bus.hpd = hpd.hpd; 824 825 conn_id = le16_to_cpu(path->usConnObjectId); 826 827 if (!radeon_atom_apply_quirks 828 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 829 &ddc_bus, &conn_id, &hpd)) 830 continue; 831 832 radeon_add_atom_connector(dev, 833 conn_id, 834 le16_to_cpu(path-> 835 usDeviceTag), 836 connector_type, &ddc_bus, 837 igp_lane_info, 838 connector_object_id, 839 &hpd, 840 &router); 841 842 } 843 } 844 845 radeon_link_encoder_connector(dev); 846 847 radeon_setup_mst_connector(dev); 848 return true; 849 } 850 851 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 852 int connector_type, 853 uint16_t devices) 854 { 855 struct radeon_device *rdev = dev->dev_private; 856 857 if (rdev->flags & RADEON_IS_IGP) { 858 return supported_devices_connector_object_id_convert 859 [connector_type]; 860 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 861 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 862 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 863 struct radeon_mode_info *mode_info = &rdev->mode_info; 864 struct atom_context *ctx = mode_info->atom_context; 865 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 866 uint16_t size, data_offset; 867 uint8_t frev, crev; 868 ATOM_XTMDS_INFO *xtmds; 869 870 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 871 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 872 873 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 874 if (connector_type == DRM_MODE_CONNECTOR_DVII) 875 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 876 else 877 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 878 } else { 879 if (connector_type == DRM_MODE_CONNECTOR_DVII) 880 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 881 else 882 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 883 } 884 } else 885 return supported_devices_connector_object_id_convert 886 [connector_type]; 887 } else { 888 return supported_devices_connector_object_id_convert 889 [connector_type]; 890 } 891 } 892 893 struct bios_connector { 894 bool valid; 895 uint16_t line_mux; 896 uint16_t devices; 897 int connector_type; 898 struct radeon_i2c_bus_rec ddc_bus; 899 struct radeon_hpd hpd; 900 }; 901 902 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 903 drm_device 904 *dev) 905 { 906 struct radeon_device *rdev = dev->dev_private; 907 struct radeon_mode_info *mode_info = &rdev->mode_info; 908 struct atom_context *ctx = mode_info->atom_context; 909 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 910 uint16_t size, data_offset; 911 uint8_t frev, crev; 912 uint16_t device_support; 913 uint8_t dac; 914 union atom_supported_devices *supported_devices; 915 int i, j, max_device; 916 struct bios_connector *bios_connectors; 917 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 918 struct radeon_router router; 919 920 router.ddc_valid = false; 921 router.cd_valid = false; 922 923 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 924 if (!bios_connectors) 925 return false; 926 927 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 928 &data_offset)) { 929 kfree(bios_connectors); 930 return false; 931 } 932 933 supported_devices = 934 (union atom_supported_devices *)(ctx->bios + data_offset); 935 936 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 937 938 if (frev > 1) 939 max_device = ATOM_MAX_SUPPORTED_DEVICE; 940 else 941 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 942 943 for (i = 0; i < max_device; i++) { 944 ATOM_CONNECTOR_INFO_I2C ci = 945 supported_devices->info.asConnInfo[i]; 946 947 bios_connectors[i].valid = false; 948 949 if (!(device_support & (1 << i))) { 950 continue; 951 } 952 953 if (i == ATOM_DEVICE_CV_INDEX) { 954 DRM_DEBUG_KMS("Skipping Component Video\n"); 955 continue; 956 } 957 958 bios_connectors[i].connector_type = 959 supported_devices_connector_convert[ci.sucConnectorInfo. 960 sbfAccess. 961 bfConnectorType]; 962 963 if (bios_connectors[i].connector_type == 964 DRM_MODE_CONNECTOR_Unknown) 965 continue; 966 967 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 968 969 bios_connectors[i].line_mux = 970 ci.sucI2cId.ucAccess; 971 972 /* give tv unique connector ids */ 973 if (i == ATOM_DEVICE_TV1_INDEX) { 974 bios_connectors[i].ddc_bus.valid = false; 975 bios_connectors[i].line_mux = 50; 976 } else if (i == ATOM_DEVICE_TV2_INDEX) { 977 bios_connectors[i].ddc_bus.valid = false; 978 bios_connectors[i].line_mux = 51; 979 } else if (i == ATOM_DEVICE_CV_INDEX) { 980 bios_connectors[i].ddc_bus.valid = false; 981 bios_connectors[i].line_mux = 52; 982 } else 983 bios_connectors[i].ddc_bus = 984 radeon_lookup_i2c_gpio(rdev, 985 bios_connectors[i].line_mux); 986 987 if ((crev > 1) && (frev > 1)) { 988 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 989 switch (isb) { 990 case 0x4: 991 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 992 break; 993 case 0xa: 994 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 995 break; 996 default: 997 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 998 break; 999 } 1000 } else { 1001 if (i == ATOM_DEVICE_DFP1_INDEX) 1002 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 1003 else if (i == ATOM_DEVICE_DFP2_INDEX) 1004 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 1005 else 1006 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 1007 } 1008 1009 /* Always set the connector type to VGA for CRT1/CRT2. if they are 1010 * shared with a DVI port, we'll pick up the DVI connector when we 1011 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 1012 */ 1013 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1014 bios_connectors[i].connector_type = 1015 DRM_MODE_CONNECTOR_VGA; 1016 1017 if (!radeon_atom_apply_quirks 1018 (dev, (1 << i), &bios_connectors[i].connector_type, 1019 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1020 &bios_connectors[i].hpd)) 1021 continue; 1022 1023 bios_connectors[i].valid = true; 1024 bios_connectors[i].devices = (1 << i); 1025 1026 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1027 radeon_add_atom_encoder(dev, 1028 radeon_get_encoder_enum(dev, 1029 (1 << i), 1030 dac), 1031 (1 << i), 1032 0); 1033 else 1034 radeon_add_legacy_encoder(dev, 1035 radeon_get_encoder_enum(dev, 1036 (1 << i), 1037 dac), 1038 (1 << i)); 1039 } 1040 1041 /* combine shared connectors */ 1042 for (i = 0; i < max_device; i++) { 1043 if (bios_connectors[i].valid) { 1044 for (j = 0; j < max_device; j++) { 1045 if (bios_connectors[j].valid && (i != j)) { 1046 if (bios_connectors[i].line_mux == 1047 bios_connectors[j].line_mux) { 1048 /* make sure not to combine LVDS */ 1049 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1050 bios_connectors[i].line_mux = 53; 1051 bios_connectors[i].ddc_bus.valid = false; 1052 continue; 1053 } 1054 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1055 bios_connectors[j].line_mux = 53; 1056 bios_connectors[j].ddc_bus.valid = false; 1057 continue; 1058 } 1059 /* combine analog and digital for DVI-I */ 1060 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1061 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1062 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1063 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1064 bios_connectors[i].devices |= 1065 bios_connectors[j].devices; 1066 bios_connectors[i].connector_type = 1067 DRM_MODE_CONNECTOR_DVII; 1068 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1069 bios_connectors[i].hpd = 1070 bios_connectors[j].hpd; 1071 bios_connectors[j].valid = false; 1072 } 1073 } 1074 } 1075 } 1076 } 1077 } 1078 1079 /* add the connectors */ 1080 for (i = 0; i < max_device; i++) { 1081 if (bios_connectors[i].valid) { 1082 uint16_t connector_object_id = 1083 atombios_get_connector_object_id(dev, 1084 bios_connectors[i].connector_type, 1085 bios_connectors[i].devices); 1086 radeon_add_atom_connector(dev, 1087 bios_connectors[i].line_mux, 1088 bios_connectors[i].devices, 1089 bios_connectors[i]. 1090 connector_type, 1091 &bios_connectors[i].ddc_bus, 1092 0, 1093 connector_object_id, 1094 &bios_connectors[i].hpd, 1095 &router); 1096 } 1097 } 1098 1099 radeon_link_encoder_connector(dev); 1100 1101 kfree(bios_connectors); 1102 return true; 1103 } 1104 1105 union firmware_info { 1106 ATOM_FIRMWARE_INFO info; 1107 ATOM_FIRMWARE_INFO_V1_2 info_12; 1108 ATOM_FIRMWARE_INFO_V1_3 info_13; 1109 ATOM_FIRMWARE_INFO_V1_4 info_14; 1110 ATOM_FIRMWARE_INFO_V2_1 info_21; 1111 ATOM_FIRMWARE_INFO_V2_2 info_22; 1112 }; 1113 1114 union igp_info { 1115 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1116 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1117 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1118 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1119 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1120 }; 1121 1122 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) 1123 { 1124 struct radeon_mode_info *mode_info = &rdev->mode_info; 1125 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1126 union igp_info *igp_info; 1127 u8 frev, crev; 1128 u16 data_offset; 1129 1130 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1131 &frev, &crev, &data_offset)) { 1132 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1133 data_offset); 1134 rdev->clock.vco_freq = 1135 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); 1136 } 1137 } 1138 1139 bool radeon_atom_get_clock_info(struct drm_device *dev) 1140 { 1141 struct radeon_device *rdev = dev->dev_private; 1142 struct radeon_mode_info *mode_info = &rdev->mode_info; 1143 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1144 union firmware_info *firmware_info; 1145 uint8_t frev, crev; 1146 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1147 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1148 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1149 struct radeon_pll *spll = &rdev->clock.spll; 1150 struct radeon_pll *mpll = &rdev->clock.mpll; 1151 uint16_t data_offset; 1152 1153 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1154 &frev, &crev, &data_offset)) { 1155 firmware_info = 1156 (union firmware_info *)(mode_info->atom_context->bios + 1157 data_offset); 1158 /* pixel clocks */ 1159 p1pll->reference_freq = 1160 le16_to_cpu(firmware_info->info.usReferenceClock); 1161 p1pll->reference_div = 0; 1162 1163 if ((frev < 2) && (crev < 2)) 1164 p1pll->pll_out_min = 1165 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1166 else 1167 p1pll->pll_out_min = 1168 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1169 p1pll->pll_out_max = 1170 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1171 1172 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { 1173 p1pll->lcd_pll_out_min = 1174 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1175 if (p1pll->lcd_pll_out_min == 0) 1176 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1177 p1pll->lcd_pll_out_max = 1178 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1179 if (p1pll->lcd_pll_out_max == 0) 1180 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1181 } else { 1182 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1183 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1184 } 1185 1186 if (p1pll->pll_out_min == 0) { 1187 if (ASIC_IS_AVIVO(rdev)) 1188 p1pll->pll_out_min = 64800; 1189 else 1190 p1pll->pll_out_min = 20000; 1191 } 1192 1193 p1pll->pll_in_min = 1194 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1195 p1pll->pll_in_max = 1196 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1197 1198 *p2pll = *p1pll; 1199 1200 /* system clock */ 1201 if (ASIC_IS_DCE4(rdev)) 1202 spll->reference_freq = 1203 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1204 else 1205 spll->reference_freq = 1206 le16_to_cpu(firmware_info->info.usReferenceClock); 1207 spll->reference_div = 0; 1208 1209 spll->pll_out_min = 1210 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1211 spll->pll_out_max = 1212 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1213 1214 /* ??? */ 1215 if (spll->pll_out_min == 0) { 1216 if (ASIC_IS_AVIVO(rdev)) 1217 spll->pll_out_min = 64800; 1218 else 1219 spll->pll_out_min = 20000; 1220 } 1221 1222 spll->pll_in_min = 1223 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1224 spll->pll_in_max = 1225 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1226 1227 /* memory clock */ 1228 if (ASIC_IS_DCE4(rdev)) 1229 mpll->reference_freq = 1230 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1231 else 1232 mpll->reference_freq = 1233 le16_to_cpu(firmware_info->info.usReferenceClock); 1234 mpll->reference_div = 0; 1235 1236 mpll->pll_out_min = 1237 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1238 mpll->pll_out_max = 1239 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1240 1241 /* ??? */ 1242 if (mpll->pll_out_min == 0) { 1243 if (ASIC_IS_AVIVO(rdev)) 1244 mpll->pll_out_min = 64800; 1245 else 1246 mpll->pll_out_min = 20000; 1247 } 1248 1249 mpll->pll_in_min = 1250 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1251 mpll->pll_in_max = 1252 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1253 1254 rdev->clock.default_sclk = 1255 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1256 rdev->clock.default_mclk = 1257 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1258 1259 if (ASIC_IS_DCE4(rdev)) { 1260 rdev->clock.default_dispclk = 1261 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1262 if (rdev->clock.default_dispclk == 0) { 1263 if (ASIC_IS_DCE6(rdev)) 1264 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1265 else if (ASIC_IS_DCE5(rdev)) 1266 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1267 else 1268 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1269 } 1270 /* set a reasonable default for DP */ 1271 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1272 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1273 rdev->clock.default_dispclk / 100); 1274 rdev->clock.default_dispclk = 60000; 1275 } 1276 rdev->clock.dp_extclk = 1277 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1278 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1279 } 1280 *dcpll = *p1pll; 1281 1282 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1283 if (rdev->clock.max_pixel_clock == 0) 1284 rdev->clock.max_pixel_clock = 40000; 1285 1286 /* not technically a clock, but... */ 1287 rdev->mode_info.firmware_flags = 1288 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1289 1290 if (ASIC_IS_DCE8(rdev)) 1291 rdev->clock.vco_freq = 1292 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); 1293 else if (ASIC_IS_DCE5(rdev)) 1294 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1295 else if (ASIC_IS_DCE41(rdev)) 1296 radeon_atombios_get_dentist_vco_freq(rdev); 1297 else 1298 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1299 1300 if (rdev->clock.vco_freq == 0) 1301 rdev->clock.vco_freq = 360000; /* 3.6 GHz */ 1302 1303 return true; 1304 } 1305 1306 return false; 1307 } 1308 1309 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1310 { 1311 struct radeon_mode_info *mode_info = &rdev->mode_info; 1312 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1313 union igp_info *igp_info; 1314 u8 frev, crev; 1315 u16 data_offset; 1316 1317 /* sideport is AMD only */ 1318 if (rdev->family == CHIP_RS600) 1319 return false; 1320 1321 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1322 &frev, &crev, &data_offset)) { 1323 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1324 data_offset); 1325 switch (crev) { 1326 case 1: 1327 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1328 return true; 1329 break; 1330 case 2: 1331 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1332 return true; 1333 break; 1334 default: 1335 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1336 break; 1337 } 1338 } 1339 return false; 1340 } 1341 1342 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1343 struct radeon_encoder_int_tmds *tmds) 1344 { 1345 struct drm_device *dev = encoder->base.dev; 1346 struct radeon_device *rdev = dev->dev_private; 1347 struct radeon_mode_info *mode_info = &rdev->mode_info; 1348 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1349 uint16_t data_offset; 1350 struct _ATOM_TMDS_INFO *tmds_info; 1351 uint8_t frev, crev; 1352 uint16_t maxfreq; 1353 int i; 1354 1355 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1356 &frev, &crev, &data_offset)) { 1357 tmds_info = 1358 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1359 data_offset); 1360 1361 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1362 for (i = 0; i < 4; i++) { 1363 tmds->tmds_pll[i].freq = 1364 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1365 tmds->tmds_pll[i].value = 1366 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1367 tmds->tmds_pll[i].value |= 1368 (tmds_info->asMiscInfo[i]. 1369 ucPLL_VCO_Gain & 0x3f) << 6; 1370 tmds->tmds_pll[i].value |= 1371 (tmds_info->asMiscInfo[i]. 1372 ucPLL_DutyCycle & 0xf) << 12; 1373 tmds->tmds_pll[i].value |= 1374 (tmds_info->asMiscInfo[i]. 1375 ucPLL_VoltageSwing & 0xf) << 16; 1376 1377 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1378 tmds->tmds_pll[i].freq, 1379 tmds->tmds_pll[i].value); 1380 1381 if (maxfreq == tmds->tmds_pll[i].freq) { 1382 tmds->tmds_pll[i].freq = 0xffffffff; 1383 break; 1384 } 1385 } 1386 return true; 1387 } 1388 return false; 1389 } 1390 1391 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1392 struct radeon_atom_ss *ss, 1393 int id) 1394 { 1395 struct radeon_mode_info *mode_info = &rdev->mode_info; 1396 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1397 uint16_t data_offset, size; 1398 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1399 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1400 uint8_t frev, crev; 1401 int i, num_indices; 1402 1403 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1404 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1405 &frev, &crev, &data_offset)) { 1406 ss_info = 1407 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1408 1409 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1410 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1411 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1412 ((u8 *)&ss_info->asSS_Info[0]); 1413 for (i = 0; i < num_indices; i++) { 1414 if (ss_assign->ucSS_Id == id) { 1415 ss->percentage = 1416 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1417 ss->type = ss_assign->ucSpreadSpectrumType; 1418 ss->step = ss_assign->ucSS_Step; 1419 ss->delay = ss_assign->ucSS_Delay; 1420 ss->range = ss_assign->ucSS_Range; 1421 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1422 return true; 1423 } 1424 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1425 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1426 } 1427 } 1428 return false; 1429 } 1430 1431 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1432 struct radeon_atom_ss *ss, 1433 int id) 1434 { 1435 struct radeon_mode_info *mode_info = &rdev->mode_info; 1436 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1437 u16 data_offset, size; 1438 union igp_info *igp_info; 1439 u8 frev, crev; 1440 u16 percentage = 0, rate = 0; 1441 1442 /* get any igp specific overrides */ 1443 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1444 &frev, &crev, &data_offset)) { 1445 igp_info = (union igp_info *) 1446 (mode_info->atom_context->bios + data_offset); 1447 switch (crev) { 1448 case 6: 1449 switch (id) { 1450 case ASIC_INTERNAL_SS_ON_TMDS: 1451 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1452 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1453 break; 1454 case ASIC_INTERNAL_SS_ON_HDMI: 1455 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1456 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1457 break; 1458 case ASIC_INTERNAL_SS_ON_LVDS: 1459 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1460 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1461 break; 1462 } 1463 break; 1464 case 7: 1465 switch (id) { 1466 case ASIC_INTERNAL_SS_ON_TMDS: 1467 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1468 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1469 break; 1470 case ASIC_INTERNAL_SS_ON_HDMI: 1471 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1472 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1473 break; 1474 case ASIC_INTERNAL_SS_ON_LVDS: 1475 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1476 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1477 break; 1478 } 1479 break; 1480 case 8: 1481 switch (id) { 1482 case ASIC_INTERNAL_SS_ON_TMDS: 1483 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1484 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1485 break; 1486 case ASIC_INTERNAL_SS_ON_HDMI: 1487 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1488 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1489 break; 1490 case ASIC_INTERNAL_SS_ON_LVDS: 1491 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1492 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1493 break; 1494 } 1495 break; 1496 default: 1497 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1498 break; 1499 } 1500 if (percentage) 1501 ss->percentage = percentage; 1502 if (rate) 1503 ss->rate = rate; 1504 } 1505 } 1506 1507 union asic_ss_info { 1508 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1509 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1510 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1511 }; 1512 1513 union asic_ss_assignment { 1514 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1515 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1516 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1517 }; 1518 1519 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1520 struct radeon_atom_ss *ss, 1521 int id, u32 clock) 1522 { 1523 struct radeon_mode_info *mode_info = &rdev->mode_info; 1524 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1525 uint16_t data_offset, size; 1526 union asic_ss_info *ss_info; 1527 union asic_ss_assignment *ss_assign; 1528 uint8_t frev, crev; 1529 int i, num_indices; 1530 1531 if (id == ASIC_INTERNAL_MEMORY_SS) { 1532 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1533 return false; 1534 } 1535 if (id == ASIC_INTERNAL_ENGINE_SS) { 1536 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1537 return false; 1538 } 1539 1540 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1541 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1542 &frev, &crev, &data_offset)) { 1543 1544 ss_info = 1545 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1546 1547 switch (frev) { 1548 case 1: 1549 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1550 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1551 1552 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1553 for (i = 0; i < num_indices; i++) { 1554 if ((ss_assign->v1.ucClockIndication == id) && 1555 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1556 ss->percentage = 1557 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1558 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1559 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1560 ss->percentage_divider = 100; 1561 return true; 1562 } 1563 ss_assign = (union asic_ss_assignment *) 1564 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1565 } 1566 break; 1567 case 2: 1568 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1569 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1570 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1571 for (i = 0; i < num_indices; i++) { 1572 if ((ss_assign->v2.ucClockIndication == id) && 1573 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1574 ss->percentage = 1575 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1576 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1577 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1578 ss->percentage_divider = 100; 1579 if ((crev == 2) && 1580 ((id == ASIC_INTERNAL_ENGINE_SS) || 1581 (id == ASIC_INTERNAL_MEMORY_SS))) 1582 ss->rate /= 100; 1583 return true; 1584 } 1585 ss_assign = (union asic_ss_assignment *) 1586 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1587 } 1588 break; 1589 case 3: 1590 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1591 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1592 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1593 for (i = 0; i < num_indices; i++) { 1594 if ((ss_assign->v3.ucClockIndication == id) && 1595 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1596 ss->percentage = 1597 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1598 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1599 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1600 if (ss_assign->v3.ucSpreadSpectrumMode & 1601 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1602 ss->percentage_divider = 1000; 1603 else 1604 ss->percentage_divider = 100; 1605 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1606 (id == ASIC_INTERNAL_MEMORY_SS)) 1607 ss->rate /= 100; 1608 if (rdev->flags & RADEON_IS_IGP) 1609 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1610 return true; 1611 } 1612 ss_assign = (union asic_ss_assignment *) 1613 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1614 } 1615 break; 1616 default: 1617 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1618 break; 1619 } 1620 1621 } 1622 return false; 1623 } 1624 1625 union lvds_info { 1626 struct _ATOM_LVDS_INFO info; 1627 struct _ATOM_LVDS_INFO_V12 info_12; 1628 }; 1629 1630 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1631 radeon_encoder 1632 *encoder) 1633 { 1634 struct drm_device *dev = encoder->base.dev; 1635 struct radeon_device *rdev = dev->dev_private; 1636 struct radeon_mode_info *mode_info = &rdev->mode_info; 1637 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1638 uint16_t data_offset, misc; 1639 union lvds_info *lvds_info; 1640 uint8_t frev, crev; 1641 struct radeon_encoder_atom_dig *lvds = NULL; 1642 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1643 1644 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1645 &frev, &crev, &data_offset)) { 1646 lvds_info = 1647 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1648 lvds = 1649 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1650 1651 if (!lvds) 1652 return NULL; 1653 1654 lvds->native_mode.clock = 1655 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1656 lvds->native_mode.hdisplay = 1657 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1658 lvds->native_mode.vdisplay = 1659 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1660 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1661 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1662 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1663 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1664 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1665 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1666 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1667 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1668 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1669 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1670 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1671 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1672 lvds->panel_pwr_delay = 1673 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1674 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1675 1676 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1677 if (misc & ATOM_VSYNC_POLARITY) 1678 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1679 if (misc & ATOM_HSYNC_POLARITY) 1680 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1681 if (misc & ATOM_COMPOSITESYNC) 1682 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1683 if (misc & ATOM_INTERLACE) 1684 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1685 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1686 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1687 1688 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1689 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1690 1691 /* set crtc values */ 1692 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1693 1694 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1695 1696 encoder->native_mode = lvds->native_mode; 1697 1698 if (encoder_enum == 2) 1699 lvds->linkb = true; 1700 else 1701 lvds->linkb = false; 1702 1703 /* parse the lcd record table */ 1704 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1705 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1706 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1707 bool bad_record = false; 1708 u8 *record; 1709 1710 if ((frev == 1) && (crev < 2)) 1711 /* absolute */ 1712 record = (u8 *)(mode_info->atom_context->bios + 1713 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1714 else 1715 /* relative */ 1716 record = (u8 *)(mode_info->atom_context->bios + 1717 data_offset + 1718 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1719 while (*record != ATOM_RECORD_END_TYPE) { 1720 switch (*record) { 1721 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1722 record += sizeof(ATOM_PATCH_RECORD_MODE); 1723 break; 1724 case LCD_RTS_RECORD_TYPE: 1725 record += sizeof(ATOM_LCD_RTS_RECORD); 1726 break; 1727 case LCD_CAP_RECORD_TYPE: 1728 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1729 break; 1730 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1731 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1732 if (fake_edid_record->ucFakeEDIDLength) { 1733 struct edid *edid; 1734 int edid_size = 1735 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1736 edid = kmalloc(edid_size, GFP_KERNEL); 1737 if (edid) { 1738 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1739 fake_edid_record->ucFakeEDIDLength); 1740 1741 if (drm_edid_is_valid(edid)) { 1742 rdev->mode_info.bios_hardcoded_edid = edid; 1743 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1744 } else 1745 kfree(edid); 1746 } 1747 } 1748 record += fake_edid_record->ucFakeEDIDLength ? 1749 fake_edid_record->ucFakeEDIDLength + 2 : 1750 sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1751 break; 1752 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1753 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1754 lvds->native_mode.width_mm = panel_res_record->usHSize; 1755 lvds->native_mode.height_mm = panel_res_record->usVSize; 1756 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1757 break; 1758 default: 1759 DRM_ERROR("Bad LCD record %d\n", *record); 1760 bad_record = true; 1761 break; 1762 } 1763 if (bad_record) 1764 break; 1765 } 1766 } 1767 } 1768 return lvds; 1769 } 1770 1771 struct radeon_encoder_primary_dac * 1772 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1773 { 1774 struct drm_device *dev = encoder->base.dev; 1775 struct radeon_device *rdev = dev->dev_private; 1776 struct radeon_mode_info *mode_info = &rdev->mode_info; 1777 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1778 uint16_t data_offset; 1779 struct _COMPASSIONATE_DATA *dac_info; 1780 uint8_t frev, crev; 1781 uint8_t bg, dac; 1782 struct radeon_encoder_primary_dac *p_dac = NULL; 1783 1784 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1785 &frev, &crev, &data_offset)) { 1786 dac_info = (struct _COMPASSIONATE_DATA *) 1787 (mode_info->atom_context->bios + data_offset); 1788 1789 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1790 1791 if (!p_dac) 1792 return NULL; 1793 1794 bg = dac_info->ucDAC1_BG_Adjustment; 1795 dac = dac_info->ucDAC1_DAC_Adjustment; 1796 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1797 1798 } 1799 return p_dac; 1800 } 1801 1802 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1803 struct drm_display_mode *mode) 1804 { 1805 struct radeon_mode_info *mode_info = &rdev->mode_info; 1806 ATOM_ANALOG_TV_INFO *tv_info; 1807 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1808 ATOM_DTD_FORMAT *dtd_timings; 1809 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1810 u8 frev, crev; 1811 u16 data_offset, misc; 1812 1813 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1814 &frev, &crev, &data_offset)) 1815 return false; 1816 1817 switch (crev) { 1818 case 1: 1819 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1820 if (index >= MAX_SUPPORTED_TV_TIMING) 1821 return false; 1822 1823 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1824 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1825 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1826 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1827 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1828 1829 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1830 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1831 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1832 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1833 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1834 1835 mode->flags = 0; 1836 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1837 if (misc & ATOM_VSYNC_POLARITY) 1838 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1839 if (misc & ATOM_HSYNC_POLARITY) 1840 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1841 if (misc & ATOM_COMPOSITESYNC) 1842 mode->flags |= DRM_MODE_FLAG_CSYNC; 1843 if (misc & ATOM_INTERLACE) 1844 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1845 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1846 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1847 1848 mode->crtc_clock = mode->clock = 1849 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1850 1851 if (index == 1) { 1852 /* PAL timings appear to have wrong values for totals */ 1853 mode->crtc_htotal -= 1; 1854 mode->crtc_vtotal -= 1; 1855 } 1856 break; 1857 case 2: 1858 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1859 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1860 return false; 1861 1862 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1863 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1864 le16_to_cpu(dtd_timings->usHBlanking_Time); 1865 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1866 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1867 le16_to_cpu(dtd_timings->usHSyncOffset); 1868 mode->crtc_hsync_end = mode->crtc_hsync_start + 1869 le16_to_cpu(dtd_timings->usHSyncWidth); 1870 1871 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1872 le16_to_cpu(dtd_timings->usVBlanking_Time); 1873 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1874 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1875 le16_to_cpu(dtd_timings->usVSyncOffset); 1876 mode->crtc_vsync_end = mode->crtc_vsync_start + 1877 le16_to_cpu(dtd_timings->usVSyncWidth); 1878 1879 mode->flags = 0; 1880 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1881 if (misc & ATOM_VSYNC_POLARITY) 1882 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1883 if (misc & ATOM_HSYNC_POLARITY) 1884 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1885 if (misc & ATOM_COMPOSITESYNC) 1886 mode->flags |= DRM_MODE_FLAG_CSYNC; 1887 if (misc & ATOM_INTERLACE) 1888 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1889 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1890 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1891 1892 mode->crtc_clock = mode->clock = 1893 le16_to_cpu(dtd_timings->usPixClk) * 10; 1894 break; 1895 } 1896 return true; 1897 } 1898 1899 enum radeon_tv_std 1900 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1901 { 1902 struct radeon_mode_info *mode_info = &rdev->mode_info; 1903 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1904 uint16_t data_offset; 1905 uint8_t frev, crev; 1906 struct _ATOM_ANALOG_TV_INFO *tv_info; 1907 enum radeon_tv_std tv_std = TV_STD_NTSC; 1908 1909 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1910 &frev, &crev, &data_offset)) { 1911 1912 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1913 (mode_info->atom_context->bios + data_offset); 1914 1915 switch (tv_info->ucTV_BootUpDefaultStandard) { 1916 case ATOM_TV_NTSC: 1917 tv_std = TV_STD_NTSC; 1918 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1919 break; 1920 case ATOM_TV_NTSCJ: 1921 tv_std = TV_STD_NTSC_J; 1922 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1923 break; 1924 case ATOM_TV_PAL: 1925 tv_std = TV_STD_PAL; 1926 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1927 break; 1928 case ATOM_TV_PALM: 1929 tv_std = TV_STD_PAL_M; 1930 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1931 break; 1932 case ATOM_TV_PALN: 1933 tv_std = TV_STD_PAL_N; 1934 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1935 break; 1936 case ATOM_TV_PALCN: 1937 tv_std = TV_STD_PAL_CN; 1938 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1939 break; 1940 case ATOM_TV_PAL60: 1941 tv_std = TV_STD_PAL_60; 1942 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1943 break; 1944 case ATOM_TV_SECAM: 1945 tv_std = TV_STD_SECAM; 1946 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1947 break; 1948 default: 1949 tv_std = TV_STD_NTSC; 1950 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1951 break; 1952 } 1953 } 1954 return tv_std; 1955 } 1956 1957 struct radeon_encoder_tv_dac * 1958 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1959 { 1960 struct drm_device *dev = encoder->base.dev; 1961 struct radeon_device *rdev = dev->dev_private; 1962 struct radeon_mode_info *mode_info = &rdev->mode_info; 1963 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1964 uint16_t data_offset; 1965 struct _COMPASSIONATE_DATA *dac_info; 1966 uint8_t frev, crev; 1967 uint8_t bg, dac; 1968 struct radeon_encoder_tv_dac *tv_dac = NULL; 1969 1970 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1971 &frev, &crev, &data_offset)) { 1972 1973 dac_info = (struct _COMPASSIONATE_DATA *) 1974 (mode_info->atom_context->bios + data_offset); 1975 1976 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1977 1978 if (!tv_dac) 1979 return NULL; 1980 1981 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1982 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1983 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1984 1985 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1986 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1987 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1988 1989 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1990 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1991 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1992 1993 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1994 } 1995 return tv_dac; 1996 } 1997 1998 static const char *thermal_controller_names[] = { 1999 "NONE", 2000 "lm63", 2001 "adm1032", 2002 "adm1030", 2003 "max6649", 2004 "lm63", /* lm64 */ 2005 "f75375", 2006 "asc7xxx", 2007 }; 2008 2009 static const char *pp_lib_thermal_controller_names[] = { 2010 "NONE", 2011 "lm63", 2012 "adm1032", 2013 "adm1030", 2014 "max6649", 2015 "lm63", /* lm64 */ 2016 "f75375", 2017 "RV6xx", 2018 "RV770", 2019 "adt7473", 2020 "NONE", 2021 "External GPIO", 2022 "Evergreen", 2023 "emc2103", 2024 "Sumo", 2025 "Northern Islands", 2026 "Southern Islands", 2027 "lm96163", 2028 "Sea Islands", 2029 }; 2030 2031 union power_info { 2032 struct _ATOM_POWERPLAY_INFO info; 2033 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2034 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2035 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2036 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2037 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2038 }; 2039 2040 union pplib_clock_info { 2041 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2042 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2043 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2044 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2045 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2046 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2047 }; 2048 2049 union pplib_power_state { 2050 struct _ATOM_PPLIB_STATE v1; 2051 struct _ATOM_PPLIB_STATE_V2 v2; 2052 }; 2053 2054 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2055 int state_index, 2056 u32 misc, u32 misc2) 2057 { 2058 rdev->pm.power_state[state_index].misc = misc; 2059 rdev->pm.power_state[state_index].misc2 = misc2; 2060 /* order matters! */ 2061 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2062 rdev->pm.power_state[state_index].type = 2063 POWER_STATE_TYPE_POWERSAVE; 2064 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2065 rdev->pm.power_state[state_index].type = 2066 POWER_STATE_TYPE_BATTERY; 2067 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2068 rdev->pm.power_state[state_index].type = 2069 POWER_STATE_TYPE_BATTERY; 2070 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2071 rdev->pm.power_state[state_index].type = 2072 POWER_STATE_TYPE_BALANCED; 2073 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2074 rdev->pm.power_state[state_index].type = 2075 POWER_STATE_TYPE_PERFORMANCE; 2076 rdev->pm.power_state[state_index].flags &= 2077 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2078 } 2079 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2080 rdev->pm.power_state[state_index].type = 2081 POWER_STATE_TYPE_BALANCED; 2082 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2083 rdev->pm.power_state[state_index].type = 2084 POWER_STATE_TYPE_DEFAULT; 2085 rdev->pm.default_power_state_index = state_index; 2086 rdev->pm.power_state[state_index].default_clock_mode = 2087 &rdev->pm.power_state[state_index].clock_info[0]; 2088 } else if (state_index == 0) { 2089 rdev->pm.power_state[state_index].clock_info[0].flags |= 2090 RADEON_PM_MODE_NO_DISPLAY; 2091 } 2092 } 2093 2094 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2095 { 2096 struct radeon_mode_info *mode_info = &rdev->mode_info; 2097 u32 misc, misc2 = 0; 2098 int num_modes = 0, i; 2099 int state_index = 0; 2100 struct radeon_i2c_bus_rec i2c_bus; 2101 union power_info *power_info; 2102 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2103 u16 data_offset; 2104 u8 frev, crev; 2105 2106 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2107 &frev, &crev, &data_offset)) 2108 return state_index; 2109 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2110 2111 /* add the i2c bus for thermal/fan chip */ 2112 if ((power_info->info.ucOverdriveThermalController > 0) && 2113 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2114 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2115 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2116 power_info->info.ucOverdriveControllerAddress >> 1); 2117 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2118 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2119 if (rdev->pm.i2c_bus) { 2120 struct i2c_board_info info = { }; 2121 const char *name = thermal_controller_names[power_info->info. 2122 ucOverdriveThermalController]; 2123 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2124 strlcpy(info.type, name, sizeof(info.type)); 2125 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2126 } 2127 } 2128 num_modes = power_info->info.ucNumOfPowerModeEntries; 2129 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2130 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2131 if (num_modes == 0) 2132 return state_index; 2133 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2134 if (!rdev->pm.power_state) 2135 return state_index; 2136 /* last mode is usually default, array is low to high */ 2137 for (i = 0; i < num_modes; i++) { 2138 rdev->pm.power_state[state_index].clock_info = 2139 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2140 if (!rdev->pm.power_state[state_index].clock_info) 2141 return state_index; 2142 rdev->pm.power_state[state_index].num_clock_modes = 1; 2143 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2144 switch (frev) { 2145 case 1: 2146 rdev->pm.power_state[state_index].clock_info[0].mclk = 2147 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2148 rdev->pm.power_state[state_index].clock_info[0].sclk = 2149 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2150 /* skip invalid modes */ 2151 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2152 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2153 continue; 2154 rdev->pm.power_state[state_index].pcie_lanes = 2155 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2156 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2157 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2158 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2159 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2160 VOLTAGE_GPIO; 2161 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2162 radeon_atombios_lookup_gpio(rdev, 2163 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2164 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2165 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2166 true; 2167 else 2168 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2169 false; 2170 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2171 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2172 VOLTAGE_VDDC; 2173 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2174 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2175 } 2176 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2177 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2178 state_index++; 2179 break; 2180 case 2: 2181 rdev->pm.power_state[state_index].clock_info[0].mclk = 2182 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2183 rdev->pm.power_state[state_index].clock_info[0].sclk = 2184 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2185 /* skip invalid modes */ 2186 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2187 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2188 continue; 2189 rdev->pm.power_state[state_index].pcie_lanes = 2190 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2191 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2192 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2193 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2194 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2195 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2196 VOLTAGE_GPIO; 2197 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2198 radeon_atombios_lookup_gpio(rdev, 2199 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2200 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2201 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2202 true; 2203 else 2204 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2205 false; 2206 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2207 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2208 VOLTAGE_VDDC; 2209 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2210 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2211 } 2212 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2213 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2214 state_index++; 2215 break; 2216 case 3: 2217 rdev->pm.power_state[state_index].clock_info[0].mclk = 2218 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2219 rdev->pm.power_state[state_index].clock_info[0].sclk = 2220 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2221 /* skip invalid modes */ 2222 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2223 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2224 continue; 2225 rdev->pm.power_state[state_index].pcie_lanes = 2226 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2227 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2228 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2229 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2230 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2231 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2232 VOLTAGE_GPIO; 2233 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2234 radeon_atombios_lookup_gpio(rdev, 2235 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2236 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2237 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2238 true; 2239 else 2240 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2241 false; 2242 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2243 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2244 VOLTAGE_VDDC; 2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2246 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2247 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2248 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2249 true; 2250 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2251 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2252 } 2253 } 2254 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2255 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2256 state_index++; 2257 break; 2258 } 2259 } 2260 /* last mode is usually default */ 2261 if (rdev->pm.default_power_state_index == -1) { 2262 rdev->pm.power_state[state_index - 1].type = 2263 POWER_STATE_TYPE_DEFAULT; 2264 rdev->pm.default_power_state_index = state_index - 1; 2265 rdev->pm.power_state[state_index - 1].default_clock_mode = 2266 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2267 rdev->pm.power_state[state_index].flags &= 2268 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2269 rdev->pm.power_state[state_index].misc = 0; 2270 rdev->pm.power_state[state_index].misc2 = 0; 2271 } 2272 return state_index; 2273 } 2274 2275 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2276 ATOM_PPLIB_THERMALCONTROLLER *controller) 2277 { 2278 struct radeon_i2c_bus_rec i2c_bus; 2279 2280 /* add the i2c bus for thermal/fan chip */ 2281 if (controller->ucType > 0) { 2282 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2283 rdev->pm.no_fan = true; 2284 rdev->pm.fan_pulses_per_revolution = 2285 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2286 if (rdev->pm.fan_pulses_per_revolution) { 2287 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2288 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2289 } 2290 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2291 DRM_INFO("Internal thermal controller %s fan control\n", 2292 (controller->ucFanParameters & 2293 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2294 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2295 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2296 DRM_INFO("Internal thermal controller %s fan control\n", 2297 (controller->ucFanParameters & 2298 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2299 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2300 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2301 DRM_INFO("Internal thermal controller %s fan control\n", 2302 (controller->ucFanParameters & 2303 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2304 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2305 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2306 DRM_INFO("Internal thermal controller %s fan control\n", 2307 (controller->ucFanParameters & 2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2309 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2310 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2311 DRM_INFO("Internal thermal controller %s fan control\n", 2312 (controller->ucFanParameters & 2313 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2314 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2315 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2316 DRM_INFO("Internal thermal controller %s fan control\n", 2317 (controller->ucFanParameters & 2318 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2319 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2320 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2321 DRM_INFO("Internal thermal controller %s fan control\n", 2322 (controller->ucFanParameters & 2323 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2324 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2325 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2326 DRM_INFO("Internal thermal controller %s fan control\n", 2327 (controller->ucFanParameters & 2328 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2329 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2330 } else if (controller->ucType == 2331 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2332 DRM_INFO("External GPIO thermal controller %s fan control\n", 2333 (controller->ucFanParameters & 2334 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2335 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2336 } else if (controller->ucType == 2337 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2338 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2339 (controller->ucFanParameters & 2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2341 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2342 } else if (controller->ucType == 2343 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2344 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2345 (controller->ucFanParameters & 2346 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2347 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2348 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2349 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2350 pp_lib_thermal_controller_names[controller->ucType], 2351 controller->ucI2cAddress >> 1, 2352 (controller->ucFanParameters & 2353 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2354 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2355 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2356 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2357 if (rdev->pm.i2c_bus) { 2358 struct i2c_board_info info = { }; 2359 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2360 info.addr = controller->ucI2cAddress >> 1; 2361 strlcpy(info.type, name, sizeof(info.type)); 2362 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2363 } 2364 } else { 2365 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2366 controller->ucType, 2367 controller->ucI2cAddress >> 1, 2368 (controller->ucFanParameters & 2369 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2370 } 2371 } 2372 } 2373 2374 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2375 u16 *vddc, u16 *vddci, u16 *mvdd) 2376 { 2377 struct radeon_mode_info *mode_info = &rdev->mode_info; 2378 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2379 u8 frev, crev; 2380 u16 data_offset; 2381 union firmware_info *firmware_info; 2382 2383 *vddc = 0; 2384 *vddci = 0; 2385 *mvdd = 0; 2386 2387 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2388 &frev, &crev, &data_offset)) { 2389 firmware_info = 2390 (union firmware_info *)(mode_info->atom_context->bios + 2391 data_offset); 2392 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2393 if ((frev == 2) && (crev >= 2)) { 2394 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2395 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2396 } 2397 } 2398 } 2399 2400 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2401 int state_index, int mode_index, 2402 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2403 { 2404 int j; 2405 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2406 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2407 u16 vddc, vddci, mvdd; 2408 2409 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2410 2411 rdev->pm.power_state[state_index].misc = misc; 2412 rdev->pm.power_state[state_index].misc2 = misc2; 2413 rdev->pm.power_state[state_index].pcie_lanes = 2414 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2415 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2416 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2417 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2418 rdev->pm.power_state[state_index].type = 2419 POWER_STATE_TYPE_BATTERY; 2420 break; 2421 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2422 rdev->pm.power_state[state_index].type = 2423 POWER_STATE_TYPE_BALANCED; 2424 break; 2425 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2426 rdev->pm.power_state[state_index].type = 2427 POWER_STATE_TYPE_PERFORMANCE; 2428 break; 2429 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2430 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2431 rdev->pm.power_state[state_index].type = 2432 POWER_STATE_TYPE_PERFORMANCE; 2433 break; 2434 } 2435 rdev->pm.power_state[state_index].flags = 0; 2436 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2437 rdev->pm.power_state[state_index].flags |= 2438 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2439 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2440 rdev->pm.power_state[state_index].type = 2441 POWER_STATE_TYPE_DEFAULT; 2442 rdev->pm.default_power_state_index = state_index; 2443 rdev->pm.power_state[state_index].default_clock_mode = 2444 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2445 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2446 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2447 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2448 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2449 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2450 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2451 } else { 2452 u16 max_vddci = 0; 2453 2454 if (ASIC_IS_DCE4(rdev)) 2455 radeon_atom_get_max_voltage(rdev, 2456 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2457 &max_vddci); 2458 /* patch the table values with the default sclk/mclk from firmware info */ 2459 for (j = 0; j < mode_index; j++) { 2460 rdev->pm.power_state[state_index].clock_info[j].mclk = 2461 rdev->clock.default_mclk; 2462 rdev->pm.power_state[state_index].clock_info[j].sclk = 2463 rdev->clock.default_sclk; 2464 if (vddc) 2465 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2466 vddc; 2467 if (max_vddci) 2468 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2469 max_vddci; 2470 } 2471 } 2472 } 2473 } 2474 2475 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2476 int state_index, int mode_index, 2477 union pplib_clock_info *clock_info) 2478 { 2479 u32 sclk, mclk; 2480 u16 vddc; 2481 2482 if (rdev->flags & RADEON_IS_IGP) { 2483 if (rdev->family >= CHIP_PALM) { 2484 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2485 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2486 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2487 } else { 2488 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2489 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2490 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2491 } 2492 } else if (rdev->family >= CHIP_BONAIRE) { 2493 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2494 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2495 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2496 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2497 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2498 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2499 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2500 VOLTAGE_NONE; 2501 } else if (rdev->family >= CHIP_TAHITI) { 2502 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2503 sclk |= clock_info->si.ucEngineClockHigh << 16; 2504 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2505 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2506 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2509 VOLTAGE_SW; 2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2511 le16_to_cpu(clock_info->si.usVDDC); 2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2513 le16_to_cpu(clock_info->si.usVDDCI); 2514 } else if (rdev->family >= CHIP_CEDAR) { 2515 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2516 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2517 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2518 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2519 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2520 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2522 VOLTAGE_SW; 2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2524 le16_to_cpu(clock_info->evergreen.usVDDC); 2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2526 le16_to_cpu(clock_info->evergreen.usVDDCI); 2527 } else { 2528 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2529 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2530 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2531 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2532 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2533 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2534 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2535 VOLTAGE_SW; 2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2537 le16_to_cpu(clock_info->r600.usVDDC); 2538 } 2539 2540 /* patch up vddc if necessary */ 2541 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2542 case ATOM_VIRTUAL_VOLTAGE_ID0: 2543 case ATOM_VIRTUAL_VOLTAGE_ID1: 2544 case ATOM_VIRTUAL_VOLTAGE_ID2: 2545 case ATOM_VIRTUAL_VOLTAGE_ID3: 2546 case ATOM_VIRTUAL_VOLTAGE_ID4: 2547 case ATOM_VIRTUAL_VOLTAGE_ID5: 2548 case ATOM_VIRTUAL_VOLTAGE_ID6: 2549 case ATOM_VIRTUAL_VOLTAGE_ID7: 2550 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2551 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2552 &vddc) == 0) 2553 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2554 break; 2555 default: 2556 break; 2557 } 2558 2559 if (rdev->flags & RADEON_IS_IGP) { 2560 /* skip invalid modes */ 2561 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2562 return false; 2563 } else { 2564 /* skip invalid modes */ 2565 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2566 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2567 return false; 2568 } 2569 return true; 2570 } 2571 2572 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2573 { 2574 struct radeon_mode_info *mode_info = &rdev->mode_info; 2575 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2576 union pplib_power_state *power_state; 2577 int i, j; 2578 int state_index = 0, mode_index = 0; 2579 union pplib_clock_info *clock_info; 2580 bool valid; 2581 union power_info *power_info; 2582 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2583 u16 data_offset; 2584 u8 frev, crev; 2585 2586 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2587 &frev, &crev, &data_offset)) 2588 return state_index; 2589 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2590 2591 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2592 if (power_info->pplib.ucNumStates == 0) 2593 return state_index; 2594 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2595 power_info->pplib.ucNumStates, GFP_KERNEL); 2596 if (!rdev->pm.power_state) 2597 return state_index; 2598 /* first mode is usually default, followed by low to high */ 2599 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2600 mode_index = 0; 2601 power_state = (union pplib_power_state *) 2602 (mode_info->atom_context->bios + data_offset + 2603 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2604 i * power_info->pplib.ucStateEntrySize); 2605 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2606 (mode_info->atom_context->bios + data_offset + 2607 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2608 (power_state->v1.ucNonClockStateIndex * 2609 power_info->pplib.ucNonClockSize)); 2610 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2611 ((power_info->pplib.ucStateEntrySize - 1) ? 2612 (power_info->pplib.ucStateEntrySize - 1) : 1), 2613 GFP_KERNEL); 2614 if (!rdev->pm.power_state[i].clock_info) 2615 return state_index; 2616 if (power_info->pplib.ucStateEntrySize - 1) { 2617 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2618 clock_info = (union pplib_clock_info *) 2619 (mode_info->atom_context->bios + data_offset + 2620 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2621 (power_state->v1.ucClockStateIndices[j] * 2622 power_info->pplib.ucClockInfoSize)); 2623 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2624 state_index, mode_index, 2625 clock_info); 2626 if (valid) 2627 mode_index++; 2628 } 2629 } else { 2630 rdev->pm.power_state[state_index].clock_info[0].mclk = 2631 rdev->clock.default_mclk; 2632 rdev->pm.power_state[state_index].clock_info[0].sclk = 2633 rdev->clock.default_sclk; 2634 mode_index++; 2635 } 2636 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2637 if (mode_index) { 2638 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2639 non_clock_info); 2640 state_index++; 2641 } 2642 } 2643 /* if multiple clock modes, mark the lowest as no display */ 2644 for (i = 0; i < state_index; i++) { 2645 if (rdev->pm.power_state[i].num_clock_modes > 1) 2646 rdev->pm.power_state[i].clock_info[0].flags |= 2647 RADEON_PM_MODE_NO_DISPLAY; 2648 } 2649 /* first mode is usually default */ 2650 if (rdev->pm.default_power_state_index == -1) { 2651 rdev->pm.power_state[0].type = 2652 POWER_STATE_TYPE_DEFAULT; 2653 rdev->pm.default_power_state_index = 0; 2654 rdev->pm.power_state[0].default_clock_mode = 2655 &rdev->pm.power_state[0].clock_info[0]; 2656 } 2657 return state_index; 2658 } 2659 2660 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2661 { 2662 struct radeon_mode_info *mode_info = &rdev->mode_info; 2663 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2664 union pplib_power_state *power_state; 2665 int i, j, non_clock_array_index, clock_array_index; 2666 int state_index = 0, mode_index = 0; 2667 union pplib_clock_info *clock_info; 2668 struct _StateArray *state_array; 2669 struct _ClockInfoArray *clock_info_array; 2670 struct _NonClockInfoArray *non_clock_info_array; 2671 bool valid; 2672 union power_info *power_info; 2673 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2674 u16 data_offset; 2675 u8 frev, crev; 2676 u8 *power_state_offset; 2677 2678 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2679 &frev, &crev, &data_offset)) 2680 return state_index; 2681 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2682 2683 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2684 state_array = (struct _StateArray *) 2685 (mode_info->atom_context->bios + data_offset + 2686 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2687 clock_info_array = (struct _ClockInfoArray *) 2688 (mode_info->atom_context->bios + data_offset + 2689 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2690 non_clock_info_array = (struct _NonClockInfoArray *) 2691 (mode_info->atom_context->bios + data_offset + 2692 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2693 if (state_array->ucNumEntries == 0) 2694 return state_index; 2695 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2696 state_array->ucNumEntries, GFP_KERNEL); 2697 if (!rdev->pm.power_state) 2698 return state_index; 2699 power_state_offset = (u8 *)state_array->states; 2700 for (i = 0; i < state_array->ucNumEntries; i++) { 2701 mode_index = 0; 2702 power_state = (union pplib_power_state *)power_state_offset; 2703 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2704 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2705 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2706 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2707 (power_state->v2.ucNumDPMLevels ? 2708 power_state->v2.ucNumDPMLevels : 1), 2709 GFP_KERNEL); 2710 if (!rdev->pm.power_state[i].clock_info) 2711 return state_index; 2712 if (power_state->v2.ucNumDPMLevels) { 2713 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2714 clock_array_index = power_state->v2.clockInfoIndex[j]; 2715 clock_info = (union pplib_clock_info *) 2716 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2717 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2718 state_index, mode_index, 2719 clock_info); 2720 if (valid) 2721 mode_index++; 2722 } 2723 } else { 2724 rdev->pm.power_state[state_index].clock_info[0].mclk = 2725 rdev->clock.default_mclk; 2726 rdev->pm.power_state[state_index].clock_info[0].sclk = 2727 rdev->clock.default_sclk; 2728 mode_index++; 2729 } 2730 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2731 if (mode_index) { 2732 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2733 non_clock_info); 2734 state_index++; 2735 } 2736 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2737 } 2738 /* if multiple clock modes, mark the lowest as no display */ 2739 for (i = 0; i < state_index; i++) { 2740 if (rdev->pm.power_state[i].num_clock_modes > 1) 2741 rdev->pm.power_state[i].clock_info[0].flags |= 2742 RADEON_PM_MODE_NO_DISPLAY; 2743 } 2744 /* first mode is usually default */ 2745 if (rdev->pm.default_power_state_index == -1) { 2746 rdev->pm.power_state[0].type = 2747 POWER_STATE_TYPE_DEFAULT; 2748 rdev->pm.default_power_state_index = 0; 2749 rdev->pm.power_state[0].default_clock_mode = 2750 &rdev->pm.power_state[0].clock_info[0]; 2751 } 2752 return state_index; 2753 } 2754 2755 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2756 { 2757 struct radeon_mode_info *mode_info = &rdev->mode_info; 2758 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2759 u16 data_offset; 2760 u8 frev, crev; 2761 int state_index = 0; 2762 2763 rdev->pm.default_power_state_index = -1; 2764 2765 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2766 &frev, &crev, &data_offset)) { 2767 switch (frev) { 2768 case 1: 2769 case 2: 2770 case 3: 2771 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2772 break; 2773 case 4: 2774 case 5: 2775 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2776 break; 2777 case 6: 2778 state_index = radeon_atombios_parse_power_table_6(rdev); 2779 break; 2780 default: 2781 break; 2782 } 2783 } 2784 2785 if (state_index == 0) { 2786 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2787 if (rdev->pm.power_state) { 2788 rdev->pm.power_state[0].clock_info = 2789 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2790 if (rdev->pm.power_state[0].clock_info) { 2791 /* add the default mode */ 2792 rdev->pm.power_state[state_index].type = 2793 POWER_STATE_TYPE_DEFAULT; 2794 rdev->pm.power_state[state_index].num_clock_modes = 1; 2795 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2796 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2797 rdev->pm.power_state[state_index].default_clock_mode = 2798 &rdev->pm.power_state[state_index].clock_info[0]; 2799 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2800 rdev->pm.power_state[state_index].pcie_lanes = 16; 2801 rdev->pm.default_power_state_index = state_index; 2802 rdev->pm.power_state[state_index].flags = 0; 2803 state_index++; 2804 } 2805 } 2806 } 2807 2808 rdev->pm.num_power_states = state_index; 2809 2810 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2811 rdev->pm.current_clock_mode_index = 0; 2812 if (rdev->pm.default_power_state_index >= 0) 2813 rdev->pm.current_vddc = 2814 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2815 else 2816 rdev->pm.current_vddc = 0; 2817 } 2818 2819 union get_clock_dividers { 2820 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2821 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2822 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2823 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2824 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2825 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2826 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2827 }; 2828 2829 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2830 u8 clock_type, 2831 u32 clock, 2832 bool strobe_mode, 2833 struct atom_clock_dividers *dividers) 2834 { 2835 union get_clock_dividers args; 2836 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2837 u8 frev, crev; 2838 2839 memset(&args, 0, sizeof(args)); 2840 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2841 2842 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2843 return -EINVAL; 2844 2845 switch (crev) { 2846 case 1: 2847 /* r4xx, r5xx */ 2848 args.v1.ucAction = clock_type; 2849 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2850 2851 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2852 2853 dividers->post_div = args.v1.ucPostDiv; 2854 dividers->fb_div = args.v1.ucFbDiv; 2855 dividers->enable_post_div = true; 2856 break; 2857 case 2: 2858 case 3: 2859 case 5: 2860 /* r6xx, r7xx, evergreen, ni, si */ 2861 if (rdev->family <= CHIP_RV770) { 2862 args.v2.ucAction = clock_type; 2863 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2864 2865 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2866 2867 dividers->post_div = args.v2.ucPostDiv; 2868 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2869 dividers->ref_div = args.v2.ucAction; 2870 if (rdev->family == CHIP_RV770) { 2871 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2872 true : false; 2873 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2874 } else 2875 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2876 } else { 2877 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2878 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2879 2880 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2881 2882 dividers->post_div = args.v3.ucPostDiv; 2883 dividers->enable_post_div = (args.v3.ucCntlFlag & 2884 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2885 dividers->enable_dithen = (args.v3.ucCntlFlag & 2886 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2887 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2888 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2889 dividers->ref_div = args.v3.ucRefDiv; 2890 dividers->vco_mode = (args.v3.ucCntlFlag & 2891 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2892 } else { 2893 /* for SI we use ComputeMemoryClockParam for memory plls */ 2894 if (rdev->family >= CHIP_TAHITI) 2895 return -EINVAL; 2896 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2897 if (strobe_mode) 2898 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2899 2900 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2901 2902 dividers->post_div = args.v5.ucPostDiv; 2903 dividers->enable_post_div = (args.v5.ucCntlFlag & 2904 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2905 dividers->enable_dithen = (args.v5.ucCntlFlag & 2906 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2907 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2908 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2909 dividers->ref_div = args.v5.ucRefDiv; 2910 dividers->vco_mode = (args.v5.ucCntlFlag & 2911 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2912 } 2913 } 2914 break; 2915 case 4: 2916 /* fusion */ 2917 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2918 2919 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2920 2921 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2922 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2923 break; 2924 case 6: 2925 /* CI */ 2926 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2927 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2928 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2929 2930 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2931 2932 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2933 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2934 dividers->ref_div = args.v6_out.ucPllRefDiv; 2935 dividers->post_div = args.v6_out.ucPllPostDiv; 2936 dividers->flags = args.v6_out.ucPllCntlFlag; 2937 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2938 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2939 break; 2940 default: 2941 return -EINVAL; 2942 } 2943 return 0; 2944 } 2945 2946 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2947 u32 clock, 2948 bool strobe_mode, 2949 struct atom_mpll_param *mpll_param) 2950 { 2951 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2952 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2953 u8 frev, crev; 2954 2955 memset(&args, 0, sizeof(args)); 2956 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2957 2958 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2959 return -EINVAL; 2960 2961 switch (frev) { 2962 case 2: 2963 switch (crev) { 2964 case 1: 2965 /* SI */ 2966 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2967 args.ucInputFlag = 0; 2968 if (strobe_mode) 2969 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2970 2971 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2972 2973 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2974 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2975 mpll_param->post_div = args.ucPostDiv; 2976 mpll_param->dll_speed = args.ucDllSpeed; 2977 mpll_param->bwcntl = args.ucBWCntl; 2978 mpll_param->vco_mode = 2979 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2980 mpll_param->yclk_sel = 2981 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2982 mpll_param->qdr = 2983 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2984 mpll_param->half_rate = 2985 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2986 break; 2987 default: 2988 return -EINVAL; 2989 } 2990 break; 2991 default: 2992 return -EINVAL; 2993 } 2994 return 0; 2995 } 2996 2997 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2998 { 2999 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 3000 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 3001 3002 args.ucEnable = enable; 3003 3004 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3005 } 3006 3007 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 3008 { 3009 GET_ENGINE_CLOCK_PS_ALLOCATION args; 3010 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 3011 3012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3013 return le32_to_cpu(args.ulReturnEngineClock); 3014 } 3015 3016 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 3017 { 3018 GET_MEMORY_CLOCK_PS_ALLOCATION args; 3019 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 3020 3021 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3022 return le32_to_cpu(args.ulReturnMemoryClock); 3023 } 3024 3025 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 3026 uint32_t eng_clock) 3027 { 3028 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3029 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3030 3031 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3032 3033 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3034 } 3035 3036 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3037 uint32_t mem_clock) 3038 { 3039 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3040 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3041 3042 if (rdev->flags & RADEON_IS_IGP) 3043 return; 3044 3045 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3046 3047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3048 } 3049 3050 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3051 u32 eng_clock, u32 mem_clock) 3052 { 3053 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3054 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3055 u32 tmp; 3056 3057 memset(&args, 0, sizeof(args)); 3058 3059 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3060 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3061 3062 args.ulTargetEngineClock = cpu_to_le32(tmp); 3063 if (mem_clock) 3064 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3065 3066 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3067 } 3068 3069 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3070 u32 mem_clock) 3071 { 3072 u32 args; 3073 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3074 3075 args = cpu_to_le32(mem_clock); /* 10 khz */ 3076 3077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3078 } 3079 3080 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3081 u32 mem_clock) 3082 { 3083 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3084 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3085 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3086 3087 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3088 3089 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3090 } 3091 3092 union set_voltage { 3093 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3094 struct _SET_VOLTAGE_PARAMETERS v1; 3095 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3096 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3097 }; 3098 3099 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3100 { 3101 union set_voltage args; 3102 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3103 u8 frev, crev, volt_index = voltage_level; 3104 3105 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3106 return; 3107 3108 /* 0xff01 is a flag rather then an actual voltage */ 3109 if (voltage_level == 0xff01) 3110 return; 3111 3112 switch (crev) { 3113 case 1: 3114 args.v1.ucVoltageType = voltage_type; 3115 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3116 args.v1.ucVoltageIndex = volt_index; 3117 break; 3118 case 2: 3119 args.v2.ucVoltageType = voltage_type; 3120 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3121 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3122 break; 3123 case 3: 3124 args.v3.ucVoltageType = voltage_type; 3125 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3126 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3127 break; 3128 default: 3129 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3130 return; 3131 } 3132 3133 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3134 } 3135 3136 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3137 u16 voltage_id, u16 *voltage) 3138 { 3139 union set_voltage args; 3140 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3141 u8 frev, crev; 3142 3143 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3144 return -EINVAL; 3145 3146 switch (crev) { 3147 case 1: 3148 return -EINVAL; 3149 case 2: 3150 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3151 args.v2.ucVoltageMode = 0; 3152 args.v2.usVoltageLevel = 0; 3153 3154 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3155 3156 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3157 break; 3158 case 3: 3159 args.v3.ucVoltageType = voltage_type; 3160 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3161 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3162 3163 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3164 3165 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3166 break; 3167 default: 3168 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3169 return -EINVAL; 3170 } 3171 3172 return 0; 3173 } 3174 3175 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3176 u16 *voltage, 3177 u16 leakage_idx) 3178 { 3179 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3180 } 3181 3182 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3183 u16 *leakage_id) 3184 { 3185 union set_voltage args; 3186 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3187 u8 frev, crev; 3188 3189 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3190 return -EINVAL; 3191 3192 switch (crev) { 3193 case 3: 3194 case 4: 3195 args.v3.ucVoltageType = 0; 3196 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3197 args.v3.usVoltageLevel = 0; 3198 3199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3200 3201 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3202 break; 3203 default: 3204 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3205 return -EINVAL; 3206 } 3207 3208 return 0; 3209 } 3210 3211 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3212 u16 *vddc, u16 *vddci, 3213 u16 virtual_voltage_id, 3214 u16 vbios_voltage_id) 3215 { 3216 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3217 u8 frev, crev; 3218 u16 data_offset, size; 3219 int i, j; 3220 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3221 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3222 3223 *vddc = 0; 3224 *vddci = 0; 3225 3226 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3227 &frev, &crev, &data_offset)) 3228 return -EINVAL; 3229 3230 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3231 (rdev->mode_info.atom_context->bios + data_offset); 3232 3233 switch (frev) { 3234 case 1: 3235 return -EINVAL; 3236 case 2: 3237 switch (crev) { 3238 case 1: 3239 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3240 return -EINVAL; 3241 leakage_bin = (u16 *) 3242 (rdev->mode_info.atom_context->bios + data_offset + 3243 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3244 vddc_id_buf = (u16 *) 3245 (rdev->mode_info.atom_context->bios + data_offset + 3246 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3247 vddc_buf = (u16 *) 3248 (rdev->mode_info.atom_context->bios + data_offset + 3249 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3250 vddci_id_buf = (u16 *) 3251 (rdev->mode_info.atom_context->bios + data_offset + 3252 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3253 vddci_buf = (u16 *) 3254 (rdev->mode_info.atom_context->bios + data_offset + 3255 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3256 3257 if (profile->ucElbVDDC_Num > 0) { 3258 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3259 if (vddc_id_buf[i] == virtual_voltage_id) { 3260 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3261 if (vbios_voltage_id <= leakage_bin[j]) { 3262 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3263 break; 3264 } 3265 } 3266 break; 3267 } 3268 } 3269 } 3270 if (profile->ucElbVDDCI_Num > 0) { 3271 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3272 if (vddci_id_buf[i] == virtual_voltage_id) { 3273 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3274 if (vbios_voltage_id <= leakage_bin[j]) { 3275 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3276 break; 3277 } 3278 } 3279 break; 3280 } 3281 } 3282 } 3283 break; 3284 default: 3285 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3286 return -EINVAL; 3287 } 3288 break; 3289 default: 3290 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3291 return -EINVAL; 3292 } 3293 3294 return 0; 3295 } 3296 3297 union get_voltage_info { 3298 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3299 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3300 }; 3301 3302 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3303 u16 virtual_voltage_id, 3304 u16 *voltage) 3305 { 3306 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3307 u32 entry_id; 3308 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3309 union get_voltage_info args; 3310 3311 for (entry_id = 0; entry_id < count; entry_id++) { 3312 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3313 virtual_voltage_id) 3314 break; 3315 } 3316 3317 if (entry_id >= count) 3318 return -EINVAL; 3319 3320 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3321 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3322 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3323 args.in.ulSCLKFreq = 3324 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3325 3326 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3327 3328 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3329 3330 return 0; 3331 } 3332 3333 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3334 u16 voltage_level, u8 voltage_type, 3335 u32 *gpio_value, u32 *gpio_mask) 3336 { 3337 union set_voltage args; 3338 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3339 u8 frev, crev; 3340 3341 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3342 return -EINVAL; 3343 3344 switch (crev) { 3345 case 1: 3346 return -EINVAL; 3347 case 2: 3348 args.v2.ucVoltageType = voltage_type; 3349 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3350 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3351 3352 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3353 3354 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3355 3356 args.v2.ucVoltageType = voltage_type; 3357 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3358 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3359 3360 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3361 3362 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3363 break; 3364 default: 3365 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3366 return -EINVAL; 3367 } 3368 3369 return 0; 3370 } 3371 3372 union voltage_object_info { 3373 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3374 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3375 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3376 }; 3377 3378 union voltage_object { 3379 struct _ATOM_VOLTAGE_OBJECT v1; 3380 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3381 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3382 }; 3383 3384 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3385 u8 voltage_type) 3386 { 3387 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3388 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3389 u8 *start = (u8 *)v1; 3390 3391 while (offset < size) { 3392 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3393 if (vo->ucVoltageType == voltage_type) 3394 return vo; 3395 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3396 vo->asFormula.ucNumOfVoltageEntries; 3397 } 3398 return NULL; 3399 } 3400 3401 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3402 u8 voltage_type) 3403 { 3404 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3405 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3406 u8 *start = (u8*)v2; 3407 3408 while (offset < size) { 3409 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3410 if (vo->ucVoltageType == voltage_type) 3411 return vo; 3412 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3413 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3414 } 3415 return NULL; 3416 } 3417 3418 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3419 u8 voltage_type, u8 voltage_mode) 3420 { 3421 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3422 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3423 u8 *start = (u8*)v3; 3424 3425 while (offset < size) { 3426 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3427 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3428 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3429 return vo; 3430 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3431 } 3432 return NULL; 3433 } 3434 3435 bool 3436 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3437 u8 voltage_type, u8 voltage_mode) 3438 { 3439 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3440 u8 frev, crev; 3441 u16 data_offset, size; 3442 union voltage_object_info *voltage_info; 3443 union voltage_object *voltage_object = NULL; 3444 3445 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3446 &frev, &crev, &data_offset)) { 3447 voltage_info = (union voltage_object_info *) 3448 (rdev->mode_info.atom_context->bios + data_offset); 3449 3450 switch (frev) { 3451 case 1: 3452 case 2: 3453 switch (crev) { 3454 case 1: 3455 voltage_object = (union voltage_object *) 3456 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3457 if (voltage_object && 3458 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3459 return true; 3460 break; 3461 case 2: 3462 voltage_object = (union voltage_object *) 3463 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3464 if (voltage_object && 3465 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3466 return true; 3467 break; 3468 default: 3469 DRM_ERROR("unknown voltage object table\n"); 3470 return false; 3471 } 3472 break; 3473 case 3: 3474 switch (crev) { 3475 case 1: 3476 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3477 voltage_type, voltage_mode)) 3478 return true; 3479 break; 3480 default: 3481 DRM_ERROR("unknown voltage object table\n"); 3482 return false; 3483 } 3484 break; 3485 default: 3486 DRM_ERROR("unknown voltage object table\n"); 3487 return false; 3488 } 3489 3490 } 3491 return false; 3492 } 3493 3494 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3495 u8 voltage_type, 3496 u8 *svd_gpio_id, u8 *svc_gpio_id) 3497 { 3498 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3499 u8 frev, crev; 3500 u16 data_offset, size; 3501 union voltage_object_info *voltage_info; 3502 union voltage_object *voltage_object = NULL; 3503 3504 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3505 &frev, &crev, &data_offset)) { 3506 voltage_info = (union voltage_object_info *) 3507 (rdev->mode_info.atom_context->bios + data_offset); 3508 3509 switch (frev) { 3510 case 3: 3511 switch (crev) { 3512 case 1: 3513 voltage_object = (union voltage_object *) 3514 atom_lookup_voltage_object_v3(&voltage_info->v3, 3515 voltage_type, 3516 VOLTAGE_OBJ_SVID2); 3517 if (voltage_object) { 3518 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3519 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3520 } else { 3521 return -EINVAL; 3522 } 3523 break; 3524 default: 3525 DRM_ERROR("unknown voltage object table\n"); 3526 return -EINVAL; 3527 } 3528 break; 3529 default: 3530 DRM_ERROR("unknown voltage object table\n"); 3531 return -EINVAL; 3532 } 3533 3534 } 3535 return 0; 3536 } 3537 3538 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3539 u8 voltage_type, u16 *max_voltage) 3540 { 3541 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3542 u8 frev, crev; 3543 u16 data_offset, size; 3544 union voltage_object_info *voltage_info; 3545 union voltage_object *voltage_object = NULL; 3546 3547 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3548 &frev, &crev, &data_offset)) { 3549 voltage_info = (union voltage_object_info *) 3550 (rdev->mode_info.atom_context->bios + data_offset); 3551 3552 switch (crev) { 3553 case 1: 3554 voltage_object = (union voltage_object *) 3555 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3556 if (voltage_object) { 3557 ATOM_VOLTAGE_FORMULA *formula = 3558 &voltage_object->v1.asFormula; 3559 if (formula->ucFlag & 1) 3560 *max_voltage = 3561 le16_to_cpu(formula->usVoltageBaseLevel) + 3562 formula->ucNumOfVoltageEntries / 2 * 3563 le16_to_cpu(formula->usVoltageStep); 3564 else 3565 *max_voltage = 3566 le16_to_cpu(formula->usVoltageBaseLevel) + 3567 (formula->ucNumOfVoltageEntries - 1) * 3568 le16_to_cpu(formula->usVoltageStep); 3569 return 0; 3570 } 3571 break; 3572 case 2: 3573 voltage_object = (union voltage_object *) 3574 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3575 if (voltage_object) { 3576 ATOM_VOLTAGE_FORMULA_V2 *formula = 3577 &voltage_object->v2.asFormula; 3578 if (formula->ucNumOfVoltageEntries) { 3579 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3580 ((u8 *)&formula->asVIDAdjustEntries[0] + 3581 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3582 *max_voltage = 3583 le16_to_cpu(lut->usVoltageValue); 3584 return 0; 3585 } 3586 } 3587 break; 3588 default: 3589 DRM_ERROR("unknown voltage object table\n"); 3590 return -EINVAL; 3591 } 3592 3593 } 3594 return -EINVAL; 3595 } 3596 3597 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3598 u8 voltage_type, u16 *min_voltage) 3599 { 3600 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3601 u8 frev, crev; 3602 u16 data_offset, size; 3603 union voltage_object_info *voltage_info; 3604 union voltage_object *voltage_object = NULL; 3605 3606 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3607 &frev, &crev, &data_offset)) { 3608 voltage_info = (union voltage_object_info *) 3609 (rdev->mode_info.atom_context->bios + data_offset); 3610 3611 switch (crev) { 3612 case 1: 3613 voltage_object = (union voltage_object *) 3614 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3615 if (voltage_object) { 3616 ATOM_VOLTAGE_FORMULA *formula = 3617 &voltage_object->v1.asFormula; 3618 *min_voltage = 3619 le16_to_cpu(formula->usVoltageBaseLevel); 3620 return 0; 3621 } 3622 break; 3623 case 2: 3624 voltage_object = (union voltage_object *) 3625 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3626 if (voltage_object) { 3627 ATOM_VOLTAGE_FORMULA_V2 *formula = 3628 &voltage_object->v2.asFormula; 3629 if (formula->ucNumOfVoltageEntries) { 3630 *min_voltage = 3631 le16_to_cpu(formula->asVIDAdjustEntries[ 3632 0 3633 ].usVoltageValue); 3634 return 0; 3635 } 3636 } 3637 break; 3638 default: 3639 DRM_ERROR("unknown voltage object table\n"); 3640 return -EINVAL; 3641 } 3642 3643 } 3644 return -EINVAL; 3645 } 3646 3647 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3648 u8 voltage_type, u16 *voltage_step) 3649 { 3650 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3651 u8 frev, crev; 3652 u16 data_offset, size; 3653 union voltage_object_info *voltage_info; 3654 union voltage_object *voltage_object = NULL; 3655 3656 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3657 &frev, &crev, &data_offset)) { 3658 voltage_info = (union voltage_object_info *) 3659 (rdev->mode_info.atom_context->bios + data_offset); 3660 3661 switch (crev) { 3662 case 1: 3663 voltage_object = (union voltage_object *) 3664 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3665 if (voltage_object) { 3666 ATOM_VOLTAGE_FORMULA *formula = 3667 &voltage_object->v1.asFormula; 3668 if (formula->ucFlag & 1) 3669 *voltage_step = 3670 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3671 else 3672 *voltage_step = 3673 le16_to_cpu(formula->usVoltageStep); 3674 return 0; 3675 } 3676 break; 3677 case 2: 3678 return -EINVAL; 3679 default: 3680 DRM_ERROR("unknown voltage object table\n"); 3681 return -EINVAL; 3682 } 3683 3684 } 3685 return -EINVAL; 3686 } 3687 3688 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3689 u8 voltage_type, 3690 u16 nominal_voltage, 3691 u16 *true_voltage) 3692 { 3693 u16 min_voltage, max_voltage, voltage_step; 3694 3695 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3696 return -EINVAL; 3697 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3698 return -EINVAL; 3699 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3700 return -EINVAL; 3701 3702 if (nominal_voltage <= min_voltage) 3703 *true_voltage = min_voltage; 3704 else if (nominal_voltage >= max_voltage) 3705 *true_voltage = max_voltage; 3706 else 3707 *true_voltage = min_voltage + 3708 ((nominal_voltage - min_voltage) / voltage_step) * 3709 voltage_step; 3710 3711 return 0; 3712 } 3713 3714 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3715 u8 voltage_type, u8 voltage_mode, 3716 struct atom_voltage_table *voltage_table) 3717 { 3718 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3719 u8 frev, crev; 3720 u16 data_offset, size; 3721 int i, ret; 3722 union voltage_object_info *voltage_info; 3723 union voltage_object *voltage_object = NULL; 3724 3725 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3726 &frev, &crev, &data_offset)) { 3727 voltage_info = (union voltage_object_info *) 3728 (rdev->mode_info.atom_context->bios + data_offset); 3729 3730 switch (frev) { 3731 case 1: 3732 case 2: 3733 switch (crev) { 3734 case 1: 3735 DRM_ERROR("old table version %d, %d\n", frev, crev); 3736 return -EINVAL; 3737 case 2: 3738 voltage_object = (union voltage_object *) 3739 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3740 if (voltage_object) { 3741 ATOM_VOLTAGE_FORMULA_V2 *formula = 3742 &voltage_object->v2.asFormula; 3743 VOLTAGE_LUT_ENTRY *lut; 3744 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3745 return -EINVAL; 3746 lut = &formula->asVIDAdjustEntries[0]; 3747 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3748 voltage_table->entries[i].value = 3749 le16_to_cpu(lut->usVoltageValue); 3750 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3751 voltage_table->entries[i].value, 3752 voltage_type, 3753 &voltage_table->entries[i].smio_low, 3754 &voltage_table->mask_low); 3755 if (ret) 3756 return ret; 3757 lut = (VOLTAGE_LUT_ENTRY *) 3758 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3759 } 3760 voltage_table->count = formula->ucNumOfVoltageEntries; 3761 return 0; 3762 } 3763 break; 3764 default: 3765 DRM_ERROR("unknown voltage object table\n"); 3766 return -EINVAL; 3767 } 3768 break; 3769 case 3: 3770 switch (crev) { 3771 case 1: 3772 voltage_object = (union voltage_object *) 3773 atom_lookup_voltage_object_v3(&voltage_info->v3, 3774 voltage_type, voltage_mode); 3775 if (voltage_object) { 3776 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3777 &voltage_object->v3.asGpioVoltageObj; 3778 VOLTAGE_LUT_ENTRY_V2 *lut; 3779 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3780 return -EINVAL; 3781 lut = &gpio->asVolGpioLut[0]; 3782 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3783 voltage_table->entries[i].value = 3784 le16_to_cpu(lut->usVoltageValue); 3785 voltage_table->entries[i].smio_low = 3786 le32_to_cpu(lut->ulVoltageId); 3787 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3788 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3789 } 3790 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3791 voltage_table->count = gpio->ucGpioEntryNum; 3792 voltage_table->phase_delay = gpio->ucPhaseDelay; 3793 return 0; 3794 } 3795 break; 3796 default: 3797 DRM_ERROR("unknown voltage object table\n"); 3798 return -EINVAL; 3799 } 3800 break; 3801 default: 3802 DRM_ERROR("unknown voltage object table\n"); 3803 return -EINVAL; 3804 } 3805 } 3806 return -EINVAL; 3807 } 3808 3809 union vram_info { 3810 struct _ATOM_VRAM_INFO_V3 v1_3; 3811 struct _ATOM_VRAM_INFO_V4 v1_4; 3812 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3813 }; 3814 3815 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3816 u8 module_index, struct atom_memory_info *mem_info) 3817 { 3818 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3819 u8 frev, crev, i; 3820 u16 data_offset, size; 3821 union vram_info *vram_info; 3822 3823 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3824 3825 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3826 &frev, &crev, &data_offset)) { 3827 vram_info = (union vram_info *) 3828 (rdev->mode_info.atom_context->bios + data_offset); 3829 switch (frev) { 3830 case 1: 3831 switch (crev) { 3832 case 3: 3833 /* r6xx */ 3834 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3835 ATOM_VRAM_MODULE_V3 *vram_module = 3836 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3837 3838 for (i = 0; i < module_index; i++) { 3839 if (le16_to_cpu(vram_module->usSize) == 0) 3840 return -EINVAL; 3841 vram_module = (ATOM_VRAM_MODULE_V3 *) 3842 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3843 } 3844 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3845 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3846 } else 3847 return -EINVAL; 3848 break; 3849 case 4: 3850 /* r7xx, evergreen */ 3851 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3852 ATOM_VRAM_MODULE_V4 *vram_module = 3853 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3854 3855 for (i = 0; i < module_index; i++) { 3856 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3857 return -EINVAL; 3858 vram_module = (ATOM_VRAM_MODULE_V4 *) 3859 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3860 } 3861 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3862 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3863 } else 3864 return -EINVAL; 3865 break; 3866 default: 3867 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3868 return -EINVAL; 3869 } 3870 break; 3871 case 2: 3872 switch (crev) { 3873 case 1: 3874 /* ni */ 3875 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3876 ATOM_VRAM_MODULE_V7 *vram_module = 3877 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3878 3879 for (i = 0; i < module_index; i++) { 3880 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3881 return -EINVAL; 3882 vram_module = (ATOM_VRAM_MODULE_V7 *) 3883 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3884 } 3885 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3886 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3887 } else 3888 return -EINVAL; 3889 break; 3890 default: 3891 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3892 return -EINVAL; 3893 } 3894 break; 3895 default: 3896 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3897 return -EINVAL; 3898 } 3899 return 0; 3900 } 3901 return -EINVAL; 3902 } 3903 3904 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3905 bool gddr5, u8 module_index, 3906 struct atom_memory_clock_range_table *mclk_range_table) 3907 { 3908 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3909 u8 frev, crev, i; 3910 u16 data_offset, size; 3911 union vram_info *vram_info; 3912 u32 mem_timing_size = gddr5 ? 3913 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3914 3915 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3916 3917 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3918 &frev, &crev, &data_offset)) { 3919 vram_info = (union vram_info *) 3920 (rdev->mode_info.atom_context->bios + data_offset); 3921 switch (frev) { 3922 case 1: 3923 switch (crev) { 3924 case 3: 3925 DRM_ERROR("old table version %d, %d\n", frev, crev); 3926 return -EINVAL; 3927 case 4: 3928 /* r7xx, evergreen */ 3929 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3930 ATOM_VRAM_MODULE_V4 *vram_module = 3931 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3932 ATOM_MEMORY_TIMING_FORMAT *format; 3933 3934 for (i = 0; i < module_index; i++) { 3935 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3936 return -EINVAL; 3937 vram_module = (ATOM_VRAM_MODULE_V4 *) 3938 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3939 } 3940 mclk_range_table->num_entries = (u8) 3941 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3942 mem_timing_size); 3943 format = &vram_module->asMemTiming[0]; 3944 for (i = 0; i < mclk_range_table->num_entries; i++) { 3945 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3946 format = (ATOM_MEMORY_TIMING_FORMAT *) 3947 ((u8 *)format + mem_timing_size); 3948 } 3949 } else 3950 return -EINVAL; 3951 break; 3952 default: 3953 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3954 return -EINVAL; 3955 } 3956 break; 3957 case 2: 3958 DRM_ERROR("new table version %d, %d\n", frev, crev); 3959 return -EINVAL; 3960 default: 3961 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3962 return -EINVAL; 3963 } 3964 return 0; 3965 } 3966 return -EINVAL; 3967 } 3968 3969 #define MEM_ID_MASK 0xff000000 3970 #define MEM_ID_SHIFT 24 3971 #define CLOCK_RANGE_MASK 0x00ffffff 3972 #define CLOCK_RANGE_SHIFT 0 3973 #define LOW_NIBBLE_MASK 0xf 3974 #define DATA_EQU_PREV 0 3975 #define DATA_FROM_TABLE 4 3976 3977 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3978 u8 module_index, 3979 struct atom_mc_reg_table *reg_table) 3980 { 3981 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3982 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3983 u32 i = 0, j; 3984 u16 data_offset, size; 3985 union vram_info *vram_info; 3986 3987 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3988 3989 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3990 &frev, &crev, &data_offset)) { 3991 vram_info = (union vram_info *) 3992 (rdev->mode_info.atom_context->bios + data_offset); 3993 switch (frev) { 3994 case 1: 3995 DRM_ERROR("old table version %d, %d\n", frev, crev); 3996 return -EINVAL; 3997 case 2: 3998 switch (crev) { 3999 case 1: 4000 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 4001 ATOM_INIT_REG_BLOCK *reg_block = 4002 (ATOM_INIT_REG_BLOCK *) 4003 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 4004 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 4005 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4006 ((u8 *)reg_block + (2 * sizeof(u16)) + 4007 le16_to_cpu(reg_block->usRegIndexTblSize)); 4008 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 4009 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 4010 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 4011 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 4012 return -EINVAL; 4013 while (i < num_entries) { 4014 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 4015 break; 4016 reg_table->mc_reg_address[i].s1 = 4017 (u16)(le16_to_cpu(format->usRegIndex)); 4018 reg_table->mc_reg_address[i].pre_reg_data = 4019 (u8)(format->ucPreRegDataLength); 4020 i++; 4021 format = (ATOM_INIT_REG_INDEX_FORMAT *) 4022 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 4023 } 4024 reg_table->last = i; 4025 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4026 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 4027 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4028 >> MEM_ID_SHIFT); 4029 if (module_index == t_mem_id) { 4030 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4031 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4032 >> CLOCK_RANGE_SHIFT); 4033 for (i = 0, j = 1; i < reg_table->last; i++) { 4034 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4035 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4036 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4037 j++; 4038 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4039 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4040 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4041 } 4042 } 4043 num_ranges++; 4044 } 4045 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4046 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4047 } 4048 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4049 return -EINVAL; 4050 reg_table->num_entries = num_ranges; 4051 } else 4052 return -EINVAL; 4053 break; 4054 default: 4055 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4056 return -EINVAL; 4057 } 4058 break; 4059 default: 4060 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4061 return -EINVAL; 4062 } 4063 return 0; 4064 } 4065 return -EINVAL; 4066 } 4067 4068 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4069 { 4070 struct radeon_device *rdev = dev->dev_private; 4071 uint32_t bios_2_scratch, bios_6_scratch; 4072 4073 if (rdev->family >= CHIP_R600) { 4074 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4075 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4076 } else { 4077 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4078 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4079 } 4080 4081 /* let the bios control the backlight */ 4082 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4083 4084 /* tell the bios not to handle mode switching */ 4085 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4086 4087 /* clear the vbios dpms state */ 4088 if (ASIC_IS_DCE4(rdev)) 4089 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4090 4091 if (rdev->family >= CHIP_R600) { 4092 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4093 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4094 } else { 4095 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4096 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4097 } 4098 4099 } 4100 4101 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4102 { 4103 uint32_t scratch_reg; 4104 int i; 4105 4106 if (rdev->family >= CHIP_R600) 4107 scratch_reg = R600_BIOS_0_SCRATCH; 4108 else 4109 scratch_reg = RADEON_BIOS_0_SCRATCH; 4110 4111 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4112 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4113 } 4114 4115 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4116 { 4117 uint32_t scratch_reg; 4118 int i; 4119 4120 if (rdev->family >= CHIP_R600) 4121 scratch_reg = R600_BIOS_0_SCRATCH; 4122 else 4123 scratch_reg = RADEON_BIOS_0_SCRATCH; 4124 4125 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4126 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4127 } 4128 4129 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4130 { 4131 struct drm_device *dev = encoder->dev; 4132 struct radeon_device *rdev = dev->dev_private; 4133 uint32_t bios_6_scratch; 4134 4135 if (rdev->family >= CHIP_R600) 4136 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4137 else 4138 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4139 4140 if (lock) { 4141 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4142 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4143 } else { 4144 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4145 bios_6_scratch |= ATOM_S6_ACC_MODE; 4146 } 4147 4148 if (rdev->family >= CHIP_R600) 4149 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4150 else 4151 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4152 } 4153 4154 /* at some point we may want to break this out into individual functions */ 4155 void 4156 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4157 struct drm_encoder *encoder, 4158 bool connected) 4159 { 4160 struct drm_device *dev = connector->dev; 4161 struct radeon_device *rdev = dev->dev_private; 4162 struct radeon_connector *radeon_connector = 4163 to_radeon_connector(connector); 4164 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4165 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4166 4167 if (rdev->family >= CHIP_R600) { 4168 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4169 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4170 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4171 } else { 4172 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4173 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4174 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4175 } 4176 4177 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4178 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4179 if (connected) { 4180 DRM_DEBUG_KMS("TV1 connected\n"); 4181 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4182 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4183 } else { 4184 DRM_DEBUG_KMS("TV1 disconnected\n"); 4185 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4186 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4187 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4188 } 4189 } 4190 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4191 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4192 if (connected) { 4193 DRM_DEBUG_KMS("CV connected\n"); 4194 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4195 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4196 } else { 4197 DRM_DEBUG_KMS("CV disconnected\n"); 4198 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4199 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4200 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4201 } 4202 } 4203 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4204 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4205 if (connected) { 4206 DRM_DEBUG_KMS("LCD1 connected\n"); 4207 bios_0_scratch |= ATOM_S0_LCD1; 4208 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4209 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4210 } else { 4211 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4212 bios_0_scratch &= ~ATOM_S0_LCD1; 4213 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4214 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4215 } 4216 } 4217 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4218 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4219 if (connected) { 4220 DRM_DEBUG_KMS("CRT1 connected\n"); 4221 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4222 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4223 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4224 } else { 4225 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4226 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4227 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4228 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4229 } 4230 } 4231 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4232 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4233 if (connected) { 4234 DRM_DEBUG_KMS("CRT2 connected\n"); 4235 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4236 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4237 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4238 } else { 4239 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4240 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4241 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4242 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4243 } 4244 } 4245 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4246 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4247 if (connected) { 4248 DRM_DEBUG_KMS("DFP1 connected\n"); 4249 bios_0_scratch |= ATOM_S0_DFP1; 4250 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4251 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4252 } else { 4253 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4254 bios_0_scratch &= ~ATOM_S0_DFP1; 4255 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4256 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4257 } 4258 } 4259 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4260 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4261 if (connected) { 4262 DRM_DEBUG_KMS("DFP2 connected\n"); 4263 bios_0_scratch |= ATOM_S0_DFP2; 4264 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4265 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4266 } else { 4267 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4268 bios_0_scratch &= ~ATOM_S0_DFP2; 4269 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4270 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4271 } 4272 } 4273 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4274 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4275 if (connected) { 4276 DRM_DEBUG_KMS("DFP3 connected\n"); 4277 bios_0_scratch |= ATOM_S0_DFP3; 4278 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4279 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4280 } else { 4281 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4282 bios_0_scratch &= ~ATOM_S0_DFP3; 4283 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4284 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4285 } 4286 } 4287 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4288 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4289 if (connected) { 4290 DRM_DEBUG_KMS("DFP4 connected\n"); 4291 bios_0_scratch |= ATOM_S0_DFP4; 4292 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4293 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4294 } else { 4295 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4296 bios_0_scratch &= ~ATOM_S0_DFP4; 4297 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4298 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4299 } 4300 } 4301 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4302 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4303 if (connected) { 4304 DRM_DEBUG_KMS("DFP5 connected\n"); 4305 bios_0_scratch |= ATOM_S0_DFP5; 4306 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4307 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4308 } else { 4309 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4310 bios_0_scratch &= ~ATOM_S0_DFP5; 4311 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4312 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4313 } 4314 } 4315 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4316 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4317 if (connected) { 4318 DRM_DEBUG_KMS("DFP6 connected\n"); 4319 bios_0_scratch |= ATOM_S0_DFP6; 4320 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4321 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4322 } else { 4323 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4324 bios_0_scratch &= ~ATOM_S0_DFP6; 4325 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4326 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4327 } 4328 } 4329 4330 if (rdev->family >= CHIP_R600) { 4331 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4332 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4333 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4334 } else { 4335 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4336 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4337 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4338 } 4339 } 4340 4341 void 4342 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4343 { 4344 struct drm_device *dev = encoder->dev; 4345 struct radeon_device *rdev = dev->dev_private; 4346 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4347 uint32_t bios_3_scratch; 4348 4349 if (ASIC_IS_DCE4(rdev)) 4350 return; 4351 4352 if (rdev->family >= CHIP_R600) 4353 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4354 else 4355 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4356 4357 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4358 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4359 bios_3_scratch |= (crtc << 18); 4360 } 4361 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4362 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4363 bios_3_scratch |= (crtc << 24); 4364 } 4365 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4366 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4367 bios_3_scratch |= (crtc << 16); 4368 } 4369 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4370 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4371 bios_3_scratch |= (crtc << 20); 4372 } 4373 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4374 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4375 bios_3_scratch |= (crtc << 17); 4376 } 4377 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4378 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4379 bios_3_scratch |= (crtc << 19); 4380 } 4381 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4382 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4383 bios_3_scratch |= (crtc << 23); 4384 } 4385 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4386 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4387 bios_3_scratch |= (crtc << 25); 4388 } 4389 4390 if (rdev->family >= CHIP_R600) 4391 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4392 else 4393 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4394 } 4395 4396 void 4397 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4398 { 4399 struct drm_device *dev = encoder->dev; 4400 struct radeon_device *rdev = dev->dev_private; 4401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4402 uint32_t bios_2_scratch; 4403 4404 if (ASIC_IS_DCE4(rdev)) 4405 return; 4406 4407 if (rdev->family >= CHIP_R600) 4408 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4409 else 4410 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4411 4412 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4413 if (on) 4414 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4415 else 4416 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4417 } 4418 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4419 if (on) 4420 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4421 else 4422 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4423 } 4424 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4425 if (on) 4426 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4427 else 4428 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4429 } 4430 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4431 if (on) 4432 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4433 else 4434 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4435 } 4436 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4437 if (on) 4438 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4439 else 4440 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4441 } 4442 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4443 if (on) 4444 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4445 else 4446 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4447 } 4448 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4449 if (on) 4450 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4451 else 4452 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4453 } 4454 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4455 if (on) 4456 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4457 else 4458 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4459 } 4460 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4461 if (on) 4462 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4463 else 4464 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4465 } 4466 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4467 if (on) 4468 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4469 else 4470 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4471 } 4472 4473 if (rdev->family >= CHIP_R600) 4474 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4475 else 4476 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4477 } 4478