1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 126 rdev->mc_rreg = &rs780_mc_rreg; 127 rdev->mc_wreg = &rs780_mc_wreg; 128 } 129 130 if (rdev->family >= CHIP_BONAIRE) { 131 rdev->pciep_rreg = &cik_pciep_rreg; 132 rdev->pciep_wreg = &cik_pciep_wreg; 133 } else if (rdev->family >= CHIP_R600) { 134 rdev->pciep_rreg = &r600_pciep_rreg; 135 rdev->pciep_wreg = &r600_pciep_wreg; 136 } 137 } 138 139 140 /* helper to disable agp */ 141 /** 142 * radeon_agp_disable - AGP disable helper function 143 * 144 * @rdev: radeon device pointer 145 * 146 * Removes AGP flags and changes the gart callbacks on AGP 147 * cards when using the internal gart rather than AGP (all asics). 148 */ 149 void radeon_agp_disable(struct radeon_device *rdev) 150 { 151 rdev->flags &= ~RADEON_IS_AGP; 152 if (rdev->family >= CHIP_R600) { 153 DRM_INFO("Forcing AGP to PCIE mode\n"); 154 rdev->flags |= RADEON_IS_PCIE; 155 } else if (rdev->family >= CHIP_RV515 || 156 rdev->family == CHIP_RV380 || 157 rdev->family == CHIP_RV410 || 158 rdev->family == CHIP_R423) { 159 DRM_INFO("Forcing AGP to PCIE mode\n"); 160 rdev->flags |= RADEON_IS_PCIE; 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 163 } else { 164 DRM_INFO("Forcing AGP to PCI mode\n"); 165 rdev->flags |= RADEON_IS_PCI; 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 167 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 168 } 169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 170 } 171 172 /* 173 * ASIC 174 */ 175 176 static struct radeon_asic_ring r100_gfx_ring = { 177 .ib_execute = &r100_ring_ib_execute, 178 .emit_fence = &r100_fence_ring_emit, 179 .emit_semaphore = &r100_semaphore_ring_emit, 180 .cs_parse = &r100_cs_parse, 181 .ring_start = &r100_ring_start, 182 .ring_test = &r100_ring_test, 183 .ib_test = &r100_ib_test, 184 .is_lockup = &r100_gpu_is_lockup, 185 .get_rptr = &r100_gfx_get_rptr, 186 .get_wptr = &r100_gfx_get_wptr, 187 .set_wptr = &r100_gfx_set_wptr, 188 }; 189 190 static struct radeon_asic r100_asic = { 191 .init = &r100_init, 192 .fini = &r100_fini, 193 .suspend = &r100_suspend, 194 .resume = &r100_resume, 195 .vga_set_state = &r100_vga_set_state, 196 .asic_reset = &r100_asic_reset, 197 .ioctl_wait_idle = NULL, 198 .gui_idle = &r100_gui_idle, 199 .mc_wait_for_idle = &r100_mc_wait_for_idle, 200 .gart = { 201 .tlb_flush = &r100_pci_gart_tlb_flush, 202 .set_page = &r100_pci_gart_set_page, 203 }, 204 .ring = { 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 206 }, 207 .irq = { 208 .set = &r100_irq_set, 209 .process = &r100_irq_process, 210 }, 211 .display = { 212 .bandwidth_update = &r100_bandwidth_update, 213 .get_vblank_counter = &r100_get_vblank_counter, 214 .wait_for_vblank = &r100_wait_for_vblank, 215 .set_backlight_level = &radeon_legacy_set_backlight_level, 216 .get_backlight_level = &radeon_legacy_get_backlight_level, 217 }, 218 .copy = { 219 .blit = &r100_copy_blit, 220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 221 .dma = NULL, 222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 223 .copy = &r100_copy_blit, 224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 225 }, 226 .surface = { 227 .set_reg = r100_set_surface_reg, 228 .clear_reg = r100_clear_surface_reg, 229 }, 230 .hpd = { 231 .init = &r100_hpd_init, 232 .fini = &r100_hpd_fini, 233 .sense = &r100_hpd_sense, 234 .set_polarity = &r100_hpd_set_polarity, 235 }, 236 .pm = { 237 .misc = &r100_pm_misc, 238 .prepare = &r100_pm_prepare, 239 .finish = &r100_pm_finish, 240 .init_profile = &r100_pm_init_profile, 241 .get_dynpm_state = &r100_pm_get_dynpm_state, 242 .get_engine_clock = &radeon_legacy_get_engine_clock, 243 .set_engine_clock = &radeon_legacy_set_engine_clock, 244 .get_memory_clock = &radeon_legacy_get_memory_clock, 245 .set_memory_clock = NULL, 246 .get_pcie_lanes = NULL, 247 .set_pcie_lanes = NULL, 248 .set_clock_gating = &radeon_legacy_set_clock_gating, 249 }, 250 .pflip = { 251 .pre_page_flip = &r100_pre_page_flip, 252 .page_flip = &r100_page_flip, 253 .post_page_flip = &r100_post_page_flip, 254 }, 255 }; 256 257 static struct radeon_asic r200_asic = { 258 .init = &r100_init, 259 .fini = &r100_fini, 260 .suspend = &r100_suspend, 261 .resume = &r100_resume, 262 .vga_set_state = &r100_vga_set_state, 263 .asic_reset = &r100_asic_reset, 264 .ioctl_wait_idle = NULL, 265 .gui_idle = &r100_gui_idle, 266 .mc_wait_for_idle = &r100_mc_wait_for_idle, 267 .gart = { 268 .tlb_flush = &r100_pci_gart_tlb_flush, 269 .set_page = &r100_pci_gart_set_page, 270 }, 271 .ring = { 272 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 273 }, 274 .irq = { 275 .set = &r100_irq_set, 276 .process = &r100_irq_process, 277 }, 278 .display = { 279 .bandwidth_update = &r100_bandwidth_update, 280 .get_vblank_counter = &r100_get_vblank_counter, 281 .wait_for_vblank = &r100_wait_for_vblank, 282 .set_backlight_level = &radeon_legacy_set_backlight_level, 283 .get_backlight_level = &radeon_legacy_get_backlight_level, 284 }, 285 .copy = { 286 .blit = &r100_copy_blit, 287 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 288 .dma = &r200_copy_dma, 289 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 290 .copy = &r100_copy_blit, 291 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 292 }, 293 .surface = { 294 .set_reg = r100_set_surface_reg, 295 .clear_reg = r100_clear_surface_reg, 296 }, 297 .hpd = { 298 .init = &r100_hpd_init, 299 .fini = &r100_hpd_fini, 300 .sense = &r100_hpd_sense, 301 .set_polarity = &r100_hpd_set_polarity, 302 }, 303 .pm = { 304 .misc = &r100_pm_misc, 305 .prepare = &r100_pm_prepare, 306 .finish = &r100_pm_finish, 307 .init_profile = &r100_pm_init_profile, 308 .get_dynpm_state = &r100_pm_get_dynpm_state, 309 .get_engine_clock = &radeon_legacy_get_engine_clock, 310 .set_engine_clock = &radeon_legacy_set_engine_clock, 311 .get_memory_clock = &radeon_legacy_get_memory_clock, 312 .set_memory_clock = NULL, 313 .get_pcie_lanes = NULL, 314 .set_pcie_lanes = NULL, 315 .set_clock_gating = &radeon_legacy_set_clock_gating, 316 }, 317 .pflip = { 318 .pre_page_flip = &r100_pre_page_flip, 319 .page_flip = &r100_page_flip, 320 .post_page_flip = &r100_post_page_flip, 321 }, 322 }; 323 324 static struct radeon_asic_ring r300_gfx_ring = { 325 .ib_execute = &r100_ring_ib_execute, 326 .emit_fence = &r300_fence_ring_emit, 327 .emit_semaphore = &r100_semaphore_ring_emit, 328 .cs_parse = &r300_cs_parse, 329 .ring_start = &r300_ring_start, 330 .ring_test = &r100_ring_test, 331 .ib_test = &r100_ib_test, 332 .is_lockup = &r100_gpu_is_lockup, 333 .get_rptr = &r100_gfx_get_rptr, 334 .get_wptr = &r100_gfx_get_wptr, 335 .set_wptr = &r100_gfx_set_wptr, 336 }; 337 338 static struct radeon_asic r300_asic = { 339 .init = &r300_init, 340 .fini = &r300_fini, 341 .suspend = &r300_suspend, 342 .resume = &r300_resume, 343 .vga_set_state = &r100_vga_set_state, 344 .asic_reset = &r300_asic_reset, 345 .ioctl_wait_idle = NULL, 346 .gui_idle = &r100_gui_idle, 347 .mc_wait_for_idle = &r300_mc_wait_for_idle, 348 .gart = { 349 .tlb_flush = &r100_pci_gart_tlb_flush, 350 .set_page = &r100_pci_gart_set_page, 351 }, 352 .ring = { 353 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 354 }, 355 .irq = { 356 .set = &r100_irq_set, 357 .process = &r100_irq_process, 358 }, 359 .display = { 360 .bandwidth_update = &r100_bandwidth_update, 361 .get_vblank_counter = &r100_get_vblank_counter, 362 .wait_for_vblank = &r100_wait_for_vblank, 363 .set_backlight_level = &radeon_legacy_set_backlight_level, 364 .get_backlight_level = &radeon_legacy_get_backlight_level, 365 }, 366 .copy = { 367 .blit = &r100_copy_blit, 368 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 369 .dma = &r200_copy_dma, 370 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 371 .copy = &r100_copy_blit, 372 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 373 }, 374 .surface = { 375 .set_reg = r100_set_surface_reg, 376 .clear_reg = r100_clear_surface_reg, 377 }, 378 .hpd = { 379 .init = &r100_hpd_init, 380 .fini = &r100_hpd_fini, 381 .sense = &r100_hpd_sense, 382 .set_polarity = &r100_hpd_set_polarity, 383 }, 384 .pm = { 385 .misc = &r100_pm_misc, 386 .prepare = &r100_pm_prepare, 387 .finish = &r100_pm_finish, 388 .init_profile = &r100_pm_init_profile, 389 .get_dynpm_state = &r100_pm_get_dynpm_state, 390 .get_engine_clock = &radeon_legacy_get_engine_clock, 391 .set_engine_clock = &radeon_legacy_set_engine_clock, 392 .get_memory_clock = &radeon_legacy_get_memory_clock, 393 .set_memory_clock = NULL, 394 .get_pcie_lanes = &rv370_get_pcie_lanes, 395 .set_pcie_lanes = &rv370_set_pcie_lanes, 396 .set_clock_gating = &radeon_legacy_set_clock_gating, 397 }, 398 .pflip = { 399 .pre_page_flip = &r100_pre_page_flip, 400 .page_flip = &r100_page_flip, 401 .post_page_flip = &r100_post_page_flip, 402 }, 403 }; 404 405 static struct radeon_asic r300_asic_pcie = { 406 .init = &r300_init, 407 .fini = &r300_fini, 408 .suspend = &r300_suspend, 409 .resume = &r300_resume, 410 .vga_set_state = &r100_vga_set_state, 411 .asic_reset = &r300_asic_reset, 412 .ioctl_wait_idle = NULL, 413 .gui_idle = &r100_gui_idle, 414 .mc_wait_for_idle = &r300_mc_wait_for_idle, 415 .gart = { 416 .tlb_flush = &rv370_pcie_gart_tlb_flush, 417 .set_page = &rv370_pcie_gart_set_page, 418 }, 419 .ring = { 420 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 421 }, 422 .irq = { 423 .set = &r100_irq_set, 424 .process = &r100_irq_process, 425 }, 426 .display = { 427 .bandwidth_update = &r100_bandwidth_update, 428 .get_vblank_counter = &r100_get_vblank_counter, 429 .wait_for_vblank = &r100_wait_for_vblank, 430 .set_backlight_level = &radeon_legacy_set_backlight_level, 431 .get_backlight_level = &radeon_legacy_get_backlight_level, 432 }, 433 .copy = { 434 .blit = &r100_copy_blit, 435 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 436 .dma = &r200_copy_dma, 437 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 438 .copy = &r100_copy_blit, 439 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 440 }, 441 .surface = { 442 .set_reg = r100_set_surface_reg, 443 .clear_reg = r100_clear_surface_reg, 444 }, 445 .hpd = { 446 .init = &r100_hpd_init, 447 .fini = &r100_hpd_fini, 448 .sense = &r100_hpd_sense, 449 .set_polarity = &r100_hpd_set_polarity, 450 }, 451 .pm = { 452 .misc = &r100_pm_misc, 453 .prepare = &r100_pm_prepare, 454 .finish = &r100_pm_finish, 455 .init_profile = &r100_pm_init_profile, 456 .get_dynpm_state = &r100_pm_get_dynpm_state, 457 .get_engine_clock = &radeon_legacy_get_engine_clock, 458 .set_engine_clock = &radeon_legacy_set_engine_clock, 459 .get_memory_clock = &radeon_legacy_get_memory_clock, 460 .set_memory_clock = NULL, 461 .get_pcie_lanes = &rv370_get_pcie_lanes, 462 .set_pcie_lanes = &rv370_set_pcie_lanes, 463 .set_clock_gating = &radeon_legacy_set_clock_gating, 464 }, 465 .pflip = { 466 .pre_page_flip = &r100_pre_page_flip, 467 .page_flip = &r100_page_flip, 468 .post_page_flip = &r100_post_page_flip, 469 }, 470 }; 471 472 static struct radeon_asic r420_asic = { 473 .init = &r420_init, 474 .fini = &r420_fini, 475 .suspend = &r420_suspend, 476 .resume = &r420_resume, 477 .vga_set_state = &r100_vga_set_state, 478 .asic_reset = &r300_asic_reset, 479 .ioctl_wait_idle = NULL, 480 .gui_idle = &r100_gui_idle, 481 .mc_wait_for_idle = &r300_mc_wait_for_idle, 482 .gart = { 483 .tlb_flush = &rv370_pcie_gart_tlb_flush, 484 .set_page = &rv370_pcie_gart_set_page, 485 }, 486 .ring = { 487 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 488 }, 489 .irq = { 490 .set = &r100_irq_set, 491 .process = &r100_irq_process, 492 }, 493 .display = { 494 .bandwidth_update = &r100_bandwidth_update, 495 .get_vblank_counter = &r100_get_vblank_counter, 496 .wait_for_vblank = &r100_wait_for_vblank, 497 .set_backlight_level = &atombios_set_backlight_level, 498 .get_backlight_level = &atombios_get_backlight_level, 499 }, 500 .copy = { 501 .blit = &r100_copy_blit, 502 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 503 .dma = &r200_copy_dma, 504 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 505 .copy = &r100_copy_blit, 506 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 507 }, 508 .surface = { 509 .set_reg = r100_set_surface_reg, 510 .clear_reg = r100_clear_surface_reg, 511 }, 512 .hpd = { 513 .init = &r100_hpd_init, 514 .fini = &r100_hpd_fini, 515 .sense = &r100_hpd_sense, 516 .set_polarity = &r100_hpd_set_polarity, 517 }, 518 .pm = { 519 .misc = &r100_pm_misc, 520 .prepare = &r100_pm_prepare, 521 .finish = &r100_pm_finish, 522 .init_profile = &r420_pm_init_profile, 523 .get_dynpm_state = &r100_pm_get_dynpm_state, 524 .get_engine_clock = &radeon_atom_get_engine_clock, 525 .set_engine_clock = &radeon_atom_set_engine_clock, 526 .get_memory_clock = &radeon_atom_get_memory_clock, 527 .set_memory_clock = &radeon_atom_set_memory_clock, 528 .get_pcie_lanes = &rv370_get_pcie_lanes, 529 .set_pcie_lanes = &rv370_set_pcie_lanes, 530 .set_clock_gating = &radeon_atom_set_clock_gating, 531 }, 532 .pflip = { 533 .pre_page_flip = &r100_pre_page_flip, 534 .page_flip = &r100_page_flip, 535 .post_page_flip = &r100_post_page_flip, 536 }, 537 }; 538 539 static struct radeon_asic rs400_asic = { 540 .init = &rs400_init, 541 .fini = &rs400_fini, 542 .suspend = &rs400_suspend, 543 .resume = &rs400_resume, 544 .vga_set_state = &r100_vga_set_state, 545 .asic_reset = &r300_asic_reset, 546 .ioctl_wait_idle = NULL, 547 .gui_idle = &r100_gui_idle, 548 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 549 .gart = { 550 .tlb_flush = &rs400_gart_tlb_flush, 551 .set_page = &rs400_gart_set_page, 552 }, 553 .ring = { 554 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 555 }, 556 .irq = { 557 .set = &r100_irq_set, 558 .process = &r100_irq_process, 559 }, 560 .display = { 561 .bandwidth_update = &r100_bandwidth_update, 562 .get_vblank_counter = &r100_get_vblank_counter, 563 .wait_for_vblank = &r100_wait_for_vblank, 564 .set_backlight_level = &radeon_legacy_set_backlight_level, 565 .get_backlight_level = &radeon_legacy_get_backlight_level, 566 }, 567 .copy = { 568 .blit = &r100_copy_blit, 569 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 570 .dma = &r200_copy_dma, 571 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 572 .copy = &r100_copy_blit, 573 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 574 }, 575 .surface = { 576 .set_reg = r100_set_surface_reg, 577 .clear_reg = r100_clear_surface_reg, 578 }, 579 .hpd = { 580 .init = &r100_hpd_init, 581 .fini = &r100_hpd_fini, 582 .sense = &r100_hpd_sense, 583 .set_polarity = &r100_hpd_set_polarity, 584 }, 585 .pm = { 586 .misc = &r100_pm_misc, 587 .prepare = &r100_pm_prepare, 588 .finish = &r100_pm_finish, 589 .init_profile = &r100_pm_init_profile, 590 .get_dynpm_state = &r100_pm_get_dynpm_state, 591 .get_engine_clock = &radeon_legacy_get_engine_clock, 592 .set_engine_clock = &radeon_legacy_set_engine_clock, 593 .get_memory_clock = &radeon_legacy_get_memory_clock, 594 .set_memory_clock = NULL, 595 .get_pcie_lanes = NULL, 596 .set_pcie_lanes = NULL, 597 .set_clock_gating = &radeon_legacy_set_clock_gating, 598 }, 599 .pflip = { 600 .pre_page_flip = &r100_pre_page_flip, 601 .page_flip = &r100_page_flip, 602 .post_page_flip = &r100_post_page_flip, 603 }, 604 }; 605 606 static struct radeon_asic rs600_asic = { 607 .init = &rs600_init, 608 .fini = &rs600_fini, 609 .suspend = &rs600_suspend, 610 .resume = &rs600_resume, 611 .vga_set_state = &r100_vga_set_state, 612 .asic_reset = &rs600_asic_reset, 613 .ioctl_wait_idle = NULL, 614 .gui_idle = &r100_gui_idle, 615 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 616 .gart = { 617 .tlb_flush = &rs600_gart_tlb_flush, 618 .set_page = &rs600_gart_set_page, 619 }, 620 .ring = { 621 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 622 }, 623 .irq = { 624 .set = &rs600_irq_set, 625 .process = &rs600_irq_process, 626 }, 627 .display = { 628 .bandwidth_update = &rs600_bandwidth_update, 629 .get_vblank_counter = &rs600_get_vblank_counter, 630 .wait_for_vblank = &avivo_wait_for_vblank, 631 .set_backlight_level = &atombios_set_backlight_level, 632 .get_backlight_level = &atombios_get_backlight_level, 633 .hdmi_enable = &r600_hdmi_enable, 634 .hdmi_setmode = &r600_hdmi_setmode, 635 }, 636 .copy = { 637 .blit = &r100_copy_blit, 638 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 639 .dma = &r200_copy_dma, 640 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 641 .copy = &r100_copy_blit, 642 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 643 }, 644 .surface = { 645 .set_reg = r100_set_surface_reg, 646 .clear_reg = r100_clear_surface_reg, 647 }, 648 .hpd = { 649 .init = &rs600_hpd_init, 650 .fini = &rs600_hpd_fini, 651 .sense = &rs600_hpd_sense, 652 .set_polarity = &rs600_hpd_set_polarity, 653 }, 654 .pm = { 655 .misc = &rs600_pm_misc, 656 .prepare = &rs600_pm_prepare, 657 .finish = &rs600_pm_finish, 658 .init_profile = &r420_pm_init_profile, 659 .get_dynpm_state = &r100_pm_get_dynpm_state, 660 .get_engine_clock = &radeon_atom_get_engine_clock, 661 .set_engine_clock = &radeon_atom_set_engine_clock, 662 .get_memory_clock = &radeon_atom_get_memory_clock, 663 .set_memory_clock = &radeon_atom_set_memory_clock, 664 .get_pcie_lanes = NULL, 665 .set_pcie_lanes = NULL, 666 .set_clock_gating = &radeon_atom_set_clock_gating, 667 }, 668 .pflip = { 669 .pre_page_flip = &rs600_pre_page_flip, 670 .page_flip = &rs600_page_flip, 671 .post_page_flip = &rs600_post_page_flip, 672 }, 673 }; 674 675 static struct radeon_asic rs690_asic = { 676 .init = &rs690_init, 677 .fini = &rs690_fini, 678 .suspend = &rs690_suspend, 679 .resume = &rs690_resume, 680 .vga_set_state = &r100_vga_set_state, 681 .asic_reset = &rs600_asic_reset, 682 .ioctl_wait_idle = NULL, 683 .gui_idle = &r100_gui_idle, 684 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 685 .gart = { 686 .tlb_flush = &rs400_gart_tlb_flush, 687 .set_page = &rs400_gart_set_page, 688 }, 689 .ring = { 690 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 691 }, 692 .irq = { 693 .set = &rs600_irq_set, 694 .process = &rs600_irq_process, 695 }, 696 .display = { 697 .get_vblank_counter = &rs600_get_vblank_counter, 698 .bandwidth_update = &rs690_bandwidth_update, 699 .wait_for_vblank = &avivo_wait_for_vblank, 700 .set_backlight_level = &atombios_set_backlight_level, 701 .get_backlight_level = &atombios_get_backlight_level, 702 .hdmi_enable = &r600_hdmi_enable, 703 .hdmi_setmode = &r600_hdmi_setmode, 704 }, 705 .copy = { 706 .blit = &r100_copy_blit, 707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 708 .dma = &r200_copy_dma, 709 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 710 .copy = &r200_copy_dma, 711 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 712 }, 713 .surface = { 714 .set_reg = r100_set_surface_reg, 715 .clear_reg = r100_clear_surface_reg, 716 }, 717 .hpd = { 718 .init = &rs600_hpd_init, 719 .fini = &rs600_hpd_fini, 720 .sense = &rs600_hpd_sense, 721 .set_polarity = &rs600_hpd_set_polarity, 722 }, 723 .pm = { 724 .misc = &rs600_pm_misc, 725 .prepare = &rs600_pm_prepare, 726 .finish = &rs600_pm_finish, 727 .init_profile = &r420_pm_init_profile, 728 .get_dynpm_state = &r100_pm_get_dynpm_state, 729 .get_engine_clock = &radeon_atom_get_engine_clock, 730 .set_engine_clock = &radeon_atom_set_engine_clock, 731 .get_memory_clock = &radeon_atom_get_memory_clock, 732 .set_memory_clock = &radeon_atom_set_memory_clock, 733 .get_pcie_lanes = NULL, 734 .set_pcie_lanes = NULL, 735 .set_clock_gating = &radeon_atom_set_clock_gating, 736 }, 737 .pflip = { 738 .pre_page_flip = &rs600_pre_page_flip, 739 .page_flip = &rs600_page_flip, 740 .post_page_flip = &rs600_post_page_flip, 741 }, 742 }; 743 744 static struct radeon_asic rv515_asic = { 745 .init = &rv515_init, 746 .fini = &rv515_fini, 747 .suspend = &rv515_suspend, 748 .resume = &rv515_resume, 749 .vga_set_state = &r100_vga_set_state, 750 .asic_reset = &rs600_asic_reset, 751 .ioctl_wait_idle = NULL, 752 .gui_idle = &r100_gui_idle, 753 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 754 .gart = { 755 .tlb_flush = &rv370_pcie_gart_tlb_flush, 756 .set_page = &rv370_pcie_gart_set_page, 757 }, 758 .ring = { 759 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 760 }, 761 .irq = { 762 .set = &rs600_irq_set, 763 .process = &rs600_irq_process, 764 }, 765 .display = { 766 .get_vblank_counter = &rs600_get_vblank_counter, 767 .bandwidth_update = &rv515_bandwidth_update, 768 .wait_for_vblank = &avivo_wait_for_vblank, 769 .set_backlight_level = &atombios_set_backlight_level, 770 .get_backlight_level = &atombios_get_backlight_level, 771 }, 772 .copy = { 773 .blit = &r100_copy_blit, 774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 775 .dma = &r200_copy_dma, 776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 777 .copy = &r100_copy_blit, 778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 779 }, 780 .surface = { 781 .set_reg = r100_set_surface_reg, 782 .clear_reg = r100_clear_surface_reg, 783 }, 784 .hpd = { 785 .init = &rs600_hpd_init, 786 .fini = &rs600_hpd_fini, 787 .sense = &rs600_hpd_sense, 788 .set_polarity = &rs600_hpd_set_polarity, 789 }, 790 .pm = { 791 .misc = &rs600_pm_misc, 792 .prepare = &rs600_pm_prepare, 793 .finish = &rs600_pm_finish, 794 .init_profile = &r420_pm_init_profile, 795 .get_dynpm_state = &r100_pm_get_dynpm_state, 796 .get_engine_clock = &radeon_atom_get_engine_clock, 797 .set_engine_clock = &radeon_atom_set_engine_clock, 798 .get_memory_clock = &radeon_atom_get_memory_clock, 799 .set_memory_clock = &radeon_atom_set_memory_clock, 800 .get_pcie_lanes = &rv370_get_pcie_lanes, 801 .set_pcie_lanes = &rv370_set_pcie_lanes, 802 .set_clock_gating = &radeon_atom_set_clock_gating, 803 }, 804 .pflip = { 805 .pre_page_flip = &rs600_pre_page_flip, 806 .page_flip = &rs600_page_flip, 807 .post_page_flip = &rs600_post_page_flip, 808 }, 809 }; 810 811 static struct radeon_asic r520_asic = { 812 .init = &r520_init, 813 .fini = &rv515_fini, 814 .suspend = &rv515_suspend, 815 .resume = &r520_resume, 816 .vga_set_state = &r100_vga_set_state, 817 .asic_reset = &rs600_asic_reset, 818 .ioctl_wait_idle = NULL, 819 .gui_idle = &r100_gui_idle, 820 .mc_wait_for_idle = &r520_mc_wait_for_idle, 821 .gart = { 822 .tlb_flush = &rv370_pcie_gart_tlb_flush, 823 .set_page = &rv370_pcie_gart_set_page, 824 }, 825 .ring = { 826 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 827 }, 828 .irq = { 829 .set = &rs600_irq_set, 830 .process = &rs600_irq_process, 831 }, 832 .display = { 833 .bandwidth_update = &rv515_bandwidth_update, 834 .get_vblank_counter = &rs600_get_vblank_counter, 835 .wait_for_vblank = &avivo_wait_for_vblank, 836 .set_backlight_level = &atombios_set_backlight_level, 837 .get_backlight_level = &atombios_get_backlight_level, 838 }, 839 .copy = { 840 .blit = &r100_copy_blit, 841 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 842 .dma = &r200_copy_dma, 843 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 844 .copy = &r100_copy_blit, 845 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 846 }, 847 .surface = { 848 .set_reg = r100_set_surface_reg, 849 .clear_reg = r100_clear_surface_reg, 850 }, 851 .hpd = { 852 .init = &rs600_hpd_init, 853 .fini = &rs600_hpd_fini, 854 .sense = &rs600_hpd_sense, 855 .set_polarity = &rs600_hpd_set_polarity, 856 }, 857 .pm = { 858 .misc = &rs600_pm_misc, 859 .prepare = &rs600_pm_prepare, 860 .finish = &rs600_pm_finish, 861 .init_profile = &r420_pm_init_profile, 862 .get_dynpm_state = &r100_pm_get_dynpm_state, 863 .get_engine_clock = &radeon_atom_get_engine_clock, 864 .set_engine_clock = &radeon_atom_set_engine_clock, 865 .get_memory_clock = &radeon_atom_get_memory_clock, 866 .set_memory_clock = &radeon_atom_set_memory_clock, 867 .get_pcie_lanes = &rv370_get_pcie_lanes, 868 .set_pcie_lanes = &rv370_set_pcie_lanes, 869 .set_clock_gating = &radeon_atom_set_clock_gating, 870 }, 871 .pflip = { 872 .pre_page_flip = &rs600_pre_page_flip, 873 .page_flip = &rs600_page_flip, 874 .post_page_flip = &rs600_post_page_flip, 875 }, 876 }; 877 878 static struct radeon_asic_ring r600_gfx_ring = { 879 .ib_execute = &r600_ring_ib_execute, 880 .emit_fence = &r600_fence_ring_emit, 881 .emit_semaphore = &r600_semaphore_ring_emit, 882 .cs_parse = &r600_cs_parse, 883 .ring_test = &r600_ring_test, 884 .ib_test = &r600_ib_test, 885 .is_lockup = &r600_gfx_is_lockup, 886 .get_rptr = &r600_gfx_get_rptr, 887 .get_wptr = &r600_gfx_get_wptr, 888 .set_wptr = &r600_gfx_set_wptr, 889 }; 890 891 static struct radeon_asic_ring r600_dma_ring = { 892 .ib_execute = &r600_dma_ring_ib_execute, 893 .emit_fence = &r600_dma_fence_ring_emit, 894 .emit_semaphore = &r600_dma_semaphore_ring_emit, 895 .cs_parse = &r600_dma_cs_parse, 896 .ring_test = &r600_dma_ring_test, 897 .ib_test = &r600_dma_ib_test, 898 .is_lockup = &r600_dma_is_lockup, 899 .get_rptr = &r600_dma_get_rptr, 900 .get_wptr = &r600_dma_get_wptr, 901 .set_wptr = &r600_dma_set_wptr, 902 }; 903 904 static struct radeon_asic r600_asic = { 905 .init = &r600_init, 906 .fini = &r600_fini, 907 .suspend = &r600_suspend, 908 .resume = &r600_resume, 909 .vga_set_state = &r600_vga_set_state, 910 .asic_reset = &r600_asic_reset, 911 .ioctl_wait_idle = r600_ioctl_wait_idle, 912 .gui_idle = &r600_gui_idle, 913 .mc_wait_for_idle = &r600_mc_wait_for_idle, 914 .get_xclk = &r600_get_xclk, 915 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 916 .gart = { 917 .tlb_flush = &r600_pcie_gart_tlb_flush, 918 .set_page = &rs600_gart_set_page, 919 }, 920 .ring = { 921 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 922 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 923 }, 924 .irq = { 925 .set = &r600_irq_set, 926 .process = &r600_irq_process, 927 }, 928 .display = { 929 .bandwidth_update = &rv515_bandwidth_update, 930 .get_vblank_counter = &rs600_get_vblank_counter, 931 .wait_for_vblank = &avivo_wait_for_vblank, 932 .set_backlight_level = &atombios_set_backlight_level, 933 .get_backlight_level = &atombios_get_backlight_level, 934 .hdmi_enable = &r600_hdmi_enable, 935 .hdmi_setmode = &r600_hdmi_setmode, 936 }, 937 .copy = { 938 .blit = &r600_copy_cpdma, 939 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 940 .dma = &r600_copy_dma, 941 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 942 .copy = &r600_copy_cpdma, 943 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 944 }, 945 .surface = { 946 .set_reg = r600_set_surface_reg, 947 .clear_reg = r600_clear_surface_reg, 948 }, 949 .hpd = { 950 .init = &r600_hpd_init, 951 .fini = &r600_hpd_fini, 952 .sense = &r600_hpd_sense, 953 .set_polarity = &r600_hpd_set_polarity, 954 }, 955 .pm = { 956 .misc = &r600_pm_misc, 957 .prepare = &rs600_pm_prepare, 958 .finish = &rs600_pm_finish, 959 .init_profile = &r600_pm_init_profile, 960 .get_dynpm_state = &r600_pm_get_dynpm_state, 961 .get_engine_clock = &radeon_atom_get_engine_clock, 962 .set_engine_clock = &radeon_atom_set_engine_clock, 963 .get_memory_clock = &radeon_atom_get_memory_clock, 964 .set_memory_clock = &radeon_atom_set_memory_clock, 965 .get_pcie_lanes = &r600_get_pcie_lanes, 966 .set_pcie_lanes = &r600_set_pcie_lanes, 967 .set_clock_gating = NULL, 968 .get_temperature = &rv6xx_get_temp, 969 }, 970 .pflip = { 971 .pre_page_flip = &rs600_pre_page_flip, 972 .page_flip = &rs600_page_flip, 973 .post_page_flip = &rs600_post_page_flip, 974 }, 975 }; 976 977 static struct radeon_asic rv6xx_asic = { 978 .init = &r600_init, 979 .fini = &r600_fini, 980 .suspend = &r600_suspend, 981 .resume = &r600_resume, 982 .vga_set_state = &r600_vga_set_state, 983 .asic_reset = &r600_asic_reset, 984 .ioctl_wait_idle = r600_ioctl_wait_idle, 985 .gui_idle = &r600_gui_idle, 986 .mc_wait_for_idle = &r600_mc_wait_for_idle, 987 .get_xclk = &r600_get_xclk, 988 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 989 .gart = { 990 .tlb_flush = &r600_pcie_gart_tlb_flush, 991 .set_page = &rs600_gart_set_page, 992 }, 993 .ring = { 994 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 995 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 996 }, 997 .irq = { 998 .set = &r600_irq_set, 999 .process = &r600_irq_process, 1000 }, 1001 .display = { 1002 .bandwidth_update = &rv515_bandwidth_update, 1003 .get_vblank_counter = &rs600_get_vblank_counter, 1004 .wait_for_vblank = &avivo_wait_for_vblank, 1005 .set_backlight_level = &atombios_set_backlight_level, 1006 .get_backlight_level = &atombios_get_backlight_level, 1007 .hdmi_enable = &r600_hdmi_enable, 1008 .hdmi_setmode = &r600_hdmi_setmode, 1009 }, 1010 .copy = { 1011 .blit = &r600_copy_cpdma, 1012 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1013 .dma = &r600_copy_dma, 1014 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1015 .copy = &r600_copy_cpdma, 1016 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1017 }, 1018 .surface = { 1019 .set_reg = r600_set_surface_reg, 1020 .clear_reg = r600_clear_surface_reg, 1021 }, 1022 .hpd = { 1023 .init = &r600_hpd_init, 1024 .fini = &r600_hpd_fini, 1025 .sense = &r600_hpd_sense, 1026 .set_polarity = &r600_hpd_set_polarity, 1027 }, 1028 .pm = { 1029 .misc = &r600_pm_misc, 1030 .prepare = &rs600_pm_prepare, 1031 .finish = &rs600_pm_finish, 1032 .init_profile = &r600_pm_init_profile, 1033 .get_dynpm_state = &r600_pm_get_dynpm_state, 1034 .get_engine_clock = &radeon_atom_get_engine_clock, 1035 .set_engine_clock = &radeon_atom_set_engine_clock, 1036 .get_memory_clock = &radeon_atom_get_memory_clock, 1037 .set_memory_clock = &radeon_atom_set_memory_clock, 1038 .get_pcie_lanes = &r600_get_pcie_lanes, 1039 .set_pcie_lanes = &r600_set_pcie_lanes, 1040 .set_clock_gating = NULL, 1041 .get_temperature = &rv6xx_get_temp, 1042 .set_uvd_clocks = &r600_set_uvd_clocks, 1043 }, 1044 .dpm = { 1045 .init = &rv6xx_dpm_init, 1046 .setup_asic = &rv6xx_setup_asic, 1047 .enable = &rv6xx_dpm_enable, 1048 .late_enable = &r600_dpm_late_enable, 1049 .disable = &rv6xx_dpm_disable, 1050 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1051 .set_power_state = &rv6xx_dpm_set_power_state, 1052 .post_set_power_state = &r600_dpm_post_set_power_state, 1053 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1054 .fini = &rv6xx_dpm_fini, 1055 .get_sclk = &rv6xx_dpm_get_sclk, 1056 .get_mclk = &rv6xx_dpm_get_mclk, 1057 .print_power_state = &rv6xx_dpm_print_power_state, 1058 #ifdef CONFIG_DEBUGFS 1059 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1060 #endif 1061 .force_performance_level = &rv6xx_dpm_force_performance_level, 1062 }, 1063 .pflip = { 1064 .pre_page_flip = &rs600_pre_page_flip, 1065 .page_flip = &rs600_page_flip, 1066 .post_page_flip = &rs600_post_page_flip, 1067 }, 1068 }; 1069 1070 static struct radeon_asic rs780_asic = { 1071 .init = &r600_init, 1072 .fini = &r600_fini, 1073 .suspend = &r600_suspend, 1074 .resume = &r600_resume, 1075 .vga_set_state = &r600_vga_set_state, 1076 .asic_reset = &r600_asic_reset, 1077 .ioctl_wait_idle = r600_ioctl_wait_idle, 1078 .gui_idle = &r600_gui_idle, 1079 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1080 .get_xclk = &r600_get_xclk, 1081 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1082 .gart = { 1083 .tlb_flush = &r600_pcie_gart_tlb_flush, 1084 .set_page = &rs600_gart_set_page, 1085 }, 1086 .ring = { 1087 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1088 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1089 }, 1090 .irq = { 1091 .set = &r600_irq_set, 1092 .process = &r600_irq_process, 1093 }, 1094 .display = { 1095 .bandwidth_update = &rs690_bandwidth_update, 1096 .get_vblank_counter = &rs600_get_vblank_counter, 1097 .wait_for_vblank = &avivo_wait_for_vblank, 1098 .set_backlight_level = &atombios_set_backlight_level, 1099 .get_backlight_level = &atombios_get_backlight_level, 1100 .hdmi_enable = &r600_hdmi_enable, 1101 .hdmi_setmode = &r600_hdmi_setmode, 1102 }, 1103 .copy = { 1104 .blit = &r600_copy_cpdma, 1105 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1106 .dma = &r600_copy_dma, 1107 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1108 .copy = &r600_copy_cpdma, 1109 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1110 }, 1111 .surface = { 1112 .set_reg = r600_set_surface_reg, 1113 .clear_reg = r600_clear_surface_reg, 1114 }, 1115 .hpd = { 1116 .init = &r600_hpd_init, 1117 .fini = &r600_hpd_fini, 1118 .sense = &r600_hpd_sense, 1119 .set_polarity = &r600_hpd_set_polarity, 1120 }, 1121 .pm = { 1122 .misc = &r600_pm_misc, 1123 .prepare = &rs600_pm_prepare, 1124 .finish = &rs600_pm_finish, 1125 .init_profile = &rs780_pm_init_profile, 1126 .get_dynpm_state = &r600_pm_get_dynpm_state, 1127 .get_engine_clock = &radeon_atom_get_engine_clock, 1128 .set_engine_clock = &radeon_atom_set_engine_clock, 1129 .get_memory_clock = NULL, 1130 .set_memory_clock = NULL, 1131 .get_pcie_lanes = NULL, 1132 .set_pcie_lanes = NULL, 1133 .set_clock_gating = NULL, 1134 .get_temperature = &rv6xx_get_temp, 1135 .set_uvd_clocks = &r600_set_uvd_clocks, 1136 }, 1137 .dpm = { 1138 .init = &rs780_dpm_init, 1139 .setup_asic = &rs780_dpm_setup_asic, 1140 .enable = &rs780_dpm_enable, 1141 .late_enable = &r600_dpm_late_enable, 1142 .disable = &rs780_dpm_disable, 1143 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1144 .set_power_state = &rs780_dpm_set_power_state, 1145 .post_set_power_state = &r600_dpm_post_set_power_state, 1146 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1147 .fini = &rs780_dpm_fini, 1148 .get_sclk = &rs780_dpm_get_sclk, 1149 .get_mclk = &rs780_dpm_get_mclk, 1150 .print_power_state = &rs780_dpm_print_power_state, 1151 #ifdef CONFIG_DEBUGFS 1152 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1153 #endif 1154 .force_performance_level = &rs780_dpm_force_performance_level, 1155 }, 1156 .pflip = { 1157 .pre_page_flip = &rs600_pre_page_flip, 1158 .page_flip = &rs600_page_flip, 1159 .post_page_flip = &rs600_post_page_flip, 1160 }, 1161 }; 1162 1163 static struct radeon_asic_ring rv770_uvd_ring = { 1164 .ib_execute = &uvd_v1_0_ib_execute, 1165 .emit_fence = &uvd_v2_2_fence_emit, 1166 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1167 .cs_parse = &radeon_uvd_cs_parse, 1168 .ring_test = &uvd_v1_0_ring_test, 1169 .ib_test = &uvd_v1_0_ib_test, 1170 .is_lockup = &radeon_ring_test_lockup, 1171 .get_rptr = &uvd_v1_0_get_rptr, 1172 .get_wptr = &uvd_v1_0_get_wptr, 1173 .set_wptr = &uvd_v1_0_set_wptr, 1174 }; 1175 1176 static struct radeon_asic rv770_asic = { 1177 .init = &rv770_init, 1178 .fini = &rv770_fini, 1179 .suspend = &rv770_suspend, 1180 .resume = &rv770_resume, 1181 .asic_reset = &r600_asic_reset, 1182 .vga_set_state = &r600_vga_set_state, 1183 .ioctl_wait_idle = r600_ioctl_wait_idle, 1184 .gui_idle = &r600_gui_idle, 1185 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1186 .get_xclk = &rv770_get_xclk, 1187 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1188 .gart = { 1189 .tlb_flush = &r600_pcie_gart_tlb_flush, 1190 .set_page = &rs600_gart_set_page, 1191 }, 1192 .ring = { 1193 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1194 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1195 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1196 }, 1197 .irq = { 1198 .set = &r600_irq_set, 1199 .process = &r600_irq_process, 1200 }, 1201 .display = { 1202 .bandwidth_update = &rv515_bandwidth_update, 1203 .get_vblank_counter = &rs600_get_vblank_counter, 1204 .wait_for_vblank = &avivo_wait_for_vblank, 1205 .set_backlight_level = &atombios_set_backlight_level, 1206 .get_backlight_level = &atombios_get_backlight_level, 1207 .hdmi_enable = &r600_hdmi_enable, 1208 .hdmi_setmode = &r600_hdmi_setmode, 1209 }, 1210 .copy = { 1211 .blit = &r600_copy_cpdma, 1212 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1213 .dma = &rv770_copy_dma, 1214 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1215 .copy = &rv770_copy_dma, 1216 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1217 }, 1218 .surface = { 1219 .set_reg = r600_set_surface_reg, 1220 .clear_reg = r600_clear_surface_reg, 1221 }, 1222 .hpd = { 1223 .init = &r600_hpd_init, 1224 .fini = &r600_hpd_fini, 1225 .sense = &r600_hpd_sense, 1226 .set_polarity = &r600_hpd_set_polarity, 1227 }, 1228 .pm = { 1229 .misc = &rv770_pm_misc, 1230 .prepare = &rs600_pm_prepare, 1231 .finish = &rs600_pm_finish, 1232 .init_profile = &r600_pm_init_profile, 1233 .get_dynpm_state = &r600_pm_get_dynpm_state, 1234 .get_engine_clock = &radeon_atom_get_engine_clock, 1235 .set_engine_clock = &radeon_atom_set_engine_clock, 1236 .get_memory_clock = &radeon_atom_get_memory_clock, 1237 .set_memory_clock = &radeon_atom_set_memory_clock, 1238 .get_pcie_lanes = &r600_get_pcie_lanes, 1239 .set_pcie_lanes = &r600_set_pcie_lanes, 1240 .set_clock_gating = &radeon_atom_set_clock_gating, 1241 .set_uvd_clocks = &rv770_set_uvd_clocks, 1242 .get_temperature = &rv770_get_temp, 1243 }, 1244 .dpm = { 1245 .init = &rv770_dpm_init, 1246 .setup_asic = &rv770_dpm_setup_asic, 1247 .enable = &rv770_dpm_enable, 1248 .late_enable = &rv770_dpm_late_enable, 1249 .disable = &rv770_dpm_disable, 1250 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1251 .set_power_state = &rv770_dpm_set_power_state, 1252 .post_set_power_state = &r600_dpm_post_set_power_state, 1253 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1254 .fini = &rv770_dpm_fini, 1255 .get_sclk = &rv770_dpm_get_sclk, 1256 .get_mclk = &rv770_dpm_get_mclk, 1257 .print_power_state = &rv770_dpm_print_power_state, 1258 #ifdef CONFIG_DEBUGFS 1259 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1260 #endif 1261 .force_performance_level = &rv770_dpm_force_performance_level, 1262 .vblank_too_short = &rv770_dpm_vblank_too_short, 1263 }, 1264 .pflip = { 1265 .pre_page_flip = &rs600_pre_page_flip, 1266 .page_flip = &rv770_page_flip, 1267 .post_page_flip = &rs600_post_page_flip, 1268 }, 1269 }; 1270 1271 static struct radeon_asic_ring evergreen_gfx_ring = { 1272 .ib_execute = &evergreen_ring_ib_execute, 1273 .emit_fence = &r600_fence_ring_emit, 1274 .emit_semaphore = &r600_semaphore_ring_emit, 1275 .cs_parse = &evergreen_cs_parse, 1276 .ring_test = &r600_ring_test, 1277 .ib_test = &r600_ib_test, 1278 .is_lockup = &evergreen_gfx_is_lockup, 1279 .get_rptr = &r600_gfx_get_rptr, 1280 .get_wptr = &r600_gfx_get_wptr, 1281 .set_wptr = &r600_gfx_set_wptr, 1282 }; 1283 1284 static struct radeon_asic_ring evergreen_dma_ring = { 1285 .ib_execute = &evergreen_dma_ring_ib_execute, 1286 .emit_fence = &evergreen_dma_fence_ring_emit, 1287 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1288 .cs_parse = &evergreen_dma_cs_parse, 1289 .ring_test = &r600_dma_ring_test, 1290 .ib_test = &r600_dma_ib_test, 1291 .is_lockup = &evergreen_dma_is_lockup, 1292 .get_rptr = &r600_dma_get_rptr, 1293 .get_wptr = &r600_dma_get_wptr, 1294 .set_wptr = &r600_dma_set_wptr, 1295 }; 1296 1297 static struct radeon_asic evergreen_asic = { 1298 .init = &evergreen_init, 1299 .fini = &evergreen_fini, 1300 .suspend = &evergreen_suspend, 1301 .resume = &evergreen_resume, 1302 .asic_reset = &evergreen_asic_reset, 1303 .vga_set_state = &r600_vga_set_state, 1304 .ioctl_wait_idle = r600_ioctl_wait_idle, 1305 .gui_idle = &r600_gui_idle, 1306 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1307 .get_xclk = &rv770_get_xclk, 1308 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1309 .gart = { 1310 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1311 .set_page = &rs600_gart_set_page, 1312 }, 1313 .ring = { 1314 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1315 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1316 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1317 }, 1318 .irq = { 1319 .set = &evergreen_irq_set, 1320 .process = &evergreen_irq_process, 1321 }, 1322 .display = { 1323 .bandwidth_update = &evergreen_bandwidth_update, 1324 .get_vblank_counter = &evergreen_get_vblank_counter, 1325 .wait_for_vblank = &dce4_wait_for_vblank, 1326 .set_backlight_level = &atombios_set_backlight_level, 1327 .get_backlight_level = &atombios_get_backlight_level, 1328 .hdmi_enable = &evergreen_hdmi_enable, 1329 .hdmi_setmode = &evergreen_hdmi_setmode, 1330 }, 1331 .copy = { 1332 .blit = &r600_copy_cpdma, 1333 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1334 .dma = &evergreen_copy_dma, 1335 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1336 .copy = &evergreen_copy_dma, 1337 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1338 }, 1339 .surface = { 1340 .set_reg = r600_set_surface_reg, 1341 .clear_reg = r600_clear_surface_reg, 1342 }, 1343 .hpd = { 1344 .init = &evergreen_hpd_init, 1345 .fini = &evergreen_hpd_fini, 1346 .sense = &evergreen_hpd_sense, 1347 .set_polarity = &evergreen_hpd_set_polarity, 1348 }, 1349 .pm = { 1350 .misc = &evergreen_pm_misc, 1351 .prepare = &evergreen_pm_prepare, 1352 .finish = &evergreen_pm_finish, 1353 .init_profile = &r600_pm_init_profile, 1354 .get_dynpm_state = &r600_pm_get_dynpm_state, 1355 .get_engine_clock = &radeon_atom_get_engine_clock, 1356 .set_engine_clock = &radeon_atom_set_engine_clock, 1357 .get_memory_clock = &radeon_atom_get_memory_clock, 1358 .set_memory_clock = &radeon_atom_set_memory_clock, 1359 .get_pcie_lanes = &r600_get_pcie_lanes, 1360 .set_pcie_lanes = &r600_set_pcie_lanes, 1361 .set_clock_gating = NULL, 1362 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1363 .get_temperature = &evergreen_get_temp, 1364 }, 1365 .dpm = { 1366 .init = &cypress_dpm_init, 1367 .setup_asic = &cypress_dpm_setup_asic, 1368 .enable = &cypress_dpm_enable, 1369 .late_enable = &rv770_dpm_late_enable, 1370 .disable = &cypress_dpm_disable, 1371 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1372 .set_power_state = &cypress_dpm_set_power_state, 1373 .post_set_power_state = &r600_dpm_post_set_power_state, 1374 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1375 .fini = &cypress_dpm_fini, 1376 .get_sclk = &rv770_dpm_get_sclk, 1377 .get_mclk = &rv770_dpm_get_mclk, 1378 .print_power_state = &rv770_dpm_print_power_state, 1379 #ifdef CONFIG_DEBUGFS 1380 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1381 #endif 1382 .force_performance_level = &rv770_dpm_force_performance_level, 1383 .vblank_too_short = &cypress_dpm_vblank_too_short, 1384 }, 1385 .pflip = { 1386 .pre_page_flip = &evergreen_pre_page_flip, 1387 .page_flip = &evergreen_page_flip, 1388 .post_page_flip = &evergreen_post_page_flip, 1389 }, 1390 }; 1391 1392 static struct radeon_asic sumo_asic = { 1393 .init = &evergreen_init, 1394 .fini = &evergreen_fini, 1395 .suspend = &evergreen_suspend, 1396 .resume = &evergreen_resume, 1397 .asic_reset = &evergreen_asic_reset, 1398 .vga_set_state = &r600_vga_set_state, 1399 .ioctl_wait_idle = r600_ioctl_wait_idle, 1400 .gui_idle = &r600_gui_idle, 1401 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1402 .get_xclk = &r600_get_xclk, 1403 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1404 .gart = { 1405 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1406 .set_page = &rs600_gart_set_page, 1407 }, 1408 .ring = { 1409 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1410 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1411 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1412 }, 1413 .irq = { 1414 .set = &evergreen_irq_set, 1415 .process = &evergreen_irq_process, 1416 }, 1417 .display = { 1418 .bandwidth_update = &evergreen_bandwidth_update, 1419 .get_vblank_counter = &evergreen_get_vblank_counter, 1420 .wait_for_vblank = &dce4_wait_for_vblank, 1421 .set_backlight_level = &atombios_set_backlight_level, 1422 .get_backlight_level = &atombios_get_backlight_level, 1423 .hdmi_enable = &evergreen_hdmi_enable, 1424 .hdmi_setmode = &evergreen_hdmi_setmode, 1425 }, 1426 .copy = { 1427 .blit = &r600_copy_cpdma, 1428 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1429 .dma = &evergreen_copy_dma, 1430 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1431 .copy = &evergreen_copy_dma, 1432 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1433 }, 1434 .surface = { 1435 .set_reg = r600_set_surface_reg, 1436 .clear_reg = r600_clear_surface_reg, 1437 }, 1438 .hpd = { 1439 .init = &evergreen_hpd_init, 1440 .fini = &evergreen_hpd_fini, 1441 .sense = &evergreen_hpd_sense, 1442 .set_polarity = &evergreen_hpd_set_polarity, 1443 }, 1444 .pm = { 1445 .misc = &evergreen_pm_misc, 1446 .prepare = &evergreen_pm_prepare, 1447 .finish = &evergreen_pm_finish, 1448 .init_profile = &sumo_pm_init_profile, 1449 .get_dynpm_state = &r600_pm_get_dynpm_state, 1450 .get_engine_clock = &radeon_atom_get_engine_clock, 1451 .set_engine_clock = &radeon_atom_set_engine_clock, 1452 .get_memory_clock = NULL, 1453 .set_memory_clock = NULL, 1454 .get_pcie_lanes = NULL, 1455 .set_pcie_lanes = NULL, 1456 .set_clock_gating = NULL, 1457 .set_uvd_clocks = &sumo_set_uvd_clocks, 1458 .get_temperature = &sumo_get_temp, 1459 }, 1460 .dpm = { 1461 .init = &sumo_dpm_init, 1462 .setup_asic = &sumo_dpm_setup_asic, 1463 .enable = &sumo_dpm_enable, 1464 .late_enable = &sumo_dpm_late_enable, 1465 .disable = &sumo_dpm_disable, 1466 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1467 .set_power_state = &sumo_dpm_set_power_state, 1468 .post_set_power_state = &sumo_dpm_post_set_power_state, 1469 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1470 .fini = &sumo_dpm_fini, 1471 .get_sclk = &sumo_dpm_get_sclk, 1472 .get_mclk = &sumo_dpm_get_mclk, 1473 .print_power_state = &sumo_dpm_print_power_state, 1474 #ifdef CONFIG_DEBUGFS 1475 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1476 #endif 1477 .force_performance_level = &sumo_dpm_force_performance_level, 1478 }, 1479 .pflip = { 1480 .pre_page_flip = &evergreen_pre_page_flip, 1481 .page_flip = &evergreen_page_flip, 1482 .post_page_flip = &evergreen_post_page_flip, 1483 }, 1484 }; 1485 1486 static struct radeon_asic btc_asic = { 1487 .init = &evergreen_init, 1488 .fini = &evergreen_fini, 1489 .suspend = &evergreen_suspend, 1490 .resume = &evergreen_resume, 1491 .asic_reset = &evergreen_asic_reset, 1492 .vga_set_state = &r600_vga_set_state, 1493 .ioctl_wait_idle = r600_ioctl_wait_idle, 1494 .gui_idle = &r600_gui_idle, 1495 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1496 .get_xclk = &rv770_get_xclk, 1497 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1498 .gart = { 1499 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1500 .set_page = &rs600_gart_set_page, 1501 }, 1502 .ring = { 1503 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1504 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1505 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1506 }, 1507 .irq = { 1508 .set = &evergreen_irq_set, 1509 .process = &evergreen_irq_process, 1510 }, 1511 .display = { 1512 .bandwidth_update = &evergreen_bandwidth_update, 1513 .get_vblank_counter = &evergreen_get_vblank_counter, 1514 .wait_for_vblank = &dce4_wait_for_vblank, 1515 .set_backlight_level = &atombios_set_backlight_level, 1516 .get_backlight_level = &atombios_get_backlight_level, 1517 .hdmi_enable = &evergreen_hdmi_enable, 1518 .hdmi_setmode = &evergreen_hdmi_setmode, 1519 }, 1520 .copy = { 1521 .blit = &r600_copy_cpdma, 1522 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1523 .dma = &evergreen_copy_dma, 1524 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1525 .copy = &evergreen_copy_dma, 1526 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1527 }, 1528 .surface = { 1529 .set_reg = r600_set_surface_reg, 1530 .clear_reg = r600_clear_surface_reg, 1531 }, 1532 .hpd = { 1533 .init = &evergreen_hpd_init, 1534 .fini = &evergreen_hpd_fini, 1535 .sense = &evergreen_hpd_sense, 1536 .set_polarity = &evergreen_hpd_set_polarity, 1537 }, 1538 .pm = { 1539 .misc = &evergreen_pm_misc, 1540 .prepare = &evergreen_pm_prepare, 1541 .finish = &evergreen_pm_finish, 1542 .init_profile = &btc_pm_init_profile, 1543 .get_dynpm_state = &r600_pm_get_dynpm_state, 1544 .get_engine_clock = &radeon_atom_get_engine_clock, 1545 .set_engine_clock = &radeon_atom_set_engine_clock, 1546 .get_memory_clock = &radeon_atom_get_memory_clock, 1547 .set_memory_clock = &radeon_atom_set_memory_clock, 1548 .get_pcie_lanes = &r600_get_pcie_lanes, 1549 .set_pcie_lanes = &r600_set_pcie_lanes, 1550 .set_clock_gating = NULL, 1551 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1552 .get_temperature = &evergreen_get_temp, 1553 }, 1554 .dpm = { 1555 .init = &btc_dpm_init, 1556 .setup_asic = &btc_dpm_setup_asic, 1557 .enable = &btc_dpm_enable, 1558 .late_enable = &rv770_dpm_late_enable, 1559 .disable = &btc_dpm_disable, 1560 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1561 .set_power_state = &btc_dpm_set_power_state, 1562 .post_set_power_state = &btc_dpm_post_set_power_state, 1563 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1564 .fini = &btc_dpm_fini, 1565 .get_sclk = &btc_dpm_get_sclk, 1566 .get_mclk = &btc_dpm_get_mclk, 1567 .print_power_state = &rv770_dpm_print_power_state, 1568 #ifdef CONFIG_DEBUGFS 1569 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1570 #endif 1571 .force_performance_level = &rv770_dpm_force_performance_level, 1572 .vblank_too_short = &btc_dpm_vblank_too_short, 1573 }, 1574 .pflip = { 1575 .pre_page_flip = &evergreen_pre_page_flip, 1576 .page_flip = &evergreen_page_flip, 1577 .post_page_flip = &evergreen_post_page_flip, 1578 }, 1579 }; 1580 1581 static struct radeon_asic_ring cayman_gfx_ring = { 1582 .ib_execute = &cayman_ring_ib_execute, 1583 .ib_parse = &evergreen_ib_parse, 1584 .emit_fence = &cayman_fence_ring_emit, 1585 .emit_semaphore = &r600_semaphore_ring_emit, 1586 .cs_parse = &evergreen_cs_parse, 1587 .ring_test = &r600_ring_test, 1588 .ib_test = &r600_ib_test, 1589 .is_lockup = &cayman_gfx_is_lockup, 1590 .vm_flush = &cayman_vm_flush, 1591 .get_rptr = &cayman_gfx_get_rptr, 1592 .get_wptr = &cayman_gfx_get_wptr, 1593 .set_wptr = &cayman_gfx_set_wptr, 1594 }; 1595 1596 static struct radeon_asic_ring cayman_dma_ring = { 1597 .ib_execute = &cayman_dma_ring_ib_execute, 1598 .ib_parse = &evergreen_dma_ib_parse, 1599 .emit_fence = &evergreen_dma_fence_ring_emit, 1600 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1601 .cs_parse = &evergreen_dma_cs_parse, 1602 .ring_test = &r600_dma_ring_test, 1603 .ib_test = &r600_dma_ib_test, 1604 .is_lockup = &cayman_dma_is_lockup, 1605 .vm_flush = &cayman_dma_vm_flush, 1606 .get_rptr = &cayman_dma_get_rptr, 1607 .get_wptr = &cayman_dma_get_wptr, 1608 .set_wptr = &cayman_dma_set_wptr 1609 }; 1610 1611 static struct radeon_asic_ring cayman_uvd_ring = { 1612 .ib_execute = &uvd_v1_0_ib_execute, 1613 .emit_fence = &uvd_v2_2_fence_emit, 1614 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1615 .cs_parse = &radeon_uvd_cs_parse, 1616 .ring_test = &uvd_v1_0_ring_test, 1617 .ib_test = &uvd_v1_0_ib_test, 1618 .is_lockup = &radeon_ring_test_lockup, 1619 .get_rptr = &uvd_v1_0_get_rptr, 1620 .get_wptr = &uvd_v1_0_get_wptr, 1621 .set_wptr = &uvd_v1_0_set_wptr, 1622 }; 1623 1624 static struct radeon_asic cayman_asic = { 1625 .init = &cayman_init, 1626 .fini = &cayman_fini, 1627 .suspend = &cayman_suspend, 1628 .resume = &cayman_resume, 1629 .asic_reset = &cayman_asic_reset, 1630 .vga_set_state = &r600_vga_set_state, 1631 .ioctl_wait_idle = r600_ioctl_wait_idle, 1632 .gui_idle = &r600_gui_idle, 1633 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1634 .get_xclk = &rv770_get_xclk, 1635 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1636 .gart = { 1637 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1638 .set_page = &rs600_gart_set_page, 1639 }, 1640 .vm = { 1641 .init = &cayman_vm_init, 1642 .fini = &cayman_vm_fini, 1643 .set_page = &cayman_dma_vm_set_page, 1644 }, 1645 .ring = { 1646 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1647 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1648 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1649 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1650 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1651 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1652 }, 1653 .irq = { 1654 .set = &evergreen_irq_set, 1655 .process = &evergreen_irq_process, 1656 }, 1657 .display = { 1658 .bandwidth_update = &evergreen_bandwidth_update, 1659 .get_vblank_counter = &evergreen_get_vblank_counter, 1660 .wait_for_vblank = &dce4_wait_for_vblank, 1661 .set_backlight_level = &atombios_set_backlight_level, 1662 .get_backlight_level = &atombios_get_backlight_level, 1663 .hdmi_enable = &evergreen_hdmi_enable, 1664 .hdmi_setmode = &evergreen_hdmi_setmode, 1665 }, 1666 .copy = { 1667 .blit = &r600_copy_cpdma, 1668 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1669 .dma = &evergreen_copy_dma, 1670 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1671 .copy = &evergreen_copy_dma, 1672 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1673 }, 1674 .surface = { 1675 .set_reg = r600_set_surface_reg, 1676 .clear_reg = r600_clear_surface_reg, 1677 }, 1678 .hpd = { 1679 .init = &evergreen_hpd_init, 1680 .fini = &evergreen_hpd_fini, 1681 .sense = &evergreen_hpd_sense, 1682 .set_polarity = &evergreen_hpd_set_polarity, 1683 }, 1684 .pm = { 1685 .misc = &evergreen_pm_misc, 1686 .prepare = &evergreen_pm_prepare, 1687 .finish = &evergreen_pm_finish, 1688 .init_profile = &btc_pm_init_profile, 1689 .get_dynpm_state = &r600_pm_get_dynpm_state, 1690 .get_engine_clock = &radeon_atom_get_engine_clock, 1691 .set_engine_clock = &radeon_atom_set_engine_clock, 1692 .get_memory_clock = &radeon_atom_get_memory_clock, 1693 .set_memory_clock = &radeon_atom_set_memory_clock, 1694 .get_pcie_lanes = &r600_get_pcie_lanes, 1695 .set_pcie_lanes = &r600_set_pcie_lanes, 1696 .set_clock_gating = NULL, 1697 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1698 .get_temperature = &evergreen_get_temp, 1699 }, 1700 .dpm = { 1701 .init = &ni_dpm_init, 1702 .setup_asic = &ni_dpm_setup_asic, 1703 .enable = &ni_dpm_enable, 1704 .late_enable = &rv770_dpm_late_enable, 1705 .disable = &ni_dpm_disable, 1706 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1707 .set_power_state = &ni_dpm_set_power_state, 1708 .post_set_power_state = &ni_dpm_post_set_power_state, 1709 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1710 .fini = &ni_dpm_fini, 1711 .get_sclk = &ni_dpm_get_sclk, 1712 .get_mclk = &ni_dpm_get_mclk, 1713 .print_power_state = &ni_dpm_print_power_state, 1714 #ifdef CONFIG_DEBUGFS 1715 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1716 #endif 1717 .force_performance_level = &ni_dpm_force_performance_level, 1718 .vblank_too_short = &ni_dpm_vblank_too_short, 1719 }, 1720 .pflip = { 1721 .pre_page_flip = &evergreen_pre_page_flip, 1722 .page_flip = &evergreen_page_flip, 1723 .post_page_flip = &evergreen_post_page_flip, 1724 }, 1725 }; 1726 1727 static struct radeon_asic trinity_asic = { 1728 .init = &cayman_init, 1729 .fini = &cayman_fini, 1730 .suspend = &cayman_suspend, 1731 .resume = &cayman_resume, 1732 .asic_reset = &cayman_asic_reset, 1733 .vga_set_state = &r600_vga_set_state, 1734 .ioctl_wait_idle = r600_ioctl_wait_idle, 1735 .gui_idle = &r600_gui_idle, 1736 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1737 .get_xclk = &r600_get_xclk, 1738 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1739 .gart = { 1740 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1741 .set_page = &rs600_gart_set_page, 1742 }, 1743 .vm = { 1744 .init = &cayman_vm_init, 1745 .fini = &cayman_vm_fini, 1746 .set_page = &cayman_dma_vm_set_page, 1747 }, 1748 .ring = { 1749 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1750 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1751 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1752 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1753 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1754 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1755 }, 1756 .irq = { 1757 .set = &evergreen_irq_set, 1758 .process = &evergreen_irq_process, 1759 }, 1760 .display = { 1761 .bandwidth_update = &dce6_bandwidth_update, 1762 .get_vblank_counter = &evergreen_get_vblank_counter, 1763 .wait_for_vblank = &dce4_wait_for_vblank, 1764 .set_backlight_level = &atombios_set_backlight_level, 1765 .get_backlight_level = &atombios_get_backlight_level, 1766 .hdmi_enable = &evergreen_hdmi_enable, 1767 .hdmi_setmode = &evergreen_hdmi_setmode, 1768 }, 1769 .copy = { 1770 .blit = &r600_copy_cpdma, 1771 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1772 .dma = &evergreen_copy_dma, 1773 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1774 .copy = &evergreen_copy_dma, 1775 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1776 }, 1777 .surface = { 1778 .set_reg = r600_set_surface_reg, 1779 .clear_reg = r600_clear_surface_reg, 1780 }, 1781 .hpd = { 1782 .init = &evergreen_hpd_init, 1783 .fini = &evergreen_hpd_fini, 1784 .sense = &evergreen_hpd_sense, 1785 .set_polarity = &evergreen_hpd_set_polarity, 1786 }, 1787 .pm = { 1788 .misc = &evergreen_pm_misc, 1789 .prepare = &evergreen_pm_prepare, 1790 .finish = &evergreen_pm_finish, 1791 .init_profile = &sumo_pm_init_profile, 1792 .get_dynpm_state = &r600_pm_get_dynpm_state, 1793 .get_engine_clock = &radeon_atom_get_engine_clock, 1794 .set_engine_clock = &radeon_atom_set_engine_clock, 1795 .get_memory_clock = NULL, 1796 .set_memory_clock = NULL, 1797 .get_pcie_lanes = NULL, 1798 .set_pcie_lanes = NULL, 1799 .set_clock_gating = NULL, 1800 .set_uvd_clocks = &sumo_set_uvd_clocks, 1801 .get_temperature = &tn_get_temp, 1802 }, 1803 .dpm = { 1804 .init = &trinity_dpm_init, 1805 .setup_asic = &trinity_dpm_setup_asic, 1806 .enable = &trinity_dpm_enable, 1807 .late_enable = &trinity_dpm_late_enable, 1808 .disable = &trinity_dpm_disable, 1809 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1810 .set_power_state = &trinity_dpm_set_power_state, 1811 .post_set_power_state = &trinity_dpm_post_set_power_state, 1812 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1813 .fini = &trinity_dpm_fini, 1814 .get_sclk = &trinity_dpm_get_sclk, 1815 .get_mclk = &trinity_dpm_get_mclk, 1816 .print_power_state = &trinity_dpm_print_power_state, 1817 #ifdef CONFIG_DEBUGFS 1818 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1819 #endif 1820 .force_performance_level = &trinity_dpm_force_performance_level, 1821 .enable_bapm = &trinity_dpm_enable_bapm, 1822 }, 1823 .pflip = { 1824 .pre_page_flip = &evergreen_pre_page_flip, 1825 .page_flip = &evergreen_page_flip, 1826 .post_page_flip = &evergreen_post_page_flip, 1827 }, 1828 }; 1829 1830 static struct radeon_asic_ring si_gfx_ring = { 1831 .ib_execute = &si_ring_ib_execute, 1832 .ib_parse = &si_ib_parse, 1833 .emit_fence = &si_fence_ring_emit, 1834 .emit_semaphore = &r600_semaphore_ring_emit, 1835 .cs_parse = NULL, 1836 .ring_test = &r600_ring_test, 1837 .ib_test = &r600_ib_test, 1838 .is_lockup = &si_gfx_is_lockup, 1839 .vm_flush = &si_vm_flush, 1840 .get_rptr = &cayman_gfx_get_rptr, 1841 .get_wptr = &cayman_gfx_get_wptr, 1842 .set_wptr = &cayman_gfx_set_wptr, 1843 }; 1844 1845 static struct radeon_asic_ring si_dma_ring = { 1846 .ib_execute = &cayman_dma_ring_ib_execute, 1847 .ib_parse = &evergreen_dma_ib_parse, 1848 .emit_fence = &evergreen_dma_fence_ring_emit, 1849 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1850 .cs_parse = NULL, 1851 .ring_test = &r600_dma_ring_test, 1852 .ib_test = &r600_dma_ib_test, 1853 .is_lockup = &si_dma_is_lockup, 1854 .vm_flush = &si_dma_vm_flush, 1855 .get_rptr = &cayman_dma_get_rptr, 1856 .get_wptr = &cayman_dma_get_wptr, 1857 .set_wptr = &cayman_dma_set_wptr, 1858 }; 1859 1860 static struct radeon_asic si_asic = { 1861 .init = &si_init, 1862 .fini = &si_fini, 1863 .suspend = &si_suspend, 1864 .resume = &si_resume, 1865 .asic_reset = &si_asic_reset, 1866 .vga_set_state = &r600_vga_set_state, 1867 .ioctl_wait_idle = r600_ioctl_wait_idle, 1868 .gui_idle = &r600_gui_idle, 1869 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1870 .get_xclk = &si_get_xclk, 1871 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1872 .gart = { 1873 .tlb_flush = &si_pcie_gart_tlb_flush, 1874 .set_page = &rs600_gart_set_page, 1875 }, 1876 .vm = { 1877 .init = &si_vm_init, 1878 .fini = &si_vm_fini, 1879 .set_page = &si_dma_vm_set_page, 1880 }, 1881 .ring = { 1882 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1883 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1884 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1885 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1886 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1887 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1888 }, 1889 .irq = { 1890 .set = &si_irq_set, 1891 .process = &si_irq_process, 1892 }, 1893 .display = { 1894 .bandwidth_update = &dce6_bandwidth_update, 1895 .get_vblank_counter = &evergreen_get_vblank_counter, 1896 .wait_for_vblank = &dce4_wait_for_vblank, 1897 .set_backlight_level = &atombios_set_backlight_level, 1898 .get_backlight_level = &atombios_get_backlight_level, 1899 .hdmi_enable = &evergreen_hdmi_enable, 1900 .hdmi_setmode = &evergreen_hdmi_setmode, 1901 }, 1902 .copy = { 1903 .blit = &r600_copy_cpdma, 1904 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1905 .dma = &si_copy_dma, 1906 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1907 .copy = &si_copy_dma, 1908 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1909 }, 1910 .surface = { 1911 .set_reg = r600_set_surface_reg, 1912 .clear_reg = r600_clear_surface_reg, 1913 }, 1914 .hpd = { 1915 .init = &evergreen_hpd_init, 1916 .fini = &evergreen_hpd_fini, 1917 .sense = &evergreen_hpd_sense, 1918 .set_polarity = &evergreen_hpd_set_polarity, 1919 }, 1920 .pm = { 1921 .misc = &evergreen_pm_misc, 1922 .prepare = &evergreen_pm_prepare, 1923 .finish = &evergreen_pm_finish, 1924 .init_profile = &sumo_pm_init_profile, 1925 .get_dynpm_state = &r600_pm_get_dynpm_state, 1926 .get_engine_clock = &radeon_atom_get_engine_clock, 1927 .set_engine_clock = &radeon_atom_set_engine_clock, 1928 .get_memory_clock = &radeon_atom_get_memory_clock, 1929 .set_memory_clock = &radeon_atom_set_memory_clock, 1930 .get_pcie_lanes = &r600_get_pcie_lanes, 1931 .set_pcie_lanes = &r600_set_pcie_lanes, 1932 .set_clock_gating = NULL, 1933 .set_uvd_clocks = &si_set_uvd_clocks, 1934 .get_temperature = &si_get_temp, 1935 }, 1936 .dpm = { 1937 .init = &si_dpm_init, 1938 .setup_asic = &si_dpm_setup_asic, 1939 .enable = &si_dpm_enable, 1940 .late_enable = &si_dpm_late_enable, 1941 .disable = &si_dpm_disable, 1942 .pre_set_power_state = &si_dpm_pre_set_power_state, 1943 .set_power_state = &si_dpm_set_power_state, 1944 .post_set_power_state = &si_dpm_post_set_power_state, 1945 .display_configuration_changed = &si_dpm_display_configuration_changed, 1946 .fini = &si_dpm_fini, 1947 .get_sclk = &ni_dpm_get_sclk, 1948 .get_mclk = &ni_dpm_get_mclk, 1949 .print_power_state = &ni_dpm_print_power_state, 1950 #ifdef CONFIG_DEBUGFS 1951 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1952 #endif 1953 .force_performance_level = &si_dpm_force_performance_level, 1954 .vblank_too_short = &ni_dpm_vblank_too_short, 1955 }, 1956 .pflip = { 1957 .pre_page_flip = &evergreen_pre_page_flip, 1958 .page_flip = &evergreen_page_flip, 1959 .post_page_flip = &evergreen_post_page_flip, 1960 }, 1961 }; 1962 1963 static struct radeon_asic_ring ci_gfx_ring = { 1964 .ib_execute = &cik_ring_ib_execute, 1965 .ib_parse = &cik_ib_parse, 1966 .emit_fence = &cik_fence_gfx_ring_emit, 1967 .emit_semaphore = &cik_semaphore_ring_emit, 1968 .cs_parse = NULL, 1969 .ring_test = &cik_ring_test, 1970 .ib_test = &cik_ib_test, 1971 .is_lockup = &cik_gfx_is_lockup, 1972 .vm_flush = &cik_vm_flush, 1973 .get_rptr = &cik_gfx_get_rptr, 1974 .get_wptr = &cik_gfx_get_wptr, 1975 .set_wptr = &cik_gfx_set_wptr, 1976 }; 1977 1978 static struct radeon_asic_ring ci_cp_ring = { 1979 .ib_execute = &cik_ring_ib_execute, 1980 .ib_parse = &cik_ib_parse, 1981 .emit_fence = &cik_fence_compute_ring_emit, 1982 .emit_semaphore = &cik_semaphore_ring_emit, 1983 .cs_parse = NULL, 1984 .ring_test = &cik_ring_test, 1985 .ib_test = &cik_ib_test, 1986 .is_lockup = &cik_gfx_is_lockup, 1987 .vm_flush = &cik_vm_flush, 1988 .get_rptr = &cik_compute_get_rptr, 1989 .get_wptr = &cik_compute_get_wptr, 1990 .set_wptr = &cik_compute_set_wptr, 1991 }; 1992 1993 static struct radeon_asic_ring ci_dma_ring = { 1994 .ib_execute = &cik_sdma_ring_ib_execute, 1995 .ib_parse = &cik_ib_parse, 1996 .emit_fence = &cik_sdma_fence_ring_emit, 1997 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 1998 .cs_parse = NULL, 1999 .ring_test = &cik_sdma_ring_test, 2000 .ib_test = &cik_sdma_ib_test, 2001 .is_lockup = &cik_sdma_is_lockup, 2002 .vm_flush = &cik_dma_vm_flush, 2003 .get_rptr = &cik_sdma_get_rptr, 2004 .get_wptr = &cik_sdma_get_wptr, 2005 .set_wptr = &cik_sdma_set_wptr, 2006 }; 2007 2008 static struct radeon_asic_ring ci_vce_ring = { 2009 .ib_execute = &radeon_vce_ib_execute, 2010 .emit_fence = &radeon_vce_fence_emit, 2011 .emit_semaphore = &radeon_vce_semaphore_emit, 2012 .cs_parse = &radeon_vce_cs_parse, 2013 .ring_test = &radeon_vce_ring_test, 2014 .ib_test = &radeon_vce_ib_test, 2015 .is_lockup = &radeon_ring_test_lockup, 2016 .get_rptr = &vce_v1_0_get_rptr, 2017 .get_wptr = &vce_v1_0_get_wptr, 2018 .set_wptr = &vce_v1_0_set_wptr, 2019 }; 2020 2021 static struct radeon_asic ci_asic = { 2022 .init = &cik_init, 2023 .fini = &cik_fini, 2024 .suspend = &cik_suspend, 2025 .resume = &cik_resume, 2026 .asic_reset = &cik_asic_reset, 2027 .vga_set_state = &r600_vga_set_state, 2028 .ioctl_wait_idle = NULL, 2029 .gui_idle = &r600_gui_idle, 2030 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2031 .get_xclk = &cik_get_xclk, 2032 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2033 .gart = { 2034 .tlb_flush = &cik_pcie_gart_tlb_flush, 2035 .set_page = &rs600_gart_set_page, 2036 }, 2037 .vm = { 2038 .init = &cik_vm_init, 2039 .fini = &cik_vm_fini, 2040 .set_page = &cik_sdma_vm_set_page, 2041 }, 2042 .ring = { 2043 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2044 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2045 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2046 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2047 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2048 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2049 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2050 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2051 }, 2052 .irq = { 2053 .set = &cik_irq_set, 2054 .process = &cik_irq_process, 2055 }, 2056 .display = { 2057 .bandwidth_update = &dce8_bandwidth_update, 2058 .get_vblank_counter = &evergreen_get_vblank_counter, 2059 .wait_for_vblank = &dce4_wait_for_vblank, 2060 .set_backlight_level = &atombios_set_backlight_level, 2061 .get_backlight_level = &atombios_get_backlight_level, 2062 .hdmi_enable = &evergreen_hdmi_enable, 2063 .hdmi_setmode = &evergreen_hdmi_setmode, 2064 }, 2065 .copy = { 2066 .blit = &cik_copy_cpdma, 2067 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2068 .dma = &cik_copy_dma, 2069 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2070 .copy = &cik_copy_cpdma, 2071 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2072 }, 2073 .surface = { 2074 .set_reg = r600_set_surface_reg, 2075 .clear_reg = r600_clear_surface_reg, 2076 }, 2077 .hpd = { 2078 .init = &evergreen_hpd_init, 2079 .fini = &evergreen_hpd_fini, 2080 .sense = &evergreen_hpd_sense, 2081 .set_polarity = &evergreen_hpd_set_polarity, 2082 }, 2083 .pm = { 2084 .misc = &evergreen_pm_misc, 2085 .prepare = &evergreen_pm_prepare, 2086 .finish = &evergreen_pm_finish, 2087 .init_profile = &sumo_pm_init_profile, 2088 .get_dynpm_state = &r600_pm_get_dynpm_state, 2089 .get_engine_clock = &radeon_atom_get_engine_clock, 2090 .set_engine_clock = &radeon_atom_set_engine_clock, 2091 .get_memory_clock = &radeon_atom_get_memory_clock, 2092 .set_memory_clock = &radeon_atom_set_memory_clock, 2093 .get_pcie_lanes = NULL, 2094 .set_pcie_lanes = NULL, 2095 .set_clock_gating = NULL, 2096 .set_uvd_clocks = &cik_set_uvd_clocks, 2097 .set_vce_clocks = &cik_set_vce_clocks, 2098 .get_temperature = &ci_get_temp, 2099 }, 2100 .dpm = { 2101 .init = &ci_dpm_init, 2102 .setup_asic = &ci_dpm_setup_asic, 2103 .enable = &ci_dpm_enable, 2104 .late_enable = &ci_dpm_late_enable, 2105 .disable = &ci_dpm_disable, 2106 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2107 .set_power_state = &ci_dpm_set_power_state, 2108 .post_set_power_state = &ci_dpm_post_set_power_state, 2109 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2110 .fini = &ci_dpm_fini, 2111 .get_sclk = &ci_dpm_get_sclk, 2112 .get_mclk = &ci_dpm_get_mclk, 2113 .print_power_state = &ci_dpm_print_power_state, 2114 #ifdef CONFIG_DEBUGFS 2115 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2116 #endif 2117 .force_performance_level = &ci_dpm_force_performance_level, 2118 .vblank_too_short = &ci_dpm_vblank_too_short, 2119 .powergate_uvd = &ci_dpm_powergate_uvd, 2120 }, 2121 .pflip = { 2122 .pre_page_flip = &evergreen_pre_page_flip, 2123 .page_flip = &evergreen_page_flip, 2124 .post_page_flip = &evergreen_post_page_flip, 2125 }, 2126 }; 2127 2128 static struct radeon_asic kv_asic = { 2129 .init = &cik_init, 2130 .fini = &cik_fini, 2131 .suspend = &cik_suspend, 2132 .resume = &cik_resume, 2133 .asic_reset = &cik_asic_reset, 2134 .vga_set_state = &r600_vga_set_state, 2135 .ioctl_wait_idle = NULL, 2136 .gui_idle = &r600_gui_idle, 2137 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2138 .get_xclk = &cik_get_xclk, 2139 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2140 .gart = { 2141 .tlb_flush = &cik_pcie_gart_tlb_flush, 2142 .set_page = &rs600_gart_set_page, 2143 }, 2144 .vm = { 2145 .init = &cik_vm_init, 2146 .fini = &cik_vm_fini, 2147 .set_page = &cik_sdma_vm_set_page, 2148 }, 2149 .ring = { 2150 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2151 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2152 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2153 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2154 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2155 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2156 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2157 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2158 }, 2159 .irq = { 2160 .set = &cik_irq_set, 2161 .process = &cik_irq_process, 2162 }, 2163 .display = { 2164 .bandwidth_update = &dce8_bandwidth_update, 2165 .get_vblank_counter = &evergreen_get_vblank_counter, 2166 .wait_for_vblank = &dce4_wait_for_vblank, 2167 .set_backlight_level = &atombios_set_backlight_level, 2168 .get_backlight_level = &atombios_get_backlight_level, 2169 .hdmi_enable = &evergreen_hdmi_enable, 2170 .hdmi_setmode = &evergreen_hdmi_setmode, 2171 }, 2172 .copy = { 2173 .blit = &cik_copy_cpdma, 2174 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2175 .dma = &cik_copy_dma, 2176 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2177 .copy = &cik_copy_dma, 2178 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2179 }, 2180 .surface = { 2181 .set_reg = r600_set_surface_reg, 2182 .clear_reg = r600_clear_surface_reg, 2183 }, 2184 .hpd = { 2185 .init = &evergreen_hpd_init, 2186 .fini = &evergreen_hpd_fini, 2187 .sense = &evergreen_hpd_sense, 2188 .set_polarity = &evergreen_hpd_set_polarity, 2189 }, 2190 .pm = { 2191 .misc = &evergreen_pm_misc, 2192 .prepare = &evergreen_pm_prepare, 2193 .finish = &evergreen_pm_finish, 2194 .init_profile = &sumo_pm_init_profile, 2195 .get_dynpm_state = &r600_pm_get_dynpm_state, 2196 .get_engine_clock = &radeon_atom_get_engine_clock, 2197 .set_engine_clock = &radeon_atom_set_engine_clock, 2198 .get_memory_clock = &radeon_atom_get_memory_clock, 2199 .set_memory_clock = &radeon_atom_set_memory_clock, 2200 .get_pcie_lanes = NULL, 2201 .set_pcie_lanes = NULL, 2202 .set_clock_gating = NULL, 2203 .set_uvd_clocks = &cik_set_uvd_clocks, 2204 .set_vce_clocks = &cik_set_vce_clocks, 2205 .get_temperature = &kv_get_temp, 2206 }, 2207 .dpm = { 2208 .init = &kv_dpm_init, 2209 .setup_asic = &kv_dpm_setup_asic, 2210 .enable = &kv_dpm_enable, 2211 .late_enable = &kv_dpm_late_enable, 2212 .disable = &kv_dpm_disable, 2213 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2214 .set_power_state = &kv_dpm_set_power_state, 2215 .post_set_power_state = &kv_dpm_post_set_power_state, 2216 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2217 .fini = &kv_dpm_fini, 2218 .get_sclk = &kv_dpm_get_sclk, 2219 .get_mclk = &kv_dpm_get_mclk, 2220 .print_power_state = &kv_dpm_print_power_state, 2221 #ifdef CONFIG_DEBUGFS 2222 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2223 #endif 2224 .force_performance_level = &kv_dpm_force_performance_level, 2225 .powergate_uvd = &kv_dpm_powergate_uvd, 2226 .enable_bapm = &kv_dpm_enable_bapm, 2227 }, 2228 .pflip = { 2229 .pre_page_flip = &evergreen_pre_page_flip, 2230 .page_flip = &evergreen_page_flip, 2231 .post_page_flip = &evergreen_post_page_flip, 2232 }, 2233 }; 2234 2235 /** 2236 * radeon_asic_init - register asic specific callbacks 2237 * 2238 * @rdev: radeon device pointer 2239 * 2240 * Registers the appropriate asic specific callbacks for each 2241 * chip family. Also sets other asics specific info like the number 2242 * of crtcs and the register aperture accessors (all asics). 2243 * Returns 0 for success. 2244 */ 2245 int radeon_asic_init(struct radeon_device *rdev) 2246 { 2247 radeon_register_accessor_init(rdev); 2248 2249 /* set the number of crtcs */ 2250 if (rdev->flags & RADEON_SINGLE_CRTC) 2251 rdev->num_crtc = 1; 2252 else 2253 rdev->num_crtc = 2; 2254 2255 rdev->has_uvd = false; 2256 2257 switch (rdev->family) { 2258 case CHIP_R100: 2259 case CHIP_RV100: 2260 case CHIP_RS100: 2261 case CHIP_RV200: 2262 case CHIP_RS200: 2263 rdev->asic = &r100_asic; 2264 break; 2265 case CHIP_R200: 2266 case CHIP_RV250: 2267 case CHIP_RS300: 2268 case CHIP_RV280: 2269 rdev->asic = &r200_asic; 2270 break; 2271 case CHIP_R300: 2272 case CHIP_R350: 2273 case CHIP_RV350: 2274 case CHIP_RV380: 2275 if (rdev->flags & RADEON_IS_PCIE) 2276 rdev->asic = &r300_asic_pcie; 2277 else 2278 rdev->asic = &r300_asic; 2279 break; 2280 case CHIP_R420: 2281 case CHIP_R423: 2282 case CHIP_RV410: 2283 rdev->asic = &r420_asic; 2284 /* handle macs */ 2285 if (rdev->bios == NULL) { 2286 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2287 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2288 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2289 rdev->asic->pm.set_memory_clock = NULL; 2290 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2291 } 2292 break; 2293 case CHIP_RS400: 2294 case CHIP_RS480: 2295 rdev->asic = &rs400_asic; 2296 break; 2297 case CHIP_RS600: 2298 rdev->asic = &rs600_asic; 2299 break; 2300 case CHIP_RS690: 2301 case CHIP_RS740: 2302 rdev->asic = &rs690_asic; 2303 break; 2304 case CHIP_RV515: 2305 rdev->asic = &rv515_asic; 2306 break; 2307 case CHIP_R520: 2308 case CHIP_RV530: 2309 case CHIP_RV560: 2310 case CHIP_RV570: 2311 case CHIP_R580: 2312 rdev->asic = &r520_asic; 2313 break; 2314 case CHIP_R600: 2315 rdev->asic = &r600_asic; 2316 break; 2317 case CHIP_RV610: 2318 case CHIP_RV630: 2319 case CHIP_RV620: 2320 case CHIP_RV635: 2321 case CHIP_RV670: 2322 rdev->asic = &rv6xx_asic; 2323 rdev->has_uvd = true; 2324 break; 2325 case CHIP_RS780: 2326 case CHIP_RS880: 2327 rdev->asic = &rs780_asic; 2328 rdev->has_uvd = true; 2329 break; 2330 case CHIP_RV770: 2331 case CHIP_RV730: 2332 case CHIP_RV710: 2333 case CHIP_RV740: 2334 rdev->asic = &rv770_asic; 2335 rdev->has_uvd = true; 2336 break; 2337 case CHIP_CEDAR: 2338 case CHIP_REDWOOD: 2339 case CHIP_JUNIPER: 2340 case CHIP_CYPRESS: 2341 case CHIP_HEMLOCK: 2342 /* set num crtcs */ 2343 if (rdev->family == CHIP_CEDAR) 2344 rdev->num_crtc = 4; 2345 else 2346 rdev->num_crtc = 6; 2347 rdev->asic = &evergreen_asic; 2348 rdev->has_uvd = true; 2349 break; 2350 case CHIP_PALM: 2351 case CHIP_SUMO: 2352 case CHIP_SUMO2: 2353 rdev->asic = &sumo_asic; 2354 rdev->has_uvd = true; 2355 break; 2356 case CHIP_BARTS: 2357 case CHIP_TURKS: 2358 case CHIP_CAICOS: 2359 /* set num crtcs */ 2360 if (rdev->family == CHIP_CAICOS) 2361 rdev->num_crtc = 4; 2362 else 2363 rdev->num_crtc = 6; 2364 rdev->asic = &btc_asic; 2365 rdev->has_uvd = true; 2366 break; 2367 case CHIP_CAYMAN: 2368 rdev->asic = &cayman_asic; 2369 /* set num crtcs */ 2370 rdev->num_crtc = 6; 2371 rdev->has_uvd = true; 2372 break; 2373 case CHIP_ARUBA: 2374 rdev->asic = &trinity_asic; 2375 /* set num crtcs */ 2376 rdev->num_crtc = 4; 2377 rdev->has_uvd = true; 2378 break; 2379 case CHIP_TAHITI: 2380 case CHIP_PITCAIRN: 2381 case CHIP_VERDE: 2382 case CHIP_OLAND: 2383 case CHIP_HAINAN: 2384 rdev->asic = &si_asic; 2385 /* set num crtcs */ 2386 if (rdev->family == CHIP_HAINAN) 2387 rdev->num_crtc = 0; 2388 else if (rdev->family == CHIP_OLAND) 2389 rdev->num_crtc = 2; 2390 else 2391 rdev->num_crtc = 6; 2392 if (rdev->family == CHIP_HAINAN) 2393 rdev->has_uvd = false; 2394 else 2395 rdev->has_uvd = true; 2396 switch (rdev->family) { 2397 case CHIP_TAHITI: 2398 rdev->cg_flags = 2399 RADEON_CG_SUPPORT_GFX_MGCG | 2400 RADEON_CG_SUPPORT_GFX_MGLS | 2401 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2402 RADEON_CG_SUPPORT_GFX_CGLS | 2403 RADEON_CG_SUPPORT_GFX_CGTS | 2404 RADEON_CG_SUPPORT_GFX_CP_LS | 2405 RADEON_CG_SUPPORT_MC_MGCG | 2406 RADEON_CG_SUPPORT_SDMA_MGCG | 2407 RADEON_CG_SUPPORT_BIF_LS | 2408 RADEON_CG_SUPPORT_VCE_MGCG | 2409 RADEON_CG_SUPPORT_UVD_MGCG | 2410 RADEON_CG_SUPPORT_HDP_LS | 2411 RADEON_CG_SUPPORT_HDP_MGCG; 2412 rdev->pg_flags = 0; 2413 break; 2414 case CHIP_PITCAIRN: 2415 rdev->cg_flags = 2416 RADEON_CG_SUPPORT_GFX_MGCG | 2417 RADEON_CG_SUPPORT_GFX_MGLS | 2418 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2419 RADEON_CG_SUPPORT_GFX_CGLS | 2420 RADEON_CG_SUPPORT_GFX_CGTS | 2421 RADEON_CG_SUPPORT_GFX_CP_LS | 2422 RADEON_CG_SUPPORT_GFX_RLC_LS | 2423 RADEON_CG_SUPPORT_MC_LS | 2424 RADEON_CG_SUPPORT_MC_MGCG | 2425 RADEON_CG_SUPPORT_SDMA_MGCG | 2426 RADEON_CG_SUPPORT_BIF_LS | 2427 RADEON_CG_SUPPORT_VCE_MGCG | 2428 RADEON_CG_SUPPORT_UVD_MGCG | 2429 RADEON_CG_SUPPORT_HDP_LS | 2430 RADEON_CG_SUPPORT_HDP_MGCG; 2431 rdev->pg_flags = 0; 2432 break; 2433 case CHIP_VERDE: 2434 rdev->cg_flags = 2435 RADEON_CG_SUPPORT_GFX_MGCG | 2436 RADEON_CG_SUPPORT_GFX_MGLS | 2437 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2438 RADEON_CG_SUPPORT_GFX_CGLS | 2439 RADEON_CG_SUPPORT_GFX_CGTS | 2440 RADEON_CG_SUPPORT_GFX_CP_LS | 2441 RADEON_CG_SUPPORT_GFX_RLC_LS | 2442 RADEON_CG_SUPPORT_MC_LS | 2443 RADEON_CG_SUPPORT_MC_MGCG | 2444 RADEON_CG_SUPPORT_SDMA_MGCG | 2445 RADEON_CG_SUPPORT_BIF_LS | 2446 RADEON_CG_SUPPORT_VCE_MGCG | 2447 RADEON_CG_SUPPORT_UVD_MGCG | 2448 RADEON_CG_SUPPORT_HDP_LS | 2449 RADEON_CG_SUPPORT_HDP_MGCG; 2450 rdev->pg_flags = 0 | 2451 /*RADEON_PG_SUPPORT_GFX_PG | */ 2452 RADEON_PG_SUPPORT_SDMA; 2453 break; 2454 case CHIP_OLAND: 2455 rdev->cg_flags = 2456 RADEON_CG_SUPPORT_GFX_MGCG | 2457 RADEON_CG_SUPPORT_GFX_MGLS | 2458 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2459 RADEON_CG_SUPPORT_GFX_CGLS | 2460 RADEON_CG_SUPPORT_GFX_CGTS | 2461 RADEON_CG_SUPPORT_GFX_CP_LS | 2462 RADEON_CG_SUPPORT_GFX_RLC_LS | 2463 RADEON_CG_SUPPORT_MC_LS | 2464 RADEON_CG_SUPPORT_MC_MGCG | 2465 RADEON_CG_SUPPORT_SDMA_MGCG | 2466 RADEON_CG_SUPPORT_BIF_LS | 2467 RADEON_CG_SUPPORT_UVD_MGCG | 2468 RADEON_CG_SUPPORT_HDP_LS | 2469 RADEON_CG_SUPPORT_HDP_MGCG; 2470 rdev->pg_flags = 0; 2471 break; 2472 case CHIP_HAINAN: 2473 rdev->cg_flags = 2474 RADEON_CG_SUPPORT_GFX_MGCG | 2475 RADEON_CG_SUPPORT_GFX_MGLS | 2476 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2477 RADEON_CG_SUPPORT_GFX_CGLS | 2478 RADEON_CG_SUPPORT_GFX_CGTS | 2479 RADEON_CG_SUPPORT_GFX_CP_LS | 2480 RADEON_CG_SUPPORT_GFX_RLC_LS | 2481 RADEON_CG_SUPPORT_MC_LS | 2482 RADEON_CG_SUPPORT_MC_MGCG | 2483 RADEON_CG_SUPPORT_SDMA_MGCG | 2484 RADEON_CG_SUPPORT_BIF_LS | 2485 RADEON_CG_SUPPORT_HDP_LS | 2486 RADEON_CG_SUPPORT_HDP_MGCG; 2487 rdev->pg_flags = 0; 2488 break; 2489 default: 2490 rdev->cg_flags = 0; 2491 rdev->pg_flags = 0; 2492 break; 2493 } 2494 break; 2495 case CHIP_BONAIRE: 2496 case CHIP_HAWAII: 2497 rdev->asic = &ci_asic; 2498 rdev->num_crtc = 6; 2499 rdev->has_uvd = true; 2500 if (rdev->family == CHIP_BONAIRE) { 2501 rdev->cg_flags = 2502 RADEON_CG_SUPPORT_GFX_MGCG | 2503 RADEON_CG_SUPPORT_GFX_MGLS | 2504 RADEON_CG_SUPPORT_GFX_CGCG | 2505 RADEON_CG_SUPPORT_GFX_CGLS | 2506 RADEON_CG_SUPPORT_GFX_CGTS | 2507 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2508 RADEON_CG_SUPPORT_GFX_CP_LS | 2509 RADEON_CG_SUPPORT_MC_LS | 2510 RADEON_CG_SUPPORT_MC_MGCG | 2511 RADEON_CG_SUPPORT_SDMA_MGCG | 2512 RADEON_CG_SUPPORT_SDMA_LS | 2513 RADEON_CG_SUPPORT_BIF_LS | 2514 RADEON_CG_SUPPORT_VCE_MGCG | 2515 RADEON_CG_SUPPORT_UVD_MGCG | 2516 RADEON_CG_SUPPORT_HDP_LS | 2517 RADEON_CG_SUPPORT_HDP_MGCG; 2518 rdev->pg_flags = 0; 2519 } else { 2520 rdev->cg_flags = 2521 RADEON_CG_SUPPORT_GFX_MGCG | 2522 RADEON_CG_SUPPORT_GFX_MGLS | 2523 RADEON_CG_SUPPORT_GFX_CGCG | 2524 RADEON_CG_SUPPORT_GFX_CGLS | 2525 RADEON_CG_SUPPORT_GFX_CGTS | 2526 RADEON_CG_SUPPORT_GFX_CP_LS | 2527 RADEON_CG_SUPPORT_MC_LS | 2528 RADEON_CG_SUPPORT_MC_MGCG | 2529 RADEON_CG_SUPPORT_SDMA_MGCG | 2530 RADEON_CG_SUPPORT_SDMA_LS | 2531 RADEON_CG_SUPPORT_BIF_LS | 2532 RADEON_CG_SUPPORT_VCE_MGCG | 2533 RADEON_CG_SUPPORT_UVD_MGCG | 2534 RADEON_CG_SUPPORT_HDP_LS | 2535 RADEON_CG_SUPPORT_HDP_MGCG; 2536 rdev->pg_flags = 0; 2537 } 2538 break; 2539 case CHIP_KAVERI: 2540 case CHIP_KABINI: 2541 case CHIP_MULLINS: 2542 rdev->asic = &kv_asic; 2543 /* set num crtcs */ 2544 if (rdev->family == CHIP_KAVERI) { 2545 rdev->num_crtc = 4; 2546 rdev->cg_flags = 2547 RADEON_CG_SUPPORT_GFX_MGCG | 2548 RADEON_CG_SUPPORT_GFX_MGLS | 2549 RADEON_CG_SUPPORT_GFX_CGCG | 2550 RADEON_CG_SUPPORT_GFX_CGLS | 2551 RADEON_CG_SUPPORT_GFX_CGTS | 2552 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2553 RADEON_CG_SUPPORT_GFX_CP_LS | 2554 RADEON_CG_SUPPORT_SDMA_MGCG | 2555 RADEON_CG_SUPPORT_SDMA_LS | 2556 RADEON_CG_SUPPORT_BIF_LS | 2557 RADEON_CG_SUPPORT_VCE_MGCG | 2558 RADEON_CG_SUPPORT_UVD_MGCG | 2559 RADEON_CG_SUPPORT_HDP_LS | 2560 RADEON_CG_SUPPORT_HDP_MGCG; 2561 rdev->pg_flags = 0; 2562 /*RADEON_PG_SUPPORT_GFX_PG | 2563 RADEON_PG_SUPPORT_GFX_SMG | 2564 RADEON_PG_SUPPORT_GFX_DMG | 2565 RADEON_PG_SUPPORT_UVD | 2566 RADEON_PG_SUPPORT_VCE | 2567 RADEON_PG_SUPPORT_CP | 2568 RADEON_PG_SUPPORT_GDS | 2569 RADEON_PG_SUPPORT_RLC_SMU_HS | 2570 RADEON_PG_SUPPORT_ACP | 2571 RADEON_PG_SUPPORT_SAMU;*/ 2572 } else { 2573 rdev->num_crtc = 2; 2574 rdev->cg_flags = 2575 RADEON_CG_SUPPORT_GFX_MGCG | 2576 RADEON_CG_SUPPORT_GFX_MGLS | 2577 RADEON_CG_SUPPORT_GFX_CGCG | 2578 RADEON_CG_SUPPORT_GFX_CGLS | 2579 RADEON_CG_SUPPORT_GFX_CGTS | 2580 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2581 RADEON_CG_SUPPORT_GFX_CP_LS | 2582 RADEON_CG_SUPPORT_SDMA_MGCG | 2583 RADEON_CG_SUPPORT_SDMA_LS | 2584 RADEON_CG_SUPPORT_BIF_LS | 2585 RADEON_CG_SUPPORT_VCE_MGCG | 2586 RADEON_CG_SUPPORT_UVD_MGCG | 2587 RADEON_CG_SUPPORT_HDP_LS | 2588 RADEON_CG_SUPPORT_HDP_MGCG; 2589 rdev->pg_flags = 0; 2590 /*RADEON_PG_SUPPORT_GFX_PG | 2591 RADEON_PG_SUPPORT_GFX_SMG | 2592 RADEON_PG_SUPPORT_UVD | 2593 RADEON_PG_SUPPORT_VCE | 2594 RADEON_PG_SUPPORT_CP | 2595 RADEON_PG_SUPPORT_GDS | 2596 RADEON_PG_SUPPORT_RLC_SMU_HS | 2597 RADEON_PG_SUPPORT_SAMU;*/ 2598 } 2599 rdev->has_uvd = true; 2600 break; 2601 default: 2602 /* FIXME: not supported yet */ 2603 return -EINVAL; 2604 } 2605 2606 if (rdev->flags & RADEON_IS_IGP) { 2607 rdev->asic->pm.get_memory_clock = NULL; 2608 rdev->asic->pm.set_memory_clock = NULL; 2609 } 2610 2611 return 0; 2612 } 2613 2614