1 /* $NetBSD: nouveau_nv84_fence.c,v 1.7 2020/02/14 04:35:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: nouveau_nv84_fence.c,v 1.7 2020/02/14 04:35:20 riastradh Exp $"); 29 30 #include "nouveau_drm.h" 31 #include "nouveau_dma.h" 32 #include "nouveau_fence.h" 33 34 #include "nv50_display.h" 35 36 #include <linux/nbsd-namespace.h> 37 38 u64 39 nv84_fence_crtc(struct nouveau_channel *chan, int crtc) 40 { 41 struct nv84_fence_chan *fctx = chan->fence; 42 return fctx->dispc_vma[crtc].offset; 43 } 44 45 static int 46 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) 47 { 48 int ret = RING_SPACE(chan, 8); 49 if (ret == 0) { 50 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); 51 OUT_RING (chan, chan->vram.handle); 52 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); 53 OUT_RING (chan, upper_32_bits(virtual)); 54 OUT_RING (chan, lower_32_bits(virtual)); 55 OUT_RING (chan, sequence); 56 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); 57 OUT_RING (chan, 0x00000000); 58 FIRE_RING (chan); 59 } 60 return ret; 61 } 62 63 static int 64 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) 65 { 66 int ret = RING_SPACE(chan, 7); 67 if (ret == 0) { 68 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); 69 OUT_RING (chan, chan->vram.handle); 70 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); 71 OUT_RING (chan, upper_32_bits(virtual)); 72 OUT_RING (chan, lower_32_bits(virtual)); 73 OUT_RING (chan, sequence); 74 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); 75 FIRE_RING (chan); 76 } 77 return ret; 78 } 79 80 static int 81 nv84_fence_emit(struct nouveau_fence *fence) 82 { 83 struct nouveau_channel *chan = fence->channel; 84 struct nv84_fence_chan *fctx = chan->fence; 85 u64 addr = chan->chid * 16; 86 87 if (fence->sysmem) 88 addr += fctx->vma_gart.offset; 89 else 90 addr += fctx->vma.offset; 91 92 return fctx->base.emit32(chan, addr, fence->base.seqno); 93 } 94 95 static int 96 nv84_fence_sync(struct nouveau_fence *fence, 97 struct nouveau_channel *prev, struct nouveau_channel *chan) 98 { 99 struct nv84_fence_chan *fctx = chan->fence; 100 u64 addr = prev->chid * 16; 101 102 if (fence->sysmem) 103 addr += fctx->vma_gart.offset; 104 else 105 addr += fctx->vma.offset; 106 107 return fctx->base.sync32(chan, addr, fence->base.seqno); 108 } 109 110 static u32 111 nv84_fence_read(struct nouveau_channel *chan) 112 { 113 struct nv84_fence_priv *priv = chan->drm->fence; 114 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); 115 } 116 117 static void 118 nv84_fence_context_del(struct nouveau_channel *chan) 119 { 120 struct drm_device *dev = chan->drm->dev; 121 struct nv84_fence_priv *priv = chan->drm->fence; 122 struct nv84_fence_chan *fctx = chan->fence; 123 int i; 124 125 for (i = 0; i < dev->mode_config.num_crtc; i++) { 126 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); 127 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); 128 } 129 130 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); 131 mutex_lock(&priv->mutex); 132 nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); 133 nouveau_bo_vma_del(priv->bo, &fctx->vma); 134 mutex_unlock(&priv->mutex); 135 nouveau_fence_context_del(&fctx->base); 136 chan->fence = NULL; 137 nouveau_fence_context_free(&fctx->base); 138 } 139 140 int 141 nv84_fence_context_new(struct nouveau_channel *chan) 142 { 143 struct nouveau_cli *cli = (void *)chan->user.client; 144 struct nv84_fence_priv *priv = chan->drm->fence; 145 struct nv84_fence_chan *fctx; 146 int ret, i; 147 148 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); 149 if (!fctx) 150 return -ENOMEM; 151 152 nouveau_fence_context_new(chan, &fctx->base); 153 fctx->base.emit = nv84_fence_emit; 154 fctx->base.sync = nv84_fence_sync; 155 fctx->base.read = nv84_fence_read; 156 fctx->base.emit32 = nv84_fence_emit32; 157 fctx->base.sync32 = nv84_fence_sync32; 158 fctx->base.sequence = nv84_fence_read(chan); 159 160 mutex_lock(&priv->mutex); 161 ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma); 162 if (ret == 0) { 163 ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm, 164 &fctx->vma_gart); 165 } 166 mutex_unlock(&priv->mutex); 167 168 /* map display semaphore buffers into channel's vm */ 169 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { 170 struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i); 171 ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]); 172 } 173 174 if (ret) 175 nv84_fence_context_del(chan); 176 return ret; 177 } 178 179 static bool 180 nv84_fence_suspend(struct nouveau_drm *drm) 181 { 182 struct nv84_fence_priv *priv = drm->fence; 183 int i; 184 185 priv->suspend = vmalloc(priv->base.contexts * sizeof(u32)); 186 if (priv->suspend) { 187 for (i = 0; i < priv->base.contexts; i++) 188 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4); 189 } 190 191 return priv->suspend != NULL; 192 } 193 194 static void 195 nv84_fence_resume(struct nouveau_drm *drm) 196 { 197 struct nv84_fence_priv *priv = drm->fence; 198 int i; 199 200 if (priv->suspend) { 201 for (i = 0; i < priv->base.contexts; i++) 202 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]); 203 vfree(priv->suspend); 204 priv->suspend = NULL; 205 } 206 } 207 208 static void 209 nv84_fence_destroy(struct nouveau_drm *drm) 210 { 211 struct nv84_fence_priv *priv = drm->fence; 212 213 nouveau_bo_unmap(priv->bo_gart); 214 if (priv->bo_gart) 215 nouveau_bo_unpin(priv->bo_gart); 216 nouveau_bo_ref(NULL, &priv->bo_gart); 217 nouveau_bo_unmap(priv->bo); 218 if (priv->bo) 219 nouveau_bo_unpin(priv->bo); 220 nouveau_bo_ref(NULL, &priv->bo); 221 drm->fence = NULL; 222 mutex_destroy(&priv->mutex); 223 kfree(priv); 224 } 225 226 int 227 nv84_fence_create(struct nouveau_drm *drm) 228 { 229 struct nvkm_fifo *fifo = nvxx_fifo(&drm->device); 230 struct nv84_fence_priv *priv; 231 u32 domain; 232 int ret; 233 234 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); 235 if (!priv) 236 return -ENOMEM; 237 238 priv->base.dtor = nv84_fence_destroy; 239 priv->base.suspend = nv84_fence_suspend; 240 priv->base.resume = nv84_fence_resume; 241 priv->base.context_new = nv84_fence_context_new; 242 priv->base.context_del = nv84_fence_context_del; 243 244 priv->base.contexts = fifo->nr; 245 priv->base.context_base = fence_context_alloc(priv->base.contexts); 246 priv->base.uevent = true; 247 248 mutex_init(&priv->mutex); 249 250 /* Use VRAM if there is any ; otherwise fallback to system memory */ 251 domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : 252 /* 253 * fences created in sysmem must be non-cached or we 254 * will lose CPU/GPU coherency! 255 */ 256 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 257 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0, 258 0, NULL, NULL, &priv->bo); 259 if (ret == 0) { 260 ret = nouveau_bo_pin(priv->bo, domain, false); 261 if (ret == 0) { 262 ret = nouveau_bo_map(priv->bo); 263 if (ret) 264 nouveau_bo_unpin(priv->bo); 265 } 266 if (ret) 267 nouveau_bo_ref(NULL, &priv->bo); 268 } 269 270 if (ret == 0) 271 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, 272 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0, 273 0, NULL, NULL, &priv->bo_gart); 274 if (ret == 0) { 275 ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT, false); 276 if (ret == 0) { 277 ret = nouveau_bo_map(priv->bo_gart); 278 if (ret) 279 nouveau_bo_unpin(priv->bo_gart); 280 } 281 if (ret) 282 nouveau_bo_ref(NULL, &priv->bo_gart); 283 } 284 285 if (ret) 286 nv84_fence_destroy(drm); 287 return ret; 288 } 289