1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <drm/intel-gtt.h> 40 #include <linux/backlight.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/completion.h> 44 #include <linux/shrinker.h> 45 46 /* General customization: 47 */ 48 49 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 50 51 #define DRIVER_NAME "i915" 52 #define DRIVER_DESC "Intel Graphics" 53 #define DRIVER_DATE "20080730" 54 55 enum pipe { 56 PIPE_A = 0, 57 PIPE_B, 58 PIPE_C, 59 I915_MAX_PIPES 60 }; 61 #define pipe_name(p) ((p) + 'A') 62 63 enum transcoder { 64 TRANSCODER_A = 0, 65 TRANSCODER_B, 66 TRANSCODER_C, 67 TRANSCODER_EDP = 0xF, 68 }; 69 #define transcoder_name(t) ((t) + 'A') 70 71 enum plane { 72 PLANE_A = 0, 73 PLANE_B, 74 PLANE_C, 75 }; 76 #define plane_name(p) ((p) + 'A') 77 78 enum port { 79 PORT_A = 0, 80 PORT_B, 81 PORT_C, 82 PORT_D, 83 PORT_E, 84 I915_MAX_PORTS 85 }; 86 #define port_name(p) ((p) + 'A') 87 88 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 89 90 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 91 92 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 93 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 94 if ((intel_encoder)->base.crtc == (__crtc)) 95 96 struct intel_pch_pll { 97 int refcount; /* count of number of CRTCs sharing this PLL */ 98 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 99 bool on; /* is the PLL actually active? Disabled during modeset */ 100 int pll_reg; 101 int fp0_reg; 102 int fp1_reg; 103 }; 104 #define I915_NUM_PLLS 2 105 106 struct intel_ddi_plls { 107 int spll_refcount; 108 int wrpll1_refcount; 109 int wrpll2_refcount; 110 }; 111 112 /* Interface history: 113 * 114 * 1.1: Original. 115 * 1.2: Add Power Management 116 * 1.3: Add vblank support 117 * 1.4: Fix cmdbuffer path, add heap destroy 118 * 1.5: Add vblank pipe configuration 119 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 120 * - Support vertical blank on secondary display pipe 121 */ 122 #define DRIVER_MAJOR 1 123 #define DRIVER_MINOR 6 124 #define DRIVER_PATCHLEVEL 0 125 126 #define WATCH_COHERENCY 0 127 #define WATCH_LISTS 0 128 #define WATCH_GTT 0 129 130 #define I915_GEM_PHYS_CURSOR_0 1 131 #define I915_GEM_PHYS_CURSOR_1 2 132 #define I915_GEM_PHYS_OVERLAY_REGS 3 133 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 134 135 struct drm_i915_gem_phys_object { 136 int id; 137 struct page **page_list; 138 drm_dma_handle_t *handle; 139 struct drm_i915_gem_object *cur_obj; 140 }; 141 142 struct opregion_header; 143 struct opregion_acpi; 144 struct opregion_swsci; 145 struct opregion_asle; 146 struct drm_i915_private; 147 148 #ifdef __NetBSD__ /* XXX acpi iomem */ 149 # include <linux/acpi_io.h> 150 # define __iomem __acpi_iomem 151 #endif 152 153 struct intel_opregion { 154 struct opregion_header __iomem *header; 155 struct opregion_acpi __iomem *acpi; 156 struct opregion_swsci __iomem *swsci; 157 struct opregion_asle __iomem *asle; 158 void __iomem *vbt; 159 u32 __iomem *lid_state; 160 }; 161 #define OPREGION_SIZE (8*1024) 162 163 #ifdef __NetBSD__ /* XXX acpi iomem */ 164 # undef __iomem 165 #endif 166 167 struct intel_overlay; 168 struct intel_overlay_error_state; 169 170 struct drm_i915_master_private { 171 drm_local_map_t *sarea; 172 struct _drm_i915_sarea *sarea_priv; 173 }; 174 #define I915_FENCE_REG_NONE -1 175 #define I915_MAX_NUM_FENCES 16 176 /* 16 fences + sign bit for FENCE_REG_NONE */ 177 #define I915_MAX_NUM_FENCE_BITS 5 178 179 struct drm_i915_fence_reg { 180 struct list_head lru_list; 181 struct drm_i915_gem_object *obj; 182 int pin_count; 183 }; 184 185 struct sdvo_device_mapping { 186 u8 initialized; 187 u8 dvo_port; 188 u8 slave_addr; 189 u8 dvo_wiring; 190 u8 i2c_pin; 191 u8 ddc_pin; 192 }; 193 194 struct intel_display_error_state; 195 196 struct drm_i915_error_state { 197 struct kref ref; 198 u32 eir; 199 u32 pgtbl_er; 200 u32 ier; 201 u32 ccid; 202 u32 derrmr; 203 u32 forcewake; 204 bool waiting[I915_NUM_RINGS]; 205 u32 pipestat[I915_MAX_PIPES]; 206 u32 tail[I915_NUM_RINGS]; 207 u32 head[I915_NUM_RINGS]; 208 u32 ctl[I915_NUM_RINGS]; 209 u32 ipeir[I915_NUM_RINGS]; 210 u32 ipehr[I915_NUM_RINGS]; 211 u32 instdone[I915_NUM_RINGS]; 212 u32 acthd[I915_NUM_RINGS]; 213 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 214 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 215 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 216 /* our own tracking of ring head and tail */ 217 u32 cpu_ring_head[I915_NUM_RINGS]; 218 u32 cpu_ring_tail[I915_NUM_RINGS]; 219 u32 error; /* gen6+ */ 220 u32 err_int; /* gen7 */ 221 u32 instpm[I915_NUM_RINGS]; 222 u32 instps[I915_NUM_RINGS]; 223 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 224 u32 seqno[I915_NUM_RINGS]; 225 u64 bbaddr; 226 u32 fault_reg[I915_NUM_RINGS]; 227 u32 done_reg; 228 u32 faddr[I915_NUM_RINGS]; 229 u64 fence[I915_MAX_NUM_FENCES]; 230 struct timeval time; 231 struct drm_i915_error_ring { 232 struct drm_i915_error_object { 233 int page_count; 234 u32 gtt_offset; 235 u32 *pages[0]; 236 } *ringbuffer, *batchbuffer; 237 struct drm_i915_error_request { 238 long jiffies; 239 u32 seqno; 240 u32 tail; 241 } *requests; 242 int num_requests; 243 } ring[I915_NUM_RINGS]; 244 struct drm_i915_error_buffer { 245 u32 size; 246 u32 name; 247 u32 rseqno, wseqno; 248 u32 gtt_offset; 249 u32 read_domains; 250 u32 write_domain; 251 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 252 s32 pinned:2; 253 u32 tiling:2; 254 u32 dirty:1; 255 u32 purgeable:1; 256 s32 ring:4; 257 u32 cache_level:2; 258 } *active_bo, *pinned_bo; 259 u32 active_bo_count, pinned_bo_count; 260 struct intel_overlay_error_state *overlay; 261 struct intel_display_error_state *display; 262 }; 263 264 struct drm_i915_display_funcs { 265 bool (*fbc_enabled)(struct drm_device *dev); 266 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 267 void (*disable_fbc)(struct drm_device *dev); 268 int (*get_display_clock_speed)(struct drm_device *dev); 269 int (*get_fifo_size)(struct drm_device *dev, int plane); 270 void (*update_wm)(struct drm_device *dev); 271 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 272 uint32_t sprite_width, int pixel_size); 273 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 274 struct drm_display_mode *mode); 275 void (*modeset_global_resources)(struct drm_device *dev); 276 int (*crtc_mode_set)(struct drm_crtc *crtc, 277 struct drm_display_mode *mode, 278 struct drm_display_mode *adjusted_mode, 279 int x, int y, 280 struct drm_framebuffer *old_fb); 281 void (*crtc_enable)(struct drm_crtc *crtc); 282 void (*crtc_disable)(struct drm_crtc *crtc); 283 void (*off)(struct drm_crtc *crtc); 284 void (*write_eld)(struct drm_connector *connector, 285 struct drm_crtc *crtc); 286 void (*fdi_link_train)(struct drm_crtc *crtc); 287 void (*init_clock_gating)(struct drm_device *dev); 288 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 289 struct drm_framebuffer *fb, 290 struct drm_i915_gem_object *obj); 291 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 292 int x, int y); 293 /* clock updates for mode set */ 294 /* cursor updates */ 295 /* render clock increase/decrease */ 296 /* display clock increase/decrease */ 297 /* pll clock increase/decrease */ 298 }; 299 300 struct drm_i915_gt_funcs { 301 void (*force_wake_get)(struct drm_i915_private *dev_priv); 302 void (*force_wake_put)(struct drm_i915_private *dev_priv); 303 }; 304 305 #define DEV_INFO_FLAGS \ 306 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 307 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 308 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 309 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 310 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 311 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 312 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 313 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 314 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 315 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 316 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 317 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 318 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 319 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 320 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 321 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 322 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 323 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 324 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 325 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 326 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 327 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 328 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 329 DEV_INFO_FLAG(has_llc) 330 331 struct intel_device_info { 332 u8 gen; 333 u8 is_mobile:1; 334 u8 is_i85x:1; 335 u8 is_i915g:1; 336 u8 is_i945gm:1; 337 u8 is_g33:1; 338 u8 need_gfx_hws:1; 339 u8 is_g4x:1; 340 u8 is_pineview:1; 341 u8 is_broadwater:1; 342 u8 is_crestline:1; 343 u8 is_ivybridge:1; 344 u8 is_valleyview:1; 345 u8 has_force_wake:1; 346 u8 is_haswell:1; 347 u8 has_fbc:1; 348 u8 has_pipe_cxsr:1; 349 u8 has_hotplug:1; 350 u8 cursor_needs_physical:1; 351 u8 has_overlay:1; 352 u8 overlay_needs_physical:1; 353 u8 supports_tv:1; 354 u8 has_bsd_ring:1; 355 u8 has_blt_ring:1; 356 u8 has_llc:1; 357 }; 358 359 #define I915_PPGTT_PD_ENTRIES 512 360 #define I915_PPGTT_PT_ENTRIES 1024 361 struct i915_hw_ppgtt { 362 struct drm_device *dev; 363 unsigned num_pd_entries; 364 struct page **pt_pages; 365 uint32_t pd_offset; 366 dma_addr_t *pt_dma_addr; 367 dma_addr_t scratch_page_dma_addr; 368 }; 369 370 371 /* This must match up with the value previously used for execbuf2.rsvd1. */ 372 #define DEFAULT_CONTEXT_ID 0 373 struct i915_hw_context { 374 int id; 375 bool is_initialized; 376 struct drm_i915_file_private *file_priv; 377 struct intel_ring_buffer *ring; 378 struct drm_i915_gem_object *obj; 379 }; 380 381 enum no_fbc_reason { 382 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 383 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 384 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 385 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 386 FBC_BAD_PLANE, /* fbc not supported on plane */ 387 FBC_NOT_TILED, /* buffer not tiled */ 388 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 389 FBC_MODULE_PARAM, 390 }; 391 392 enum intel_pch { 393 PCH_NONE = 0, /* No PCH present */ 394 PCH_IBX, /* Ibexpeak PCH */ 395 PCH_CPT, /* Cougarpoint PCH */ 396 PCH_LPT, /* Lynxpoint PCH */ 397 }; 398 399 enum intel_sbi_destination { 400 SBI_ICLK, 401 SBI_MPHY, 402 }; 403 404 #define QUIRK_PIPEA_FORCE (1<<0) 405 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 406 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 407 408 struct intel_fbdev; 409 struct intel_fbc_work; 410 411 struct intel_gmbus { 412 struct i2c_adapter adapter; 413 u32 force_bit; 414 u32 reg0; 415 u32 gpio_reg; 416 struct i2c_algo_bit_data bit_algo; 417 struct drm_i915_private *dev_priv; 418 }; 419 420 struct i915_suspend_saved_registers { 421 u8 saveLBB; 422 u32 saveDSPACNTR; 423 u32 saveDSPBCNTR; 424 u32 saveDSPARB; 425 u32 savePIPEACONF; 426 u32 savePIPEBCONF; 427 u32 savePIPEASRC; 428 u32 savePIPEBSRC; 429 u32 saveFPA0; 430 u32 saveFPA1; 431 u32 saveDPLL_A; 432 u32 saveDPLL_A_MD; 433 u32 saveHTOTAL_A; 434 u32 saveHBLANK_A; 435 u32 saveHSYNC_A; 436 u32 saveVTOTAL_A; 437 u32 saveVBLANK_A; 438 u32 saveVSYNC_A; 439 u32 saveBCLRPAT_A; 440 u32 saveTRANSACONF; 441 u32 saveTRANS_HTOTAL_A; 442 u32 saveTRANS_HBLANK_A; 443 u32 saveTRANS_HSYNC_A; 444 u32 saveTRANS_VTOTAL_A; 445 u32 saveTRANS_VBLANK_A; 446 u32 saveTRANS_VSYNC_A; 447 u32 savePIPEASTAT; 448 u32 saveDSPASTRIDE; 449 u32 saveDSPASIZE; 450 u32 saveDSPAPOS; 451 u32 saveDSPAADDR; 452 u32 saveDSPASURF; 453 u32 saveDSPATILEOFF; 454 u32 savePFIT_PGM_RATIOS; 455 u32 saveBLC_HIST_CTL; 456 u32 saveBLC_PWM_CTL; 457 u32 saveBLC_PWM_CTL2; 458 u32 saveBLC_CPU_PWM_CTL; 459 u32 saveBLC_CPU_PWM_CTL2; 460 u32 saveFPB0; 461 u32 saveFPB1; 462 u32 saveDPLL_B; 463 u32 saveDPLL_B_MD; 464 u32 saveHTOTAL_B; 465 u32 saveHBLANK_B; 466 u32 saveHSYNC_B; 467 u32 saveVTOTAL_B; 468 u32 saveVBLANK_B; 469 u32 saveVSYNC_B; 470 u32 saveBCLRPAT_B; 471 u32 saveTRANSBCONF; 472 u32 saveTRANS_HTOTAL_B; 473 u32 saveTRANS_HBLANK_B; 474 u32 saveTRANS_HSYNC_B; 475 u32 saveTRANS_VTOTAL_B; 476 u32 saveTRANS_VBLANK_B; 477 u32 saveTRANS_VSYNC_B; 478 u32 savePIPEBSTAT; 479 u32 saveDSPBSTRIDE; 480 u32 saveDSPBSIZE; 481 u32 saveDSPBPOS; 482 u32 saveDSPBADDR; 483 u32 saveDSPBSURF; 484 u32 saveDSPBTILEOFF; 485 u32 saveVGA0; 486 u32 saveVGA1; 487 u32 saveVGA_PD; 488 u32 saveVGACNTRL; 489 u32 saveADPA; 490 u32 saveLVDS; 491 u32 savePP_ON_DELAYS; 492 u32 savePP_OFF_DELAYS; 493 u32 saveDVOA; 494 u32 saveDVOB; 495 u32 saveDVOC; 496 u32 savePP_ON; 497 u32 savePP_OFF; 498 u32 savePP_CONTROL; 499 u32 savePP_DIVISOR; 500 u32 savePFIT_CONTROL; 501 u32 save_palette_a[256]; 502 u32 save_palette_b[256]; 503 u32 saveDPFC_CB_BASE; 504 u32 saveFBC_CFB_BASE; 505 u32 saveFBC_LL_BASE; 506 u32 saveFBC_CONTROL; 507 u32 saveFBC_CONTROL2; 508 u32 saveIER; 509 u32 saveIIR; 510 u32 saveIMR; 511 u32 saveDEIER; 512 u32 saveDEIMR; 513 u32 saveGTIER; 514 u32 saveGTIMR; 515 u32 saveFDI_RXA_IMR; 516 u32 saveFDI_RXB_IMR; 517 u32 saveCACHE_MODE_0; 518 u32 saveMI_ARB_STATE; 519 u32 saveSWF0[16]; 520 u32 saveSWF1[16]; 521 u32 saveSWF2[3]; 522 u8 saveMSR; 523 u8 saveSR[8]; 524 u8 saveGR[25]; 525 u8 saveAR_INDEX; 526 u8 saveAR[21]; 527 u8 saveDACMASK; 528 u8 saveCR[37]; 529 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 530 u32 saveCURACNTR; 531 u32 saveCURAPOS; 532 u32 saveCURABASE; 533 u32 saveCURBCNTR; 534 u32 saveCURBPOS; 535 u32 saveCURBBASE; 536 u32 saveCURSIZE; 537 u32 saveDP_B; 538 u32 saveDP_C; 539 u32 saveDP_D; 540 u32 savePIPEA_GMCH_DATA_M; 541 u32 savePIPEB_GMCH_DATA_M; 542 u32 savePIPEA_GMCH_DATA_N; 543 u32 savePIPEB_GMCH_DATA_N; 544 u32 savePIPEA_DP_LINK_M; 545 u32 savePIPEB_DP_LINK_M; 546 u32 savePIPEA_DP_LINK_N; 547 u32 savePIPEB_DP_LINK_N; 548 u32 saveFDI_RXA_CTL; 549 u32 saveFDI_TXA_CTL; 550 u32 saveFDI_RXB_CTL; 551 u32 saveFDI_TXB_CTL; 552 u32 savePFA_CTL_1; 553 u32 savePFB_CTL_1; 554 u32 savePFA_WIN_SZ; 555 u32 savePFB_WIN_SZ; 556 u32 savePFA_WIN_POS; 557 u32 savePFB_WIN_POS; 558 u32 savePCH_DREF_CONTROL; 559 u32 saveDISP_ARB_CTL; 560 u32 savePIPEA_DATA_M1; 561 u32 savePIPEA_DATA_N1; 562 u32 savePIPEA_LINK_M1; 563 u32 savePIPEA_LINK_N1; 564 u32 savePIPEB_DATA_M1; 565 u32 savePIPEB_DATA_N1; 566 u32 savePIPEB_LINK_M1; 567 u32 savePIPEB_LINK_N1; 568 u32 saveMCHBAR_RENDER_STANDBY; 569 u32 savePCH_PORT_HOTPLUG; 570 }; 571 572 struct intel_gen6_power_mgmt { 573 struct work_struct work; 574 u32 pm_iir; 575 /* lock - irqsave spinlock that protectects the work_struct and 576 * pm_iir. */ 577 spinlock_t lock; 578 579 /* The below variables an all the rps hw state are protected by 580 * dev->struct mutext. */ 581 u8 cur_delay; 582 u8 min_delay; 583 u8 max_delay; 584 585 struct delayed_work delayed_resume_work; 586 587 /* 588 * Protects RPS/RC6 register access and PCU communication. 589 * Must be taken after struct_mutex if nested. 590 */ 591 struct mutex hw_lock; 592 }; 593 594 struct intel_ilk_power_mgmt { 595 u8 cur_delay; 596 u8 min_delay; 597 u8 max_delay; 598 u8 fmax; 599 u8 fstart; 600 601 u64 last_count1; 602 unsigned long last_time1; 603 unsigned long chipset_power; 604 u64 last_count2; 605 struct timespec last_time2; 606 unsigned long gfx_power; 607 u8 corr; 608 609 int c_m; 610 int r_t; 611 612 struct drm_i915_gem_object *pwrctx; 613 struct drm_i915_gem_object *renderctx; 614 }; 615 616 struct i915_dri1_state { 617 unsigned allow_batchbuffer : 1; 618 #ifdef __NetBSD__ 619 struct drm_local_map gfx_hws_cpu_map; 620 #else 621 u32 __iomem *gfx_hws_cpu_addr; 622 #endif 623 624 unsigned int cpp; 625 int back_offset; 626 int front_offset; 627 int current_page; 628 int page_flipping; 629 630 uint32_t counter; 631 }; 632 633 struct intel_l3_parity { 634 u32 *remap_info; 635 struct work_struct error_work; 636 }; 637 638 typedef struct drm_i915_private { 639 struct drm_device *dev; 640 641 const struct intel_device_info *info; 642 643 int relative_constants_mode; 644 645 #ifdef __NetBSD__ 646 struct drm_local_map *regs_map; 647 #else 648 void __iomem *regs; 649 #endif 650 651 struct drm_i915_gt_funcs gt; 652 /** gt_fifo_count and the subsequent register write are synchronized 653 * with dev->struct_mutex. */ 654 unsigned gt_fifo_count; 655 /** forcewake_count is protected by gt_lock */ 656 unsigned forcewake_count; 657 /** gt_lock is also taken in irq contexts. */ 658 struct spinlock gt_lock; 659 660 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 661 662 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 663 * controller on different i2c buses. */ 664 struct mutex gmbus_mutex; 665 666 /** 667 * Base address of the gmbus and gpio block. 668 */ 669 uint32_t gpio_mmio_base; 670 671 struct pci_dev *bridge_dev; 672 struct intel_ring_buffer ring[I915_NUM_RINGS]; 673 uint32_t next_seqno; 674 675 drm_dma_handle_t *status_page_dmah; 676 struct resource mch_res; 677 678 atomic_t irq_received; 679 680 /* protects the irq masks */ 681 spinlock_t irq_lock; 682 683 /* DPIO indirect register protection */ 684 spinlock_t dpio_lock; 685 686 /** Cached value of IMR to avoid reads in updating the bitfield */ 687 u32 pipestat[2]; 688 u32 irq_mask; 689 u32 gt_irq_mask; 690 u32 pch_irq_mask; 691 692 u32 hotplug_supported_mask; 693 struct work_struct hotplug_work; 694 695 int num_pipe; 696 int num_pch_pll; 697 698 /* For hangcheck timer */ 699 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 700 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 701 struct timer_list hangcheck_timer; 702 int hangcheck_count; 703 uint32_t last_acthd[I915_NUM_RINGS]; 704 uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; 705 706 unsigned int stop_rings; 707 708 unsigned long cfb_size; 709 unsigned int cfb_fb; 710 enum plane cfb_plane; 711 int cfb_y; 712 struct intel_fbc_work *fbc_work; 713 714 struct intel_opregion opregion; 715 716 /* overlay */ 717 struct intel_overlay *overlay; 718 bool sprite_scaling_enabled; 719 720 /* LVDS info */ 721 int backlight_level; /* restore backlight to this value */ 722 bool backlight_enabled; 723 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 724 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 725 726 /* Feature bits from the VBIOS */ 727 unsigned int int_tv_support:1; 728 unsigned int lvds_dither:1; 729 unsigned int lvds_vbt:1; 730 unsigned int int_crt_support:1; 731 unsigned int lvds_use_ssc:1; 732 unsigned int display_clock_mode:1; 733 int lvds_ssc_freq; 734 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 735 unsigned int lvds_val; /* used for checking LVDS channel mode */ 736 struct { 737 int rate; 738 int lanes; 739 int preemphasis; 740 int vswing; 741 742 bool initialized; 743 bool support; 744 int bpp; 745 struct edp_power_seq pps; 746 } edp; 747 bool no_aux_handshake; 748 749 int crt_ddc_pin; 750 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 751 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 752 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 753 754 unsigned int fsb_freq, mem_freq, is_ddr3; 755 756 spinlock_t error_lock; 757 /* Protected by dev->error_lock. */ 758 struct drm_i915_error_state *first_error; 759 struct work_struct error_work; 760 struct completion error_completion; 761 struct workqueue_struct *wq; 762 763 /* Display functions */ 764 struct drm_i915_display_funcs display; 765 766 /* PCH chipset type */ 767 enum intel_pch pch_type; 768 unsigned short pch_id; 769 770 unsigned long quirks; 771 772 /* Register state */ 773 bool modeset_on_lid; 774 775 struct { 776 /** Bridge to intel-gtt-ko */ 777 struct intel_gtt *gtt; 778 /** Memory allocator for GTT stolen memory */ 779 struct drm_mm stolen; 780 /** Memory allocator for GTT */ 781 struct drm_mm gtt_space; 782 /** List of all objects in gtt_space. Used to restore gtt 783 * mappings on resume */ 784 struct list_head bound_list; 785 /** 786 * List of objects which are not bound to the GTT (thus 787 * are idle and not used by the GPU) but still have 788 * (presumably uncached) pages still attached. 789 */ 790 struct list_head unbound_list; 791 792 /** Usable portion of the GTT for GEM */ 793 unsigned long gtt_start; 794 unsigned long gtt_mappable_end; 795 unsigned long gtt_end; 796 797 struct io_mapping *gtt_mapping; 798 phys_addr_t gtt_base_addr; 799 int gtt_mtrr; 800 801 /** PPGTT used for aliasing the PPGTT with the GTT */ 802 struct i915_hw_ppgtt *aliasing_ppgtt; 803 804 struct shrinker inactive_shrinker; 805 bool shrinker_no_lock_stealing; 806 807 /** 808 * List of objects currently involved in rendering. 809 * 810 * Includes buffers having the contents of their GPU caches 811 * flushed, not necessarily primitives. last_rendering_seqno 812 * represents when the rendering involved will be completed. 813 * 814 * A reference is held on the buffer while on this list. 815 */ 816 struct list_head active_list; 817 818 /** 819 * LRU list of objects which are not in the ringbuffer and 820 * are ready to unbind, but are still in the GTT. 821 * 822 * last_rendering_seqno is 0 while an object is in this list. 823 * 824 * A reference is not held on the buffer while on this list, 825 * as merely being GTT-bound shouldn't prevent its being 826 * freed, and we'll pull it off the list in the free path. 827 */ 828 struct list_head inactive_list; 829 830 /** LRU list of objects with fence regs on them. */ 831 struct list_head fence_list; 832 833 /** 834 * We leave the user IRQ off as much as possible, 835 * but this means that requests will finish and never 836 * be retired once the system goes idle. Set a timer to 837 * fire periodically while the ring is running. When it 838 * fires, go retire requests. 839 */ 840 struct delayed_work retire_work; 841 842 /** 843 * Are we in a non-interruptible section of code like 844 * modesetting? 845 */ 846 bool interruptible; 847 848 /** 849 * Flag if the X Server, and thus DRM, is not currently in 850 * control of the device. 851 * 852 * This is set between LeaveVT and EnterVT. It needs to be 853 * replaced with a semaphore. It also needs to be 854 * transitioned away from for kernel modesetting. 855 */ 856 int suspended; 857 858 /** 859 * Flag if the hardware appears to be wedged. 860 * 861 * This is set when attempts to idle the device timeout. 862 * It prevents command submission from occurring and makes 863 * every pending request fail 864 */ 865 atomic_t wedged; 866 867 /** Bit 6 swizzling required for X tiling */ 868 uint32_t bit_6_swizzle_x; 869 /** Bit 6 swizzling required for Y tiling */ 870 uint32_t bit_6_swizzle_y; 871 872 /* storage for physical objects */ 873 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 874 875 /* accounting, useful for userland debugging */ 876 size_t gtt_total; 877 size_t mappable_gtt_total; 878 size_t object_memory; 879 u32 object_count; 880 } mm; 881 882 /* Kernel Modesetting */ 883 884 struct sdvo_device_mapping sdvo_mappings[2]; 885 /* indicate whether the LVDS_BORDER should be enabled or not */ 886 unsigned int lvds_border_bits; 887 /* Panel fitter placement and size for Ironlake+ */ 888 u32 pch_pf_pos, pch_pf_size; 889 890 struct drm_crtc *plane_to_crtc_mapping[3]; 891 struct drm_crtc *pipe_to_crtc_mapping[3]; 892 #ifdef __NetBSD__ 893 /* XXX The locking scheme looks broken. This mutex is a stop-gap. */ 894 struct spinlock pending_flip_lock; 895 drm_waitqueue_t pending_flip_queue; 896 #else 897 wait_queue_head_t pending_flip_queue; 898 #endif 899 900 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 901 struct intel_ddi_plls ddi_plls; 902 903 /* Reclocking support */ 904 bool render_reclock_avail; 905 bool lvds_downclock_avail; 906 /* indicates the reduced downclock for LVDS*/ 907 int lvds_downclock; 908 u16 orig_clock; 909 int child_dev_num; 910 struct child_device_config *child_dev; 911 912 bool mchbar_need_disable; 913 914 struct intel_l3_parity l3_parity; 915 916 /* gen6+ rps state */ 917 struct intel_gen6_power_mgmt rps; 918 919 /* ilk-only ips/rps state. Everything in here is protected by the global 920 * mchdev_lock in intel_pm.c */ 921 struct intel_ilk_power_mgmt ips; 922 923 enum no_fbc_reason no_fbc_reason; 924 925 struct drm_mm_node *compressed_fb; 926 struct drm_mm_node *compressed_llb; 927 928 #ifdef __NetBSD__ 929 time_t last_gpu_reset; 930 #else 931 unsigned long last_gpu_reset; 932 #endif 933 934 /* list of fbdev register on this device */ 935 struct intel_fbdev *fbdev; 936 937 /* 938 * The console may be contended at resume, but we don't 939 * want it to block on it. 940 */ 941 struct work_struct console_resume_work; 942 943 struct backlight_device *backlight; 944 945 struct drm_property *broadcast_rgb_property; 946 struct drm_property *force_audio_property; 947 948 bool hw_contexts_disabled; 949 uint32_t hw_context_size; 950 951 bool fdi_rx_polarity_reversed; 952 953 struct i915_suspend_saved_registers regfile; 954 955 /* Old dri1 support infrastructure, beware the dragons ya fools entering 956 * here! */ 957 struct i915_dri1_state dri1; 958 } drm_i915_private_t; 959 960 /* Iterate over initialised rings */ 961 #define for_each_ring(ring__, dev_priv__, i__) \ 962 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 963 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 964 965 enum hdmi_force_audio { 966 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 967 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 968 HDMI_AUDIO_AUTO, /* trust EDID */ 969 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 970 }; 971 972 enum i915_cache_level { 973 I915_CACHE_NONE = 0, 974 I915_CACHE_LLC, 975 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ 976 }; 977 978 struct drm_i915_gem_object_ops { 979 /* Interface between the GEM object and its backing storage. 980 * get_pages() is called once prior to the use of the associated set 981 * of pages before to binding them into the GTT, and put_pages() is 982 * called after we no longer need them. As we expect there to be 983 * associated cost with migrating pages between the backing storage 984 * and making them available for the GPU (e.g. clflush), we may hold 985 * onto the pages after they are no longer referenced by the GPU 986 * in case they may be used again shortly (for example migrating the 987 * pages to a different memory domain within the GTT). put_pages() 988 * will therefore most likely be called when the object itself is 989 * being released or under memory pressure (where we attempt to 990 * reap pages for the shrinker). 991 */ 992 int (*get_pages)(struct drm_i915_gem_object *); 993 void (*put_pages)(struct drm_i915_gem_object *); 994 }; 995 996 struct drm_i915_gem_object { 997 struct drm_gem_object base; 998 999 const struct drm_i915_gem_object_ops *ops; 1000 1001 /** Current space allocated to this object in the GTT, if any. */ 1002 struct drm_mm_node *gtt_space; 1003 struct list_head gtt_list; 1004 1005 /** This object's place on the active/inactive lists */ 1006 struct list_head ring_list; 1007 struct list_head mm_list; 1008 /** This object's place in the batchbuffer or on the eviction list */ 1009 struct list_head exec_list; 1010 1011 /** 1012 * This is set if the object is on the active lists (has pending 1013 * rendering and so a non-zero seqno), and is not set if it i s on 1014 * inactive (ready to be unbound) list. 1015 */ 1016 unsigned int active:1; 1017 1018 /** 1019 * This is set if the object has been written to since last bound 1020 * to the GTT 1021 */ 1022 unsigned int dirty:1; 1023 1024 /** 1025 * Fence register bits (if any) for this object. Will be set 1026 * as needed when mapped into the GTT. 1027 * Protected by dev->struct_mutex. 1028 */ 1029 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1030 1031 /** 1032 * Advice: are the backing pages purgeable? 1033 */ 1034 unsigned int madv:2; 1035 1036 /** 1037 * Current tiling mode for the object. 1038 */ 1039 unsigned int tiling_mode:2; 1040 /** 1041 * Whether the tiling parameters for the currently associated fence 1042 * register have changed. Note that for the purposes of tracking 1043 * tiling changes we also treat the unfenced register, the register 1044 * slot that the object occupies whilst it executes a fenced 1045 * command (such as BLT on gen2/3), as a "fence". 1046 */ 1047 unsigned int fence_dirty:1; 1048 1049 /** How many users have pinned this object in GTT space. The following 1050 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1051 * (via user_pin_count), execbuffer (objects are not allowed multiple 1052 * times for the same batchbuffer), and the framebuffer code. When 1053 * switching/pageflipping, the framebuffer code has at most two buffers 1054 * pinned per crtc. 1055 * 1056 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1057 * bits with absolutely no headroom. So use 4 bits. */ 1058 unsigned int pin_count:4; 1059 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1060 1061 /** 1062 * Is the object at the current location in the gtt mappable and 1063 * fenceable? Used to avoid costly recalculations. 1064 */ 1065 unsigned int map_and_fenceable:1; 1066 1067 /** 1068 * Whether the current gtt mapping needs to be mappable (and isn't just 1069 * mappable by accident). Track pin and fault separate for a more 1070 * accurate mappable working set. 1071 */ 1072 unsigned int fault_mappable:1; 1073 unsigned int pin_mappable:1; 1074 1075 /* 1076 * Is the GPU currently using a fence to access this buffer, 1077 */ 1078 unsigned int pending_fenced_gpu_access:1; 1079 unsigned int fenced_gpu_access:1; 1080 1081 unsigned int cache_level:2; 1082 1083 unsigned int has_aliasing_ppgtt_mapping:1; 1084 unsigned int has_global_gtt_mapping:1; 1085 unsigned int has_dma_mapping:1; 1086 1087 #ifdef __NetBSD__ 1088 struct pglist igo_pageq; 1089 bus_dma_segment_t *pages; /* `pages' is an expedient misnomer. */ 1090 int igo_nsegs; 1091 bus_dmamap_t igo_dmamap; 1092 #else 1093 struct sg_table *pages; 1094 #endif 1095 int pages_pin_count; 1096 1097 /* prime dma-buf support */ 1098 void *dma_buf_vmapping; 1099 int vmapping_count; 1100 1101 /** 1102 * Used for performing relocations during execbuffer insertion. 1103 */ 1104 struct hlist_node exec_node; 1105 unsigned long exec_handle; 1106 struct drm_i915_gem_exec_object2 *exec_entry; 1107 1108 /** 1109 * Current offset of the object in GTT space. 1110 * 1111 * This is the same as gtt_space->start 1112 */ 1113 uint32_t gtt_offset; 1114 1115 struct intel_ring_buffer *ring; 1116 1117 /** Breadcrumb of last rendering to the buffer. */ 1118 uint32_t last_read_seqno; 1119 uint32_t last_write_seqno; 1120 /** Breadcrumb of last fenced GPU access to the buffer. */ 1121 uint32_t last_fenced_seqno; 1122 1123 /** Current tiling stride for the object, if it's tiled. */ 1124 uint32_t stride; 1125 1126 /** Record of address bit 17 of each page at last unbind. */ 1127 unsigned long *bit_17; 1128 1129 /** User space pin count and filp owning the pin */ 1130 uint32_t user_pin_count; 1131 struct drm_file *pin_filp; 1132 1133 /** for phy allocated objects */ 1134 struct drm_i915_gem_phys_object *phys_obj; 1135 1136 /** 1137 * Number of crtcs where this object is currently the fb, but 1138 * will be page flipped away on the next vblank. When it 1139 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1140 */ 1141 atomic_t pending_flip; 1142 }; 1143 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1144 1145 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1146 1147 /** 1148 * Request queue structure. 1149 * 1150 * The request queue allows us to note sequence numbers that have been emitted 1151 * and may be associated with active buffers to be retired. 1152 * 1153 * By keeping this list, we can avoid having to do questionable 1154 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1155 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1156 */ 1157 struct drm_i915_gem_request { 1158 /** On Which ring this request was generated */ 1159 struct intel_ring_buffer *ring; 1160 1161 /** GEM sequence number associated with this request. */ 1162 uint32_t seqno; 1163 1164 /** Postion in the ringbuffer of the end of the request */ 1165 u32 tail; 1166 1167 /** Time at which this request was emitted, in jiffies. */ 1168 unsigned long emitted_jiffies; 1169 1170 /** global list entry for this request */ 1171 struct list_head list; 1172 1173 struct drm_i915_file_private *file_priv; 1174 /** file_priv list entry for this request */ 1175 struct list_head client_list; 1176 }; 1177 1178 struct drm_i915_file_private { 1179 struct { 1180 struct spinlock lock; 1181 struct list_head request_list; 1182 } mm; 1183 struct idr context_idr; 1184 }; 1185 1186 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1187 1188 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1189 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1190 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1191 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1192 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1193 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1194 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1195 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1196 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1197 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1198 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1199 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1200 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1201 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1202 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1203 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1204 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1205 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1206 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1207 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1208 (dev)->pci_device == 0x0152 || \ 1209 (dev)->pci_device == 0x015a) 1210 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1211 (dev)->pci_device == 0x0106 || \ 1212 (dev)->pci_device == 0x010A) 1213 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1214 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1215 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1216 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1217 ((dev)->pci_device & 0xFF00) == 0x0A00) 1218 1219 /* 1220 * The genX designation typically refers to the render engine, so render 1221 * capability related checks should use IS_GEN, while display and other checks 1222 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1223 * chips, etc.). 1224 */ 1225 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1226 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1227 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1228 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1229 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1230 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1231 1232 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1233 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1234 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1235 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1236 1237 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1238 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1239 1240 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1241 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1242 1243 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1244 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1245 1246 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1247 * rows, which changed the alignment requirements and fence programming. 1248 */ 1249 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1250 IS_I915GM(dev))) 1251 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1252 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1253 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1254 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1255 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1256 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1257 /* dsparb controlled by hw only */ 1258 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1259 1260 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1261 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1262 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1263 1264 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1265 1266 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1267 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1268 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1269 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1270 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1271 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1272 1273 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1274 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1275 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1276 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1277 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1278 1279 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1280 1281 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1282 1283 #define GT_FREQUENCY_MULTIPLIER 50 1284 1285 #include "i915_trace.h" 1286 1287 /** 1288 * RC6 is a special power stage which allows the GPU to enter an very 1289 * low-voltage mode when idle, using down to 0V while at this stage. This 1290 * stage is entered automatically when the GPU is idle when RC6 support is 1291 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1292 * 1293 * There are different RC6 modes available in Intel GPU, which differentiate 1294 * among each other with the latency required to enter and leave RC6 and 1295 * voltage consumed by the GPU in different states. 1296 * 1297 * The combination of the following flags define which states GPU is allowed 1298 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1299 * RC6pp is deepest RC6. Their support by hardware varies according to the 1300 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1301 * which brings the most power savings; deeper states save more power, but 1302 * require higher latency to switch to and wake up. 1303 */ 1304 #define INTEL_RC6_ENABLE (1<<0) 1305 #define INTEL_RC6p_ENABLE (1<<1) 1306 #define INTEL_RC6pp_ENABLE (1<<2) 1307 1308 extern struct drm_ioctl_desc i915_ioctls[]; 1309 extern int i915_max_ioctl; 1310 extern unsigned int i915_fbpercrtc __always_unused; 1311 extern int i915_panel_ignore_lid __read_mostly; 1312 extern unsigned int i915_powersave __read_mostly; 1313 extern int i915_semaphores __read_mostly; 1314 extern unsigned int i915_lvds_downclock __read_mostly; 1315 extern int i915_lvds_channel_mode __read_mostly; 1316 extern int i915_panel_use_ssc __read_mostly; 1317 extern int i915_vbt_sdvo_panel_type __read_mostly; 1318 extern int i915_enable_rc6 __read_mostly; 1319 extern int i915_enable_fbc __read_mostly; 1320 extern bool i915_enable_hangcheck __read_mostly; 1321 extern int i915_enable_ppgtt __read_mostly; 1322 extern unsigned int i915_preliminary_hw_support __read_mostly; 1323 1324 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1325 extern int i915_resume(struct drm_device *dev); 1326 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1327 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1328 1329 /* i915_dma.c */ 1330 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1331 extern void i915_kernel_lost_context(struct drm_device * dev); 1332 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1333 extern int i915_driver_unload(struct drm_device *); 1334 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1335 extern void i915_driver_lastclose(struct drm_device * dev); 1336 extern void i915_driver_preclose(struct drm_device *dev, 1337 struct drm_file *file_priv); 1338 extern void i915_driver_postclose(struct drm_device *dev, 1339 struct drm_file *file_priv); 1340 extern int i915_driver_device_is_agp(struct drm_device * dev); 1341 #ifdef CONFIG_COMPAT 1342 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1343 unsigned long arg); 1344 #endif 1345 extern int i915_emit_box(struct drm_device *dev, 1346 struct drm_clip_rect *box, 1347 int DR1, int DR4); 1348 extern int intel_gpu_reset(struct drm_device *dev); 1349 extern int i915_reset(struct drm_device *dev); 1350 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1351 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1352 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1353 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1354 1355 extern void intel_console_resume(struct work_struct *work); 1356 1357 /* i915_irq.c */ 1358 void i915_hangcheck_elapsed(unsigned long data); 1359 void i915_handle_error(struct drm_device *dev, bool wedged); 1360 1361 extern void intel_irq_init(struct drm_device *dev); 1362 extern void intel_gt_init(struct drm_device *dev); 1363 #ifdef __NetBSD__ /* XXX gt fini */ 1364 extern void intel_gt_fini(struct drm_device *dev); 1365 #endif 1366 extern void intel_gt_reset(struct drm_device *dev); 1367 1368 void i915_error_state_free(struct kref *error_ref); 1369 1370 void 1371 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1372 1373 void 1374 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1375 1376 void intel_enable_asle(struct drm_device *dev); 1377 1378 #ifdef CONFIG_DEBUG_FS 1379 extern void i915_destroy_error_state(struct drm_device *dev); 1380 #else 1381 #define i915_destroy_error_state(x) 1382 #endif 1383 1384 1385 /* i915_gem.c */ 1386 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1387 struct drm_file *file_priv); 1388 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1389 struct drm_file *file_priv); 1390 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1391 struct drm_file *file_priv); 1392 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1393 struct drm_file *file_priv); 1394 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1395 struct drm_file *file_priv); 1396 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1397 struct drm_file *file_priv); 1398 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1399 struct drm_file *file_priv); 1400 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1401 struct drm_file *file_priv); 1402 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1403 struct drm_file *file_priv); 1404 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1405 struct drm_file *file_priv); 1406 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1407 struct drm_file *file_priv); 1408 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1409 struct drm_file *file_priv); 1410 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1411 struct drm_file *file_priv); 1412 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1413 struct drm_file *file); 1414 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1415 struct drm_file *file); 1416 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1417 struct drm_file *file_priv); 1418 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1419 struct drm_file *file_priv); 1420 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1421 struct drm_file *file_priv); 1422 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1423 struct drm_file *file_priv); 1424 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1425 struct drm_file *file_priv); 1426 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1427 struct drm_file *file_priv); 1428 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1429 struct drm_file *file_priv); 1430 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1431 struct drm_file *file_priv); 1432 void i915_gem_load(struct drm_device *dev); 1433 int i915_gem_init_object(struct drm_gem_object *obj); 1434 void i915_gem_object_init(struct drm_i915_gem_object *obj, 1435 const struct drm_i915_gem_object_ops *ops); 1436 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1437 size_t size); 1438 void i915_gem_free_object(struct drm_gem_object *obj); 1439 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1440 uint32_t alignment, 1441 bool map_and_fenceable, 1442 bool nonblocking); 1443 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1444 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1445 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1446 void i915_gem_lastclose(struct drm_device *dev); 1447 1448 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 1449 #ifdef __NetBSD__ /* XXX */ 1450 static inline struct page * 1451 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 1452 { 1453 1454 /* 1455 * Pages must be pinned so that we need not hold the lock to 1456 * prevent them from disappearing. 1457 */ 1458 KASSERT(obj->pages != NULL); 1459 mutex_enter(obj->base.gemo_shm_uao->vmobjlock); 1460 struct vm_page *const page = uvm_pagelookup(obj->base.gemo_shm_uao, 1461 ptoa(n)); 1462 mutex_exit(obj->base.gemo_shm_uao->vmobjlock); 1463 1464 return container_of(page, struct page, p_vmp); 1465 } 1466 #else 1467 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 1468 { 1469 struct scatterlist *sg = obj->pages->sgl; 1470 int nents = obj->pages->nents; 1471 while (nents > SG_MAX_SINGLE_ALLOC) { 1472 if (n < SG_MAX_SINGLE_ALLOC - 1) 1473 break; 1474 1475 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); 1476 n -= SG_MAX_SINGLE_ALLOC - 1; 1477 nents -= SG_MAX_SINGLE_ALLOC - 1; 1478 } 1479 return sg_page(sg+n); 1480 } 1481 #endif 1482 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1483 { 1484 BUG_ON(obj->pages == NULL); 1485 obj->pages_pin_count++; 1486 } 1487 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1488 { 1489 BUG_ON(obj->pages_pin_count == 0); 1490 obj->pages_pin_count--; 1491 } 1492 1493 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1494 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1495 struct intel_ring_buffer *to); 1496 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1497 struct intel_ring_buffer *ring); 1498 1499 int i915_gem_dumb_create(struct drm_file *file_priv, 1500 struct drm_device *dev, 1501 struct drm_mode_create_dumb *args); 1502 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1503 uint32_t handle, uint64_t *offset); 1504 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1505 uint32_t handle); 1506 /** 1507 * Returns true if seq1 is later than seq2. 1508 */ 1509 static inline bool 1510 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1511 { 1512 return (int32_t)(seq1 - seq2) >= 0; 1513 } 1514 1515 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1516 1517 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1518 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1519 1520 static inline bool 1521 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1522 { 1523 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1524 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1525 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1526 return true; 1527 } else 1528 return false; 1529 } 1530 1531 static inline void 1532 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1533 { 1534 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1535 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1536 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1537 } 1538 } 1539 1540 void i915_gem_retire_requests(struct drm_device *dev); 1541 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1542 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, 1543 bool interruptible); 1544 1545 void i915_gem_reset(struct drm_device *dev); 1546 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1547 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1548 uint32_t read_domains, 1549 uint32_t write_domain); 1550 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1551 int __must_check i915_gem_init(struct drm_device *dev); 1552 int __must_check i915_gem_init_hw(struct drm_device *dev); 1553 void i915_gem_l3_remap(struct drm_device *dev); 1554 void i915_gem_init_swizzling(struct drm_device *dev); 1555 void i915_gem_init_ppgtt(struct drm_device *dev); 1556 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1557 int __must_check i915_gpu_idle(struct drm_device *dev); 1558 int __must_check i915_gem_idle(struct drm_device *dev); 1559 int i915_add_request(struct intel_ring_buffer *ring, 1560 struct drm_file *file, 1561 u32 *seqno); 1562 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1563 uint32_t seqno); 1564 #ifdef __NetBSD__ /* XXX */ 1565 int i915_gem_fault(struct uvm_faultinfo *, vaddr_t, struct vm_page **, 1566 int, int, vm_prot_t, int); 1567 #else 1568 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1569 #endif 1570 int __must_check 1571 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1572 bool write); 1573 int __must_check 1574 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1575 int __must_check 1576 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1577 u32 alignment, 1578 struct intel_ring_buffer *pipelined); 1579 int i915_gem_attach_phys_object(struct drm_device *dev, 1580 struct drm_i915_gem_object *obj, 1581 int id, 1582 int align); 1583 void i915_gem_detach_phys_object(struct drm_device *dev, 1584 struct drm_i915_gem_object *obj); 1585 void i915_gem_free_all_phys_object(struct drm_device *dev); 1586 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1587 1588 uint32_t 1589 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1590 uint32_t size, 1591 int tiling_mode); 1592 1593 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1594 enum i915_cache_level cache_level); 1595 1596 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1597 struct dma_buf *dma_buf); 1598 1599 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1600 struct drm_gem_object *gem_obj, int flags); 1601 1602 /* i915_gem_context.c */ 1603 void i915_gem_context_init(struct drm_device *dev); 1604 void i915_gem_context_fini(struct drm_device *dev); 1605 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1606 int i915_switch_context(struct intel_ring_buffer *ring, 1607 struct drm_file *file, int to_id); 1608 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1609 struct drm_file *file); 1610 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1611 struct drm_file *file); 1612 1613 /* i915_gem_gtt.c */ 1614 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1615 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1616 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1617 struct drm_i915_gem_object *obj, 1618 enum i915_cache_level cache_level); 1619 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1620 struct drm_i915_gem_object *obj); 1621 1622 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1623 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1624 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1625 enum i915_cache_level cache_level); 1626 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1627 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1628 void i915_gem_init_global_gtt(struct drm_device *dev, 1629 unsigned long start, 1630 unsigned long mappable_end, 1631 unsigned long end); 1632 #ifdef __NetBSD__ /* XXX fini global gtt */ 1633 void i915_gem_fini_global_gtt(struct drm_device *dev); 1634 #endif 1635 int i915_gem_gtt_init(struct drm_device *dev); 1636 void i915_gem_gtt_fini(struct drm_device *dev); 1637 static inline void i915_gem_chipset_flush(struct drm_device *dev) 1638 { 1639 if (INTEL_INFO(dev)->gen < 6) 1640 intel_gtt_chipset_flush(); 1641 } 1642 1643 1644 /* i915_gem_evict.c */ 1645 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1646 unsigned alignment, 1647 unsigned cache_level, 1648 bool mappable, 1649 bool nonblock); 1650 int i915_gem_evict_everything(struct drm_device *dev); 1651 1652 /* i915_gem_stolen.c */ 1653 int i915_gem_init_stolen(struct drm_device *dev); 1654 void i915_gem_cleanup_stolen(struct drm_device *dev); 1655 1656 /* i915_gem_tiling.c */ 1657 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1658 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1659 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1660 1661 /* i915_gem_debug.c */ 1662 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1663 const char *where, uint32_t mark); 1664 #if WATCH_LISTS 1665 int i915_verify_lists(struct drm_device *dev); 1666 #else 1667 #define i915_verify_lists(dev) 0 1668 #endif 1669 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1670 int handle); 1671 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1672 const char *where, uint32_t mark); 1673 1674 /* i915_debugfs.c */ 1675 int i915_debugfs_init(struct drm_minor *minor); 1676 void i915_debugfs_cleanup(struct drm_minor *minor); 1677 1678 /* i915_suspend.c */ 1679 extern int i915_save_state(struct drm_device *dev); 1680 extern int i915_restore_state(struct drm_device *dev); 1681 1682 /* i915_suspend.c */ 1683 extern int i915_save_state(struct drm_device *dev); 1684 extern int i915_restore_state(struct drm_device *dev); 1685 1686 /* i915_sysfs.c */ 1687 void i915_setup_sysfs(struct drm_device *dev_priv); 1688 void i915_teardown_sysfs(struct drm_device *dev_priv); 1689 1690 /* intel_i2c.c */ 1691 extern int intel_setup_gmbus(struct drm_device *dev); 1692 extern void intel_teardown_gmbus(struct drm_device *dev); 1693 #ifdef __NetBSD__ 1694 static inline bool intel_gmbus_is_port_valid(unsigned port) 1695 #else 1696 extern inline bool intel_gmbus_is_port_valid(unsigned port) 1697 #endif 1698 { 1699 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1700 } 1701 1702 extern struct i2c_adapter *intel_gmbus_get_adapter( 1703 struct drm_i915_private *dev_priv, unsigned port); 1704 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1705 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1706 #ifdef __NetBSD__ 1707 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1708 #else 1709 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1710 #endif 1711 { 1712 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1713 } 1714 extern void intel_i2c_reset(struct drm_device *dev); 1715 1716 /* intel_opregion.c */ 1717 extern int intel_opregion_setup(struct drm_device *dev); 1718 #ifdef CONFIG_ACPI 1719 extern void intel_opregion_init(struct drm_device *dev); 1720 extern void intel_opregion_fini(struct drm_device *dev); 1721 extern void intel_opregion_asle_intr(struct drm_device *dev); 1722 extern void intel_opregion_gse_intr(struct drm_device *dev); 1723 extern void intel_opregion_enable_asle(struct drm_device *dev); 1724 #else 1725 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1726 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1727 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1728 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1729 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1730 #endif 1731 1732 /* intel_acpi.c */ 1733 #ifdef CONFIG_ACPI 1734 extern void intel_register_dsm_handler(void); 1735 extern void intel_unregister_dsm_handler(void); 1736 #else 1737 static inline void intel_register_dsm_handler(void) { return; } 1738 static inline void intel_unregister_dsm_handler(void) { return; } 1739 #endif /* CONFIG_ACPI */ 1740 1741 /* modesetting */ 1742 extern void intel_modeset_init_hw(struct drm_device *dev); 1743 extern void intel_modeset_init(struct drm_device *dev); 1744 extern void intel_modeset_gem_init(struct drm_device *dev); 1745 extern void intel_modeset_cleanup(struct drm_device *dev); 1746 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1747 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 1748 bool force_restore); 1749 extern bool intel_fbc_enabled(struct drm_device *dev); 1750 extern void intel_disable_fbc(struct drm_device *dev); 1751 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1752 extern void intel_init_pch_refclk(struct drm_device *dev); 1753 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1754 extern void intel_detect_pch(struct drm_device *dev); 1755 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1756 extern int intel_enable_rc6(const struct drm_device *dev); 1757 1758 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1759 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1760 struct drm_file *file); 1761 1762 /* overlay */ 1763 #ifdef CONFIG_DEBUG_FS 1764 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1765 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1766 1767 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1768 extern void intel_display_print_error_state(struct seq_file *m, 1769 struct drm_device *dev, 1770 struct intel_display_error_state *error); 1771 #endif 1772 1773 /* On SNB platform, before reading ring registers forcewake bit 1774 * must be set to prevent GT core from power down and stale values being 1775 * returned. 1776 */ 1777 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1778 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1779 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1780 1781 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1782 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1783 1784 #define __i915_read(x, y) \ 1785 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1786 1787 __i915_read(8, b) 1788 __i915_read(16, w) 1789 __i915_read(32, l) 1790 __i915_read(64, q) 1791 #undef __i915_read 1792 1793 #define __i915_write(x, y) \ 1794 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1795 1796 __i915_write(8, b) 1797 __i915_write(16, w) 1798 __i915_write(32, l) 1799 __i915_write(64, q) 1800 #undef __i915_write 1801 1802 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1803 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1804 1805 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1806 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1807 #ifdef __NetBSD__ 1808 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->regs_map, (reg)) 1809 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->regs_map, (reg), (val)) 1810 #else 1811 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1812 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1813 #endif 1814 1815 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1816 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1817 #ifdef __NetBSD__ 1818 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->regs_map, (reg)) 1819 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->regs_map, (reg), (val)) 1820 #else 1821 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1822 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1823 #endif 1824 1825 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1826 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1827 1828 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1829 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1830 1831 1832 #endif 1833