1 /* $NetBSD: i915_drv.h,v 1.48 2022/09/22 14:37:38 riastradh Exp $ */ 2 3 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5 /* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sub license, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * 30 */ 31 32 #ifndef _I915_DRV_H_ 33 #define _I915_DRV_H_ 34 35 #if defined(__NetBSD__) 36 #ifdef _KERNEL_OPT 37 #include "acpica.h" 38 #endif /* _KERNEL_OPT */ 39 #if (NACPICA > 0) 40 #define CONFIG_ACPI 41 #endif /* NACPICA > 0 */ 42 #endif /* __NetBSD__ */ 43 44 #include <uapi/drm/i915_drm.h> 45 #include <uapi/drm/drm_fourcc.h> 46 47 #include <linux/io-mapping.h> 48 #include <linux/i2c.h> 49 #include <linux/i2c-algo-bit.h> 50 #include <linux/backlight.h> 51 #include <linux/hash.h> 52 #include <linux/intel-iommu.h> 53 #include <linux/kref.h> 54 #include <linux/mm_types.h> 55 #include <linux/perf_event.h> 56 #include <linux/pm_qos.h> 57 #include <linux/dma-resv.h> 58 #include <linux/shmem_fs.h> 59 #include <linux/stackdepot.h> 60 #include <linux/xarray.h> 61 #include <linux/uuid.h> 62 63 #include <drm/intel-gtt.h> 64 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 65 #include <drm/drm_gem.h> 66 #include <drm/drm_auth.h> 67 #include <drm/drm_cache.h> 68 #include <drm/drm_util.h> 69 #include <drm/drm_dsc.h> 70 #include <drm/drm_atomic.h> 71 #include <drm/drm_connector.h> 72 #include <drm/i915_mei_hdcp_interface.h> 73 74 #include "i915_fixed.h" 75 #include "i915_params.h" 76 #include "i915_reg.h" 77 #include "i915_utils.h" 78 79 #include "display/intel_bios.h" 80 #include "display/intel_display.h" 81 #include "display/intel_display_power.h" 82 #include "display/intel_dpll_mgr.h" 83 #include "display/intel_dsb.h" 84 #include "display/intel_frontbuffer.h" 85 #include "display/intel_gmbus.h" 86 #include "display/intel_opregion.h" 87 88 #include "gem/i915_gem_context_types.h" 89 #include "gem/i915_gem_shrinker.h" 90 #include "gem/i915_gem_stolen.h" 91 92 #include "gt/intel_lrc.h" 93 #include "gt/intel_engine.h" 94 #include "gt/intel_gt_types.h" 95 #include "gt/intel_workarounds.h" 96 #include "gt/uc/intel_uc.h" 97 98 #include "intel_device_info.h" 99 #include "intel_pch.h" 100 #include "intel_runtime_pm.h" 101 #include "intel_memory_region.h" 102 #include "intel_uncore.h" 103 #include "intel_wakeref.h" 104 #include "intel_wopcm.h" 105 106 #include "i915_gem.h" 107 #include "i915_gem_fence_reg.h" 108 #include "i915_gem_gtt.h" 109 #include "i915_gpu_error.h" 110 #include "i915_perf_types.h" 111 #include "i915_request.h" 112 #include "i915_scheduler.h" 113 #include "gt/intel_timeline.h" 114 #include "i915_vma.h" 115 #include "i915_irq.h" 116 117 #include "intel_region_lmem.h" 118 119 #include "intel_gvt.h" 120 121 /* General customization: 122 */ 123 124 #define DRIVER_NAME "i915" 125 #define DRIVER_DESC "Intel Graphics" 126 #define DRIVER_DATE "20200114" 127 #define DRIVER_TIMESTAMP 1579001978 128 129 struct drm_i915_gem_object; 130 131 enum hpd_pin { 132 HPD_NONE = 0, 133 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 134 HPD_CRT, 135 HPD_SDVO_B, 136 HPD_SDVO_C, 137 HPD_PORT_A, 138 HPD_PORT_B, 139 HPD_PORT_C, 140 HPD_PORT_D, 141 HPD_PORT_E, 142 HPD_PORT_F, 143 HPD_PORT_G, 144 HPD_PORT_H, 145 HPD_PORT_I, 146 147 HPD_NUM_PINS 148 }; 149 150 #define for_each_hpd_pin(__pin) \ 151 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 152 153 /* Threshold == 5 for long IRQs, 50 for short */ 154 #define HPD_STORM_DEFAULT_THRESHOLD 50 155 156 struct i915_hotplug { 157 struct delayed_work hotplug_work; 158 159 struct { 160 unsigned long last_jiffies; 161 int count; 162 enum { 163 HPD_ENABLED = 0, 164 HPD_DISABLED = 1, 165 HPD_MARK_DISABLED = 2 166 } state; 167 } stats[HPD_NUM_PINS]; 168 u32 event_bits; 169 u32 retry_bits; 170 struct delayed_work reenable_work; 171 172 u32 long_port_mask; 173 u32 short_port_mask; 174 struct work_struct dig_port_work; 175 176 struct work_struct poll_init_work; 177 bool poll_enabled; 178 179 unsigned int hpd_storm_threshold; 180 /* Whether or not to count short HPD IRQs in HPD storms */ 181 u8 hpd_short_storm_enabled; 182 183 /* 184 * if we get a HPD irq from DP and a HPD irq from non-DP 185 * the non-DP HPD could block the workqueue on a mode config 186 * mutex getting, that userspace may have taken. However 187 * userspace is waiting on the DP workqueue to run which is 188 * blocked behind the non-DP one. 189 */ 190 struct workqueue_struct *dp_wq; 191 }; 192 193 #define I915_GEM_GPU_DOMAINS \ 194 (I915_GEM_DOMAIN_RENDER | \ 195 I915_GEM_DOMAIN_SAMPLER | \ 196 I915_GEM_DOMAIN_COMMAND | \ 197 I915_GEM_DOMAIN_INSTRUCTION | \ 198 I915_GEM_DOMAIN_VERTEX) 199 200 struct drm_i915_private; 201 struct i915_mm_struct; 202 struct i915_mmu_object; 203 204 struct drm_i915_file_private { 205 struct drm_i915_private *dev_priv; 206 207 union { 208 struct drm_file *file; 209 struct rcu_head rcu; 210 }; 211 212 struct { 213 spinlock_t lock; 214 struct list_head request_list; 215 } mm; 216 217 struct xarray context_xa; 218 219 struct idr vm_idr; 220 struct mutex vm_idr_lock; /* guards vm_idr */ 221 222 unsigned int bsd_engine; 223 224 /* 225 * Every context ban increments per client ban score. Also 226 * hangs in short succession increments ban score. If ban threshold 227 * is reached, client is considered banned and submitting more work 228 * will fail. This is a stop gap measure to limit the badly behaving 229 * clients access to gpu. Note that unbannable contexts never increment 230 * the client ban score. 231 */ 232 #define I915_CLIENT_SCORE_HANG_FAST 1 233 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 234 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 235 #define I915_CLIENT_SCORE_BANNED 9 236 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 237 atomic_t ban_score; 238 unsigned long hang_timestamp; 239 }; 240 241 /* Interface history: 242 * 243 * 1.1: Original. 244 * 1.2: Add Power Management 245 * 1.3: Add vblank support 246 * 1.4: Fix cmdbuffer path, add heap destroy 247 * 1.5: Add vblank pipe configuration 248 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 249 * - Support vertical blank on secondary display pipe 250 */ 251 #define DRIVER_MAJOR 1 252 #define DRIVER_MINOR 6 253 #define DRIVER_PATCHLEVEL 0 254 255 struct intel_overlay; 256 struct intel_overlay_error_state; 257 258 struct sdvo_device_mapping { 259 u8 initialized; 260 u8 dvo_port; 261 u8 slave_addr; 262 u8 dvo_wiring; 263 u8 i2c_pin; 264 u8 ddc_pin; 265 }; 266 267 struct intel_connector; 268 struct intel_encoder; 269 struct intel_atomic_state; 270 struct intel_crtc_state; 271 struct intel_initial_plane_config; 272 struct intel_crtc; 273 struct intel_limit; 274 struct dpll; 275 struct intel_cdclk_state; 276 277 struct drm_i915_display_funcs { 278 void (*get_cdclk)(struct drm_i915_private *dev_priv, 279 struct intel_cdclk_state *cdclk_state); 280 void (*set_cdclk)(struct drm_i915_private *dev_priv, 281 const struct intel_cdclk_state *cdclk_state, 282 enum pipe pipe); 283 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 284 enum i9xx_plane_id i9xx_plane); 285 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 286 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 287 void (*initial_watermarks)(struct intel_atomic_state *state, 288 struct intel_crtc *crtc); 289 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 290 struct intel_crtc *crtc); 291 void (*optimize_watermarks)(struct intel_atomic_state *state, 292 struct intel_crtc *crtc); 293 int (*compute_global_watermarks)(struct intel_atomic_state *state); 294 void (*update_wm)(struct intel_crtc *crtc); 295 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 296 u8 (*calc_voltage_level)(int cdclk); 297 /* Returns the active state of the crtc, and if the crtc is active, 298 * fills out the pipe-config with the hw state. */ 299 bool (*get_pipe_config)(struct intel_crtc *, 300 struct intel_crtc_state *); 301 void (*get_initial_plane_config)(struct intel_crtc *, 302 struct intel_initial_plane_config *); 303 int (*crtc_compute_clock)(struct intel_crtc *crtc, 304 struct intel_crtc_state *crtc_state); 305 void (*crtc_enable)(struct intel_atomic_state *state, 306 struct intel_crtc *crtc); 307 void (*crtc_disable)(struct intel_atomic_state *state, 308 struct intel_crtc *crtc); 309 void (*commit_modeset_enables)(struct intel_atomic_state *state); 310 void (*commit_modeset_disables)(struct intel_atomic_state *state); 311 void (*audio_codec_enable)(struct intel_encoder *encoder, 312 const struct intel_crtc_state *crtc_state, 313 const struct drm_connector_state *conn_state); 314 void (*audio_codec_disable)(struct intel_encoder *encoder, 315 const struct intel_crtc_state *old_crtc_state, 316 const struct drm_connector_state *old_conn_state); 317 void (*fdi_link_train)(struct intel_crtc *crtc, 318 const struct intel_crtc_state *crtc_state); 319 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 320 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 321 /* clock updates for mode set */ 322 /* cursor updates */ 323 /* render clock increase/decrease */ 324 /* display clock increase/decrease */ 325 /* pll clock increase/decrease */ 326 327 int (*color_check)(struct intel_crtc_state *crtc_state); 328 /* 329 * Program double buffered color management registers during 330 * vblank evasion. The registers should then latch during the 331 * next vblank start, alongside any other double buffered registers 332 * involved with the same commit. 333 */ 334 void (*color_commit)(const struct intel_crtc_state *crtc_state); 335 /* 336 * Load LUTs (and other single buffered color management 337 * registers). Will (hopefully) be called during the vblank 338 * following the latching of any double buffered registers 339 * involved with the same commit. 340 */ 341 void (*load_luts)(const struct intel_crtc_state *crtc_state); 342 void (*read_luts)(struct intel_crtc_state *crtc_state); 343 }; 344 345 struct intel_csr { 346 struct work_struct work; 347 const char *fw_path; 348 u32 required_version; 349 u32 max_fw_size; /* bytes */ 350 u32 *dmc_payload; 351 u32 dmc_fw_size; /* dwords */ 352 u32 version; 353 u32 mmio_count; 354 i915_reg_t mmioaddr[20]; 355 u32 mmiodata[20]; 356 u32 dc_state; 357 u32 target_dc_state; 358 u32 allowed_dc_mask; 359 intel_wakeref_t wakeref; 360 }; 361 362 enum i915_cache_level { 363 I915_CACHE_NONE = 0, 364 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 365 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 366 caches, eg sampler/render caches, and the 367 large Last-Level-Cache. LLC is coherent with 368 the CPU, but L3 is only visible to the GPU. */ 369 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 370 }; 371 372 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 373 374 struct intel_fbc { 375 /* This is always the inner lock when overlapping with struct_mutex and 376 * it's the outer lock when overlapping with stolen_lock. */ 377 struct mutex lock; 378 unsigned threshold; 379 unsigned int possible_framebuffer_bits; 380 unsigned int busy_bits; 381 struct intel_crtc *crtc; 382 383 struct drm_mm_node compressed_fb; 384 struct drm_mm_node *compressed_llb; 385 386 bool false_color; 387 388 bool active; 389 bool activated; 390 bool flip_pending; 391 392 bool underrun_detected; 393 struct work_struct underrun_work; 394 395 /* 396 * Due to the atomic rules we can't access some structures without the 397 * appropriate locking, so we cache information here in order to avoid 398 * these problems. 399 */ 400 struct intel_fbc_state_cache { 401 struct { 402 unsigned int mode_flags; 403 u32 hsw_bdw_pixel_rate; 404 } crtc; 405 406 struct { 407 unsigned int rotation; 408 int src_w; 409 int src_h; 410 bool visible; 411 /* 412 * Display surface base address adjustement for 413 * pageflips. Note that on gen4+ this only adjusts up 414 * to a tile, offsets within a tile are handled in 415 * the hw itself (with the TILEOFF register). 416 */ 417 int adjusted_x; 418 int adjusted_y; 419 420 int y; 421 422 u16 pixel_blend_mode; 423 } plane; 424 425 struct { 426 const struct drm_format_info *format; 427 unsigned int stride; 428 } fb; 429 u16 gen9_wa_cfb_stride; 430 s8 fence_id; 431 } state_cache; 432 433 /* 434 * This structure contains everything that's relevant to program the 435 * hardware registers. When we want to figure out if we need to disable 436 * and re-enable FBC for a new configuration we just check if there's 437 * something different in the struct. The genx_fbc_activate functions 438 * are supposed to read from it in order to program the registers. 439 */ 440 struct intel_fbc_reg_params { 441 struct { 442 enum pipe pipe; 443 enum i9xx_plane_id i9xx_plane; 444 unsigned int fence_y_offset; 445 } crtc; 446 447 struct { 448 const struct drm_format_info *format; 449 unsigned int stride; 450 } fb; 451 452 int cfb_size; 453 u16 gen9_wa_cfb_stride; 454 s8 fence_id; 455 bool plane_visible; 456 } params; 457 458 const char *no_fbc_reason; 459 }; 460 461 /* 462 * HIGH_RR is the highest eDP panel refresh rate read from EDID 463 * LOW_RR is the lowest eDP panel refresh rate found from EDID 464 * parsing for same resolution. 465 */ 466 enum drrs_refresh_rate_type { 467 DRRS_HIGH_RR, 468 DRRS_LOW_RR, 469 DRRS_MAX_RR, /* RR count */ 470 }; 471 472 enum drrs_support_type { 473 DRRS_NOT_SUPPORTED = 0, 474 STATIC_DRRS_SUPPORT = 1, 475 SEAMLESS_DRRS_SUPPORT = 2 476 }; 477 478 struct intel_dp; 479 struct i915_drrs { 480 struct mutex mutex; 481 struct delayed_work work; 482 struct intel_dp *dp; 483 unsigned busy_frontbuffer_bits; 484 enum drrs_refresh_rate_type refresh_rate_type; 485 enum drrs_support_type type; 486 }; 487 488 struct i915_psr { 489 struct mutex lock; 490 491 #define I915_PSR_DEBUG_MODE_MASK 0x0f 492 #define I915_PSR_DEBUG_DEFAULT 0x00 493 #define I915_PSR_DEBUG_DISABLE 0x01 494 #define I915_PSR_DEBUG_ENABLE 0x02 495 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 496 #define I915_PSR_DEBUG_IRQ 0x10 497 498 u32 debug; 499 bool sink_support; 500 bool enabled; 501 struct intel_dp *dp; 502 enum pipe pipe; 503 enum transcoder transcoder; 504 bool active; 505 struct work_struct work; 506 unsigned busy_frontbuffer_bits; 507 bool sink_psr2_support; 508 bool link_standby; 509 bool colorimetry_support; 510 bool psr2_enabled; 511 u8 sink_sync_latency; 512 ktime_t last_entry_attempt; 513 ktime_t last_exit; 514 bool sink_not_reliable; 515 bool irq_aux_error; 516 u16 su_x_granularity; 517 bool dc3co_enabled; 518 u32 dc3co_exit_delay; 519 struct delayed_work idle_work; 520 bool initially_probed; 521 }; 522 523 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 524 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 525 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 526 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 527 #define QUIRK_INCREASE_T12_DELAY (1<<6) 528 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 529 530 #ifdef __NetBSD__ 531 /* NetBSD hack to note version was called and thus mmap flags valid. */ 532 #define QUIRK_NETBSD_VERSION_CALLED (1ul<<31) 533 #endif 534 535 struct intel_fbdev; 536 struct intel_fbc_work; 537 538 struct intel_gmbus { 539 struct i2c_adapter adapter; 540 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 541 u32 force_bit; 542 u32 reg0; 543 i915_reg_t gpio_reg; 544 struct i2c_algo_bit_data bit_algo; 545 struct drm_i915_private *dev_priv; 546 }; 547 548 struct i915_suspend_saved_registers { 549 u32 saveDSPARB; 550 u32 saveFBC_CONTROL; 551 u32 saveCACHE_MODE_0; 552 u32 saveMI_ARB_STATE; 553 u32 saveSWF0[16]; 554 u32 saveSWF1[16]; 555 u32 saveSWF3[3]; 556 u64 saveFENCE[I915_MAX_NUM_FENCES]; 557 u32 savePCH_PORT_HOTPLUG; 558 u16 saveGCDGMBUS; 559 }; 560 561 struct vlv_s0ix_state; 562 563 #define MAX_L3_SLICES 2 564 struct intel_l3_parity { 565 u32 *remap_info[MAX_L3_SLICES]; 566 struct work_struct error_work; 567 int which_slice; 568 }; 569 570 struct i915_gem_mm { 571 /** Memory allocator for GTT stolen memory */ 572 struct drm_mm stolen; 573 /** Protects the usage of the GTT stolen memory allocator. This is 574 * always the inner lock when overlapping with struct_mutex. */ 575 struct mutex stolen_lock; 576 577 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 578 spinlock_t obj_lock; 579 580 /** 581 * List of objects which are purgeable. 582 */ 583 struct list_head purge_list; 584 585 /** 586 * List of objects which have allocated pages and are shrinkable. 587 */ 588 struct list_head shrink_list; 589 590 /** 591 * List of objects which are pending destruction. 592 */ 593 struct llist_head free_list; 594 struct work_struct free_work; 595 /** 596 * Count of objects pending destructions. Used to skip needlessly 597 * waiting on an RCU barrier if no objects are waiting to be freed. 598 */ 599 atomic_t free_count; 600 601 /** 602 * Small stash of WC pages 603 */ 604 struct pagestash wc_stash; 605 606 /** 607 * tmpfs instance used for shmem backed objects 608 */ 609 struct vfsmount *gemfs; 610 611 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 612 613 struct notifier_block oom_notifier; 614 struct notifier_block vmap_notifier; 615 struct shrinker shrinker; 616 617 /** 618 * Workqueue to fault in userptr pages, flushed by the execbuf 619 * when required but otherwise left to userspace to try again 620 * on EAGAIN. 621 */ 622 struct workqueue_struct *userptr_wq; 623 624 /* shrinker accounting, also useful for userland debugging */ 625 u64 shrink_memory; 626 u32 shrink_count; 627 }; 628 629 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 630 631 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 632 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 633 634 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 635 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 636 637 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 638 639 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 640 #define I915_NUM_QGV_POINTS 8 641 642 struct ddi_vbt_port_info { 643 /* Non-NULL if port present. */ 644 const struct child_device_config *child; 645 646 int max_tmds_clock; 647 648 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 649 u8 hdmi_level_shift; 650 u8 hdmi_level_shift_set:1; 651 652 u8 supports_dvi:1; 653 u8 supports_hdmi:1; 654 u8 supports_dp:1; 655 u8 supports_edp:1; 656 u8 supports_typec_usb:1; 657 u8 supports_tbt:1; 658 659 u8 alternate_aux_channel; 660 u8 alternate_ddc_pin; 661 662 u8 dp_boost_level; 663 u8 hdmi_boost_level; 664 int dp_max_link_rate; /* 0 for not limited by VBT */ 665 }; 666 667 enum psr_lines_to_wait { 668 PSR_0_LINES_TO_WAIT = 0, 669 PSR_1_LINE_TO_WAIT, 670 PSR_4_LINES_TO_WAIT, 671 PSR_8_LINES_TO_WAIT 672 }; 673 674 struct intel_vbt_data { 675 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 676 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 677 678 /* Feature bits */ 679 unsigned int int_tv_support:1; 680 unsigned int lvds_dither:1; 681 unsigned int int_crt_support:1; 682 unsigned int lvds_use_ssc:1; 683 unsigned int int_lvds_support:1; 684 unsigned int display_clock_mode:1; 685 unsigned int fdi_rx_polarity_inverted:1; 686 unsigned int panel_type:4; 687 int lvds_ssc_freq; 688 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 689 enum drm_panel_orientation orientation; 690 691 enum drrs_support_type drrs_type; 692 693 struct { 694 int rate; 695 int lanes; 696 int preemphasis; 697 int vswing; 698 bool low_vswing; 699 bool initialized; 700 int bpp; 701 struct edp_power_seq pps; 702 } edp; 703 704 struct { 705 bool enable; 706 bool full_link; 707 bool require_aux_wakeup; 708 int idle_frames; 709 enum psr_lines_to_wait lines_to_wait; 710 int tp1_wakeup_time_us; 711 int tp2_tp3_wakeup_time_us; 712 int psr2_tp2_tp3_wakeup_time_us; 713 } psr; 714 715 struct { 716 u16 pwm_freq_hz; 717 bool present; 718 bool active_low_pwm; 719 u8 min_brightness; /* min_brightness/255 of max */ 720 u8 controller; /* brightness controller number */ 721 enum intel_backlight_type type; 722 } backlight; 723 724 /* MIPI DSI */ 725 struct { 726 u16 panel_id; 727 struct mipi_config *config; 728 struct mipi_pps_data *pps; 729 u16 bl_ports; 730 u16 cabc_ports; 731 u8 seq_version; 732 u32 size; 733 u8 *data; 734 const u8 *sequence[MIPI_SEQ_MAX]; 735 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 736 enum drm_panel_orientation orientation; 737 } dsi; 738 739 int crt_ddc_pin; 740 741 struct list_head display_devices; 742 743 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 744 struct sdvo_device_mapping sdvo_mappings[2]; 745 }; 746 747 enum intel_ddb_partitioning { 748 INTEL_DDB_PART_1_2, 749 INTEL_DDB_PART_5_6, /* IVB+ */ 750 }; 751 752 struct intel_wm_level { 753 bool enable; 754 u32 pri_val; 755 u32 spr_val; 756 u32 cur_val; 757 u32 fbc_val; 758 }; 759 760 struct ilk_wm_values { 761 u32 wm_pipe[3]; 762 u32 wm_lp[3]; 763 u32 wm_lp_spr[3]; 764 u32 wm_linetime[3]; 765 bool enable_fbc_wm; 766 enum intel_ddb_partitioning partitioning; 767 }; 768 769 struct g4x_pipe_wm { 770 u16 plane[I915_MAX_PLANES]; 771 u16 fbc; 772 }; 773 774 struct g4x_sr_wm { 775 u16 plane; 776 u16 cursor; 777 u16 fbc; 778 }; 779 780 struct vlv_wm_ddl_values { 781 u8 plane[I915_MAX_PLANES]; 782 }; 783 784 struct vlv_wm_values { 785 struct g4x_pipe_wm pipe[3]; 786 struct g4x_sr_wm sr; 787 struct vlv_wm_ddl_values ddl[3]; 788 u8 level; 789 bool cxsr; 790 }; 791 792 struct g4x_wm_values { 793 struct g4x_pipe_wm pipe[2]; 794 struct g4x_sr_wm sr; 795 struct g4x_sr_wm hpll; 796 bool cxsr; 797 bool hpll_en; 798 bool fbc_en; 799 }; 800 801 struct skl_ddb_entry { 802 u16 start, end; /* in number of blocks, 'end' is exclusive */ 803 }; 804 805 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 806 { 807 return entry->end - entry->start; 808 } 809 810 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 811 const struct skl_ddb_entry *e2) 812 { 813 if (e1->start == e2->start && e1->end == e2->end) 814 return true; 815 816 return false; 817 } 818 819 struct skl_ddb_allocation { 820 u8 enabled_slices; /* GEN11 has configurable 2 slices */ 821 }; 822 823 struct skl_ddb_values { 824 unsigned dirty_pipes; 825 struct skl_ddb_allocation ddb; 826 }; 827 828 struct skl_wm_level { 829 u16 min_ddb_alloc; 830 u16 plane_res_b; 831 u8 plane_res_l; 832 bool plane_en; 833 bool ignore_lines; 834 }; 835 836 /* Stores plane specific WM parameters */ 837 struct skl_wm_params { 838 bool x_tiled, y_tiled; 839 bool rc_surface; 840 bool is_planar; 841 u32 width; 842 u8 cpp; 843 u32 plane_pixel_rate; 844 u32 y_min_scanlines; 845 u32 plane_bytes_per_line; 846 uint_fixed_16_16_t plane_blocks_per_line; 847 uint_fixed_16_16_t y_tile_minimum; 848 u32 linetime_us; 849 u32 dbuf_block_size; 850 }; 851 852 enum intel_pipe_crc_source { 853 INTEL_PIPE_CRC_SOURCE_NONE, 854 INTEL_PIPE_CRC_SOURCE_PLANE1, 855 INTEL_PIPE_CRC_SOURCE_PLANE2, 856 INTEL_PIPE_CRC_SOURCE_PLANE3, 857 INTEL_PIPE_CRC_SOURCE_PLANE4, 858 INTEL_PIPE_CRC_SOURCE_PLANE5, 859 INTEL_PIPE_CRC_SOURCE_PLANE6, 860 INTEL_PIPE_CRC_SOURCE_PLANE7, 861 INTEL_PIPE_CRC_SOURCE_PIPE, 862 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 863 INTEL_PIPE_CRC_SOURCE_TV, 864 INTEL_PIPE_CRC_SOURCE_DP_B, 865 INTEL_PIPE_CRC_SOURCE_DP_C, 866 INTEL_PIPE_CRC_SOURCE_DP_D, 867 INTEL_PIPE_CRC_SOURCE_AUTO, 868 INTEL_PIPE_CRC_SOURCE_MAX, 869 }; 870 871 #define INTEL_PIPE_CRC_ENTRIES_NR 128 872 struct intel_pipe_crc { 873 spinlock_t lock; 874 int skipped; 875 enum intel_pipe_crc_source source; 876 }; 877 878 struct i915_frontbuffer_tracking { 879 spinlock_t lock; 880 881 /* 882 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 883 * scheduled flips. 884 */ 885 unsigned busy_bits; 886 unsigned flip_bits; 887 }; 888 889 struct i915_virtual_gpu { 890 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 891 bool active; 892 u32 caps; 893 }; 894 895 /* used in computing the new watermarks state */ 896 struct intel_wm_config { 897 unsigned int num_pipes_active; 898 bool sprites_enabled; 899 bool sprites_scaled; 900 }; 901 902 struct intel_cdclk_state { 903 unsigned int cdclk, vco, ref, bypass; 904 u8 voltage_level; 905 }; 906 907 struct i915_selftest_stash { 908 atomic_t counter; 909 }; 910 911 #ifdef __NetBSD__ 912 # define __i915_iomem 913 # define __iomem __i915_iomem 914 #endif 915 916 struct drm_i915_private { 917 struct drm_device drm; 918 919 struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 920 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 921 struct intel_driver_caps caps; 922 923 /** 924 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 925 * end of stolen which we can optionally use to create GEM objects 926 * backed by stolen memory. Note that stolen_usable_size tells us 927 * exactly how much of this we are actually allowed to use, given that 928 * some portion of it is in fact reserved for use by hardware functions. 929 */ 930 struct resource dsm; 931 /** 932 * Reseved portion of Data Stolen Memory 933 */ 934 struct resource dsm_reserved; 935 936 /* 937 * Stolen memory is segmented in hardware with different portions 938 * offlimits to certain functions. 939 * 940 * The drm_mm is initialised to the total accessible range, as found 941 * from the PCI config. On Broadwell+, this is further restricted to 942 * avoid the first page! The upper end of stolen memory is reserved for 943 * hardware functions and similarly removed from the accessible range. 944 */ 945 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 946 947 struct intel_uncore uncore; 948 struct intel_uncore_mmio_debug mmio_debug; 949 950 struct i915_virtual_gpu vgpu; 951 952 struct intel_gvt *gvt; 953 954 struct intel_wopcm wopcm; 955 956 struct intel_csr csr; 957 958 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 959 960 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 961 * controller on different i2c buses. */ 962 struct mutex gmbus_mutex; 963 964 /** 965 * Base address of where the gmbus and gpio blocks are located (either 966 * on PCH or on SoC for platforms without PCH). 967 */ 968 u32 gpio_mmio_base; 969 970 u32 hsw_psr_mmio_adjust; 971 972 /* MMIO base address for MIPI regs */ 973 u32 mipi_mmio_base; 974 975 u32 pps_mmio_base; 976 977 #ifdef __NetBSD__ 978 spinlock_t gmbus_wait_lock; 979 drm_waitqueue_t gmbus_wait_queue; 980 #else 981 wait_queue_head_t gmbus_wait_queue; 982 #endif 983 984 struct pci_dev *bridge_dev; 985 986 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 987 struct rb_root uabi_engines; 988 struct llist_head uabi_engines_llist; 989 990 struct resource mch_res; 991 992 /* protects the irq masks */ 993 spinlock_t irq_lock; 994 995 bool display_irqs_enabled; 996 997 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 998 struct pm_qos_request pm_qos; 999 1000 /* Sideband mailbox protection */ 1001 struct mutex sb_lock; 1002 struct pm_qos_request sb_qos; 1003 1004 /** Cached value of IMR to avoid reads in updating the bitfield */ 1005 union { 1006 u32 irq_mask; 1007 u32 de_irq_mask[I915_MAX_PIPES]; 1008 }; 1009 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1010 1011 struct i915_hotplug hotplug; 1012 struct intel_fbc fbc; 1013 struct i915_drrs drrs; 1014 struct intel_opregion opregion; 1015 struct intel_vbt_data vbt; 1016 1017 bool preserve_bios_swizzle; 1018 1019 /* overlay */ 1020 struct intel_overlay *overlay; 1021 1022 /* backlight registers and fields in struct intel_panel */ 1023 struct mutex backlight_lock; 1024 1025 /* protects panel power sequencer state */ 1026 struct mutex pps_mutex; 1027 1028 unsigned int fsb_freq, mem_freq, is_ddr3; 1029 unsigned int skl_preferred_vco_freq; 1030 unsigned int max_cdclk_freq; 1031 1032 unsigned int max_dotclk_freq; 1033 unsigned int rawclk_freq; 1034 unsigned int hpll_freq; 1035 unsigned int fdi_pll_freq; 1036 unsigned int czclk_freq; 1037 1038 /* 1039 * For reading holding any crtc lock is sufficient, 1040 * for writing must hold all of them. 1041 */ 1042 struct { 1043 /* 1044 * The current logical cdclk state. 1045 * See intel_atomic_state.cdclk.logical 1046 */ 1047 struct intel_cdclk_state logical; 1048 /* 1049 * The current actual cdclk state. 1050 * See intel_atomic_state.cdclk.actual 1051 */ 1052 struct intel_cdclk_state actual; 1053 /* The current hardware cdclk state */ 1054 struct intel_cdclk_state hw; 1055 1056 /* cdclk, divider, and ratio table from bspec */ 1057 const struct intel_cdclk_vals *table; 1058 1059 int force_min_cdclk; 1060 } cdclk; 1061 1062 /** 1063 * wq - Driver workqueue for GEM. 1064 * 1065 * NOTE: Work items scheduled here are not allowed to grab any modeset 1066 * locks, for otherwise the flushing done in the pageflip code will 1067 * result in deadlocks. 1068 */ 1069 struct workqueue_struct *wq; 1070 1071 /* ordered wq for modesets */ 1072 struct workqueue_struct *modeset_wq; 1073 /* unbound hipri wq for page flips/plane updates */ 1074 struct workqueue_struct *flip_wq; 1075 1076 /* Display functions */ 1077 struct drm_i915_display_funcs display; 1078 1079 /* PCH chipset type */ 1080 enum intel_pch pch_type; 1081 unsigned short pch_id; 1082 1083 unsigned long quirks; 1084 1085 struct drm_atomic_state *modeset_restore_state; 1086 struct drm_modeset_acquire_ctx reset_ctx; 1087 1088 spinlock_t atomic_commit_lock; 1089 drm_waitqueue_t atomic_commit_wq; 1090 1091 struct i915_ggtt ggtt; /* VM representing the global address space */ 1092 1093 struct i915_gem_mm mm; 1094 DECLARE_HASHTABLE(mm_structs, 7); 1095 struct mutex mm_lock; 1096 1097 /* Kernel Modesetting */ 1098 1099 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1100 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1101 1102 #ifdef CONFIG_DEBUG_FS 1103 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1104 #endif 1105 1106 /* dpll and cdclk state is protected by connection_mutex */ 1107 int num_shared_dpll; 1108 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1109 const struct intel_dpll_mgr *dpll_mgr; 1110 1111 /* 1112 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1113 * Must be global rather than per dpll, because on some platforms 1114 * plls share registers. 1115 */ 1116 struct mutex dpll_lock; 1117 1118 /* 1119 * For reading active_pipes, min_cdclk, min_voltage_level holding 1120 * any crtc lock is sufficient, for writing must hold all of them. 1121 */ 1122 u8 active_pipes; 1123 /* minimum acceptable cdclk for each pipe */ 1124 int min_cdclk[I915_MAX_PIPES]; 1125 /* minimum acceptable voltage level for each pipe */ 1126 u8 min_voltage_level[I915_MAX_PIPES]; 1127 1128 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1129 1130 struct i915_wa_list gt_wa_list; 1131 1132 struct i915_frontbuffer_tracking fb_tracking; 1133 1134 struct intel_atomic_helper { 1135 struct llist_head free_list; 1136 struct work_struct free_work; 1137 } atomic_helper; 1138 1139 u16 orig_clock; 1140 1141 bool mchbar_need_disable; 1142 1143 struct intel_l3_parity l3_parity; 1144 1145 /* 1146 * edram size in MB. 1147 * Cannot be determined by PCIID. You must always read a register. 1148 */ 1149 u32 edram_size_mb; 1150 1151 struct i915_power_domains power_domains; 1152 1153 struct i915_psr psr; 1154 1155 struct i915_gpu_error gpu_error; 1156 1157 struct drm_i915_gem_object *vlv_pctx; 1158 1159 /* list of fbdev register on this device */ 1160 struct intel_fbdev *fbdev; 1161 struct work_struct fbdev_suspend_work; 1162 1163 struct drm_property *broadcast_rgb_property; 1164 struct drm_property *force_audio_property; 1165 1166 /* hda/i915 audio component */ 1167 struct i915_audio_component *audio_component; 1168 bool audio_component_registered; 1169 /** 1170 * av_mutex - mutex for audio/video sync 1171 * 1172 */ 1173 struct mutex av_mutex; 1174 int audio_power_refcount; 1175 u32 audio_freq_cntrl; 1176 1177 u32 fdi_rx_config; 1178 1179 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1180 u32 chv_phy_control; 1181 /* 1182 * Shadows for CHV DPLL_MD regs to keep the state 1183 * checker somewhat working in the presence hardware 1184 * crappiness (can't read out DPLL_MD for pipes B & C). 1185 */ 1186 u32 chv_dpll_md[I915_MAX_PIPES]; 1187 u32 bxt_phy_grc; 1188 1189 u32 suspend_count; 1190 bool power_domains_suspended; 1191 struct i915_suspend_saved_registers regfile; 1192 struct vlv_s0ix_state *vlv_s0ix_state; 1193 1194 enum { 1195 I915_SAGV_UNKNOWN = 0, 1196 I915_SAGV_DISABLED, 1197 I915_SAGV_ENABLED, 1198 I915_SAGV_NOT_CONTROLLED 1199 } sagv_status; 1200 1201 u32 sagv_block_time_us; 1202 1203 struct { 1204 /* 1205 * Raw watermark latency values: 1206 * in 0.1us units for WM0, 1207 * in 0.5us units for WM1+. 1208 */ 1209 /* primary */ 1210 u16 pri_latency[5]; 1211 /* sprite */ 1212 u16 spr_latency[5]; 1213 /* cursor */ 1214 u16 cur_latency[5]; 1215 /* 1216 * Raw watermark memory latency values 1217 * for SKL for all 8 levels 1218 * in 1us units. 1219 */ 1220 u16 skl_latency[8]; 1221 1222 /* current hardware state */ 1223 union { 1224 struct ilk_wm_values hw; 1225 struct skl_ddb_values skl_hw; 1226 struct vlv_wm_values vlv; 1227 struct g4x_wm_values g4x; 1228 }; 1229 1230 u8 max_level; 1231 1232 /* 1233 * Should be held around atomic WM register writing; also 1234 * protects * intel_crtc->wm.active and 1235 * crtc_state->wm.need_postvbl_update. 1236 */ 1237 struct mutex wm_mutex; 1238 1239 /* 1240 * Set during HW readout of watermarks/DDB. Some platforms 1241 * need to know when we're still using BIOS-provided values 1242 * (which we don't fully trust). 1243 */ 1244 bool distrust_bios_wm; 1245 } wm; 1246 1247 struct dram_info { 1248 bool valid; 1249 bool is_16gb_dimm; 1250 u8 num_channels; 1251 u8 ranks; 1252 u32 bandwidth_kbps; 1253 bool symmetric_memory; 1254 enum intel_dram_type { 1255 INTEL_DRAM_UNKNOWN, 1256 INTEL_DRAM_DDR3, 1257 INTEL_DRAM_DDR4, 1258 INTEL_DRAM_LPDDR3, 1259 INTEL_DRAM_LPDDR4 1260 } type; 1261 } dram_info; 1262 1263 struct intel_bw_info { 1264 /* for each QGV point */ 1265 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1266 u8 num_qgv_points; 1267 u8 num_planes; 1268 } max_bw[6]; 1269 1270 struct drm_private_obj bw_obj; 1271 1272 struct intel_runtime_pm runtime_pm; 1273 1274 struct i915_perf perf; 1275 1276 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1277 struct intel_gt gt; 1278 1279 struct { 1280 struct i915_gem_contexts { 1281 spinlock_t lock; /* locks list */ 1282 struct list_head list; 1283 1284 struct llist_head free_list; 1285 struct work_struct free_work; 1286 } contexts; 1287 1288 /* 1289 * We replace the local file with a global mappings as the 1290 * backing storage for the mmap is on the device and not 1291 * on the struct file, and we do not want to prolong the 1292 * lifetime of the local fd. To minimise the number of 1293 * anonymous inodes we create, we use a global singleton to 1294 * share the global mapping. 1295 */ 1296 struct file *mmap_singleton; 1297 } gem; 1298 1299 u8 pch_ssc_use; 1300 1301 /* For i915gm/i945gm vblank irq workaround */ 1302 u8 vblank_enabled; 1303 1304 /* perform PHY state sanity checks? */ 1305 bool chv_phy_assert[2]; 1306 1307 bool ipc_enabled; 1308 1309 /* Used to save the pipe-to-encoder mapping for audio */ 1310 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1311 1312 /* necessary resource sharing with HDMI LPE audio driver. */ 1313 struct { 1314 struct platform_device *platdev; 1315 int irq; 1316 } lpe_audio; 1317 1318 struct i915_pmu pmu; 1319 1320 struct i915_hdcp_comp_master *hdcp_master; 1321 bool hdcp_comp_added; 1322 1323 /* Mutex to protect the above hdcp component related values. */ 1324 struct mutex hdcp_comp_mutex; 1325 1326 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1327 1328 #ifdef __NetBSD__ 1329 pci_intr_handle_t *pci_ihp; 1330 void *pci_intrcookie; 1331 #endif 1332 1333 /* 1334 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1335 * will be rejected. Instead look for a better place. 1336 */ 1337 }; 1338 1339 #ifdef __NetBSD__ 1340 # undef __iomem 1341 # undef __i915_iomem 1342 #endif 1343 1344 struct dram_dimm_info { 1345 u8 size, width, ranks; 1346 }; 1347 1348 struct dram_channel_info { 1349 struct dram_dimm_info dimm_l, dimm_s; 1350 u8 ranks; 1351 bool is_16gb_dimm; 1352 }; 1353 1354 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1355 { 1356 return __UNCONST(const_container_of(dev, struct drm_i915_private, drm)); 1357 } 1358 1359 #ifndef __NetBSD__ 1360 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1361 { 1362 return dev_get_drvdata(kdev); 1363 } 1364 #endif 1365 1366 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1367 { 1368 return pci_get_drvdata(pdev); 1369 } 1370 1371 /* Simple iterator over all initialised engines */ 1372 #define for_each_engine(engine__, dev_priv__, id__) \ 1373 for ((id__) = 0; \ 1374 (id__) < I915_NUM_ENGINES; \ 1375 (id__)++) \ 1376 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1377 1378 /* Iterator over subset of engines selected by mask */ 1379 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1380 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ 1381 (tmp__) ? \ 1382 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1383 0;) 1384 1385 #define rb_to_uabi_engine(rb) \ 1386 rb_entry_safe(rb, struct intel_engine_cs, uabi_node.rbtree) 1387 1388 #define for_each_uabi_engine(engine__, i915__) \ 1389 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1390 (engine__); \ 1391 (engine__) = rb_to_uabi_engine(rb_next2(&(i915__)->uabi_engines, &(engine__)->uabi_node.rbtree))) 1392 1393 #define I915_GTT_OFFSET_NONE ((u32)-1) 1394 1395 /* 1396 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1397 * considered to be the frontbuffer for the given plane interface-wise. This 1398 * doesn't mean that the hw necessarily already scans it out, but that any 1399 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1400 * 1401 * We have one bit per pipe and per scanout plane type. 1402 */ 1403 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1404 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1405 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1406 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1407 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1408 }) 1409 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1410 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1411 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1412 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1413 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1414 1415 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1416 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1417 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1418 1419 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1420 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1421 1422 #define REVID_FOREVER 0xff 1423 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1424 1425 #define INTEL_GEN_MASK(s, e) ( \ 1426 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1427 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1428 GENMASK((e) - 1, (s) - 1)) 1429 1430 /* Returns true if Gen is in inclusive range [Start, End] */ 1431 #define IS_GEN_RANGE(dev_priv, s, e) \ 1432 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1433 1434 #define IS_GEN(dev_priv, n) \ 1435 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1436 INTEL_INFO(dev_priv)->gen == (n)) 1437 1438 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1439 1440 /* 1441 * Return true if revision is in range [since,until] inclusive. 1442 * 1443 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1444 */ 1445 #define IS_REVID(p, since, until) \ 1446 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1447 1448 static __always_inline unsigned int 1449 __platform_mask_index(const struct intel_runtime_info *info, 1450 enum intel_platform p) 1451 { 1452 const unsigned int pbits = 1453 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1454 1455 /* Expand the platform_mask array if this fails. */ 1456 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1457 pbits * ARRAY_SIZE(info->platform_mask)); 1458 1459 return p / pbits; 1460 } 1461 1462 static __always_inline unsigned int 1463 __platform_mask_bit(const struct intel_runtime_info *info, 1464 enum intel_platform p) 1465 { 1466 const unsigned int pbits = 1467 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1468 1469 return p % pbits + INTEL_SUBPLATFORM_BITS; 1470 } 1471 1472 static inline u32 1473 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1474 { 1475 const unsigned int pi = __platform_mask_index(info, p); 1476 1477 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1478 } 1479 1480 static __always_inline bool 1481 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1482 { 1483 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1484 const unsigned int pi = __platform_mask_index(info, p); 1485 const unsigned int pb = __platform_mask_bit(info, p); 1486 1487 #if 0 1488 BUILD_BUG_ON(!__builtin_constant_p(p)); 1489 #endif 1490 1491 return info->platform_mask[pi] & BIT(pb); 1492 } 1493 1494 static __always_inline inline bool 1495 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1496 enum intel_platform p, unsigned int s) 1497 { 1498 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1499 const unsigned int pi = __platform_mask_index(info, p); 1500 const unsigned int pb = __platform_mask_bit(info, p); 1501 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1502 const u32 mask = info->platform_mask[pi]; 1503 1504 #if 0 1505 BUILD_BUG_ON(!__builtin_constant_p(p)); 1506 BUILD_BUG_ON(!__builtin_constant_p(s)); 1507 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1508 #endif 1509 1510 /* Shift and test on the MSB position so sign flag can be used. */ 1511 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1512 } 1513 1514 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1515 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1516 1517 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1518 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1519 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1520 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1521 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1522 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1523 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1524 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1525 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1526 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1527 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1528 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1529 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1530 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1531 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1532 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1533 #define IS_IRONLAKE_M(dev_priv) \ 1534 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1535 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1536 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1537 INTEL_INFO(dev_priv)->gt == 1) 1538 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1539 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1540 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1541 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1542 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1543 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1544 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1545 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1546 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1547 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1548 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1549 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1550 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1551 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1552 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1553 #define IS_BDW_ULT(dev_priv) \ 1554 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1555 #define IS_BDW_ULX(dev_priv) \ 1556 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1557 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1558 INTEL_INFO(dev_priv)->gt == 3) 1559 #define IS_HSW_ULT(dev_priv) \ 1560 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1561 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1562 INTEL_INFO(dev_priv)->gt == 3) 1563 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1564 INTEL_INFO(dev_priv)->gt == 1) 1565 /* ULX machines are also considered ULT. */ 1566 #define IS_HSW_ULX(dev_priv) \ 1567 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1568 #define IS_SKL_ULT(dev_priv) \ 1569 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1570 #define IS_SKL_ULX(dev_priv) \ 1571 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1572 #define IS_KBL_ULT(dev_priv) \ 1573 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1574 #define IS_KBL_ULX(dev_priv) \ 1575 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1576 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1577 INTEL_INFO(dev_priv)->gt == 2) 1578 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1579 INTEL_INFO(dev_priv)->gt == 3) 1580 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1581 INTEL_INFO(dev_priv)->gt == 4) 1582 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1583 INTEL_INFO(dev_priv)->gt == 2) 1584 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1585 INTEL_INFO(dev_priv)->gt == 3) 1586 #define IS_CFL_ULT(dev_priv) \ 1587 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1588 #define IS_CFL_ULX(dev_priv) \ 1589 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1590 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1591 INTEL_INFO(dev_priv)->gt == 2) 1592 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1593 INTEL_INFO(dev_priv)->gt == 3) 1594 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1595 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1596 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1597 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1598 1599 #define SKL_REVID_A0 0x0 1600 #define SKL_REVID_B0 0x1 1601 #define SKL_REVID_C0 0x2 1602 #define SKL_REVID_D0 0x3 1603 #define SKL_REVID_E0 0x4 1604 #define SKL_REVID_F0 0x5 1605 #define SKL_REVID_G0 0x6 1606 #define SKL_REVID_H0 0x7 1607 1608 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1609 1610 #define BXT_REVID_A0 0x0 1611 #define BXT_REVID_A1 0x1 1612 #define BXT_REVID_B0 0x3 1613 #define BXT_REVID_B_LAST 0x8 1614 #define BXT_REVID_C0 0x9 1615 1616 #define IS_BXT_REVID(dev_priv, since, until) \ 1617 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1618 1619 #define KBL_REVID_A0 0x0 1620 #define KBL_REVID_B0 0x1 1621 #define KBL_REVID_C0 0x2 1622 #define KBL_REVID_D0 0x3 1623 #define KBL_REVID_E0 0x4 1624 1625 #define IS_KBL_REVID(dev_priv, since, until) \ 1626 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1627 1628 #define GLK_REVID_A0 0x0 1629 #define GLK_REVID_A1 0x1 1630 1631 #define IS_GLK_REVID(dev_priv, since, until) \ 1632 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1633 1634 #define CNL_REVID_A0 0x0 1635 #define CNL_REVID_B0 0x1 1636 #define CNL_REVID_C0 0x2 1637 1638 #define IS_CNL_REVID(p, since, until) \ 1639 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1640 1641 #define ICL_REVID_A0 0x0 1642 #define ICL_REVID_A2 0x1 1643 #define ICL_REVID_B0 0x3 1644 #define ICL_REVID_B2 0x4 1645 #define ICL_REVID_C0 0x5 1646 1647 #define IS_ICL_REVID(p, since, until) \ 1648 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1649 1650 #define TGL_REVID_A0 0x0 1651 1652 #define IS_TGL_REVID(p, since, until) \ 1653 (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) 1654 1655 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1656 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1657 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1658 1659 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 1660 1661 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 1662 unsigned int first__ = (first); \ 1663 unsigned int count__ = (count); \ 1664 (INTEL_INFO(dev_priv)->engine_mask & \ 1665 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1666 }) 1667 #define VDBOX_MASK(dev_priv) \ 1668 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 1669 #define VEBOX_MASK(dev_priv) \ 1670 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 1671 1672 /* 1673 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1674 * All later gens can run the final buffer from the ppgtt 1675 */ 1676 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1677 1678 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1679 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1680 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1681 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1682 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 1683 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 1684 1685 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1686 1687 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1688 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1689 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1690 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1691 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 1692 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 1693 1694 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1695 1696 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1697 #define HAS_PPGTT(dev_priv) \ 1698 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1699 #define HAS_FULL_PPGTT(dev_priv) \ 1700 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1701 1702 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1703 GEM_BUG_ON((sizes) == 0); \ 1704 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1705 }) 1706 1707 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1708 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1709 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1710 1711 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1712 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1713 1714 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1715 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1716 1717 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1718 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1719 (IS_CANNONLAKE(dev_priv) || \ 1720 IS_SKL_GT3(dev_priv) || \ 1721 IS_SKL_GT4(dev_priv)) 1722 1723 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1724 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1725 IS_GEMINILAKE(dev_priv) || \ 1726 IS_KABYLAKE(dev_priv)) 1727 1728 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1729 * rows, which changed the alignment requirements and fence programming. 1730 */ 1731 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1732 !(IS_I915G(dev_priv) || \ 1733 IS_I915GM(dev_priv))) 1734 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1735 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1736 1737 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1738 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1739 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1740 1741 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1742 1743 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1744 1745 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1746 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1747 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1748 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) 1749 1750 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1751 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1752 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1753 1754 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1755 1756 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1757 1758 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1759 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1760 1761 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1762 1763 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1764 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1765 1766 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1767 1768 /* Having GuC is not the same as using GuC */ 1769 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) 1770 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) 1771 1772 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1773 1774 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1775 1776 1777 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1778 1779 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1780 1781 /* DPF == dynamic parity feature */ 1782 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1783 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1784 2 : HAS_L3_DPF(dev_priv)) 1785 1786 #define GT_FREQUENCY_MULTIPLIER 50 1787 #define GEN9_FREQ_SCALER 3 1788 1789 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1790 1791 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1792 1793 /* Only valid when HAS_DISPLAY() is true */ 1794 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) 1795 1796 static inline bool intel_vtd_active(void) 1797 { 1798 #ifdef CONFIG_INTEL_IOMMU 1799 if (intel_iommu_gfx_mapped) 1800 return true; 1801 #endif 1802 return false; 1803 } 1804 1805 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1806 { 1807 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1808 } 1809 1810 static inline bool 1811 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1812 { 1813 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1814 } 1815 1816 /* i915_drv.c */ 1817 #ifdef CONFIG_COMPAT 1818 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 1819 #else 1820 #define i915_compat_ioctl NULL 1821 #endif 1822 extern const struct dev_pm_ops i915_pm_ops; 1823 1824 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1825 void i915_driver_remove(struct drm_i915_private *i915); 1826 1827 int i915_drm_resume(struct drm_device *); 1828 int i915_drm_resume_early(struct drm_device *); 1829 int i915_drm_prepare(struct drm_device *); 1830 int i915_drm_suspend(struct drm_device *); 1831 int i915_drm_suspend_late(struct drm_device *, bool); 1832 1833 int i915_resume_switcheroo(struct drm_i915_private *i915); 1834 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1835 1836 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 1837 1838 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 1839 { 1840 return dev_priv->gvt; 1841 } 1842 1843 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 1844 { 1845 return dev_priv->vgpu.active; 1846 } 1847 1848 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1849 struct drm_file *file_priv); 1850 1851 /* i915_gem.c */ 1852 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1853 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1854 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1855 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1856 int i915_gem_freeze(struct drm_i915_private *dev_priv); 1857 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 1858 1859 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1860 1861 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1862 { 1863 /* 1864 * A single pass should suffice to release all the freed objects (along 1865 * most call paths) , but be a little more paranoid in that freeing 1866 * the objects does take a little amount of time, during which the rcu 1867 * callbacks could have added new objects into the freed list, and 1868 * armed the work again. 1869 */ 1870 while (atomic_read(&i915->mm.free_count)) { 1871 flush_work(&i915->mm.free_work); 1872 rcu_barrier(); 1873 } 1874 } 1875 1876 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1877 { 1878 /* 1879 * Similar to objects above (see i915_gem_drain_freed-objects), in 1880 * general we have workers that are armed by RCU and then rearm 1881 * themselves in their callbacks. To be paranoid, we need to 1882 * drain the workqueue a second time after waiting for the RCU 1883 * grace period so that we catch work queued via RCU from the first 1884 * pass. As neither drain_workqueue() nor flush_workqueue() report 1885 * a result, we make an assumption that we only don't require more 1886 * than 3 passes to catch all _recursive_ RCU delayed work. 1887 * 1888 */ 1889 int pass = 3; 1890 do { 1891 flush_workqueue(i915->wq); 1892 rcu_barrier(); 1893 i915_gem_drain_freed_objects(i915); 1894 } while (--pass); 1895 drain_workqueue(i915->wq); 1896 } 1897 1898 struct i915_vma * __must_check 1899 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1900 const struct i915_ggtt_view *view, 1901 u64 size, 1902 u64 alignment, 1903 u64 flags); 1904 1905 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1906 unsigned long flags); 1907 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1908 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1909 1910 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1911 1912 static inline int __must_check 1913 i915_mutex_lock_interruptible(struct drm_device *dev) 1914 { 1915 return mutex_lock_interruptible(&dev->struct_mutex); 1916 } 1917 1918 int i915_gem_dumb_create(struct drm_file *file_priv, 1919 struct drm_device *dev, 1920 struct drm_mode_create_dumb *args); 1921 1922 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1923 1924 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1925 { 1926 return atomic_read(&error->reset_count); 1927 } 1928 1929 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1930 const struct intel_engine_cs *engine) 1931 { 1932 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1933 } 1934 1935 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1936 void i915_gem_driver_register(struct drm_i915_private *i915); 1937 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1938 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1939 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1940 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1941 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1942 void i915_gem_resume(struct drm_i915_private *dev_priv); 1943 1944 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1945 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1946 1947 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1948 enum i915_cache_level cache_level); 1949 1950 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1951 struct dma_buf *dma_buf); 1952 1953 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1954 1955 static inline struct i915_gem_context * 1956 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1957 { 1958 return xa_load(&file_priv->context_xa, id); 1959 } 1960 1961 static inline struct i915_gem_context * 1962 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1963 { 1964 struct i915_gem_context *ctx; 1965 1966 rcu_read_lock(); 1967 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1968 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1969 ctx = NULL; 1970 rcu_read_unlock(); 1971 1972 return ctx; 1973 } 1974 1975 /* i915_gem_evict.c */ 1976 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1977 u64 min_size, u64 alignment, 1978 unsigned long color, 1979 u64 start, u64 end, 1980 unsigned flags); 1981 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1982 struct drm_mm_node *node, 1983 unsigned int flags); 1984 int i915_gem_evict_vm(struct i915_address_space *vm); 1985 1986 /* i915_gem_internal.c */ 1987 struct drm_i915_gem_object * 1988 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1989 phys_addr_t size); 1990 1991 /* i915_gem_tiling.c */ 1992 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1993 { 1994 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1995 1996 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1997 i915_gem_object_is_tiled(obj); 1998 } 1999 2000 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 2001 unsigned int tiling, unsigned int stride); 2002 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 2003 unsigned int tiling, unsigned int stride); 2004 2005 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 2006 2007 /* i915_cmd_parser.c */ 2008 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 2009 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 2010 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 2011 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 2012 struct i915_vma *batch, 2013 u32 batch_offset, 2014 u32 batch_length, 2015 struct i915_vma *shadow, 2016 bool trampoline); 2017 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 2018 2019 /* intel_device_info.c */ 2020 static inline struct intel_device_info * 2021 mkwrite_device_info(struct drm_i915_private *dev_priv) 2022 { 2023 return (struct intel_device_info *)INTEL_INFO(dev_priv); 2024 } 2025 2026 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2027 struct drm_file *file); 2028 2029 #define __I915_REG_OP(op__, dev_priv__, ...) \ 2030 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 2031 2032 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 2033 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 2034 2035 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 2036 2037 /* These are untraced mmio-accessors that are only valid to be used inside 2038 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 2039 * controlled. 2040 * 2041 * Think twice, and think again, before using these. 2042 * 2043 * As an example, these accessors can possibly be used between: 2044 * 2045 * spin_lock_irq(&dev_priv->uncore.lock); 2046 * intel_uncore_forcewake_get__locked(); 2047 * 2048 * and 2049 * 2050 * intel_uncore_forcewake_put__locked(); 2051 * spin_unlock_irq(&dev_priv->uncore.lock); 2052 * 2053 * 2054 * Note: some registers may not need forcewake held, so 2055 * intel_uncore_forcewake_{get,put} can be omitted, see 2056 * intel_uncore_forcewake_for_reg(). 2057 * 2058 * Certain architectures will die if the same cacheline is concurrently accessed 2059 * by different clients (e.g. on Ivybridge). Access to registers should 2060 * therefore generally be serialised, by either the dev_priv->uncore.lock or 2061 * a more localised lock guarding all access to that bank of registers. 2062 */ 2063 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 2064 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 2065 2066 /* register wait wrappers for display regs */ 2067 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \ 2068 intel_wait_for_register(&(dev_priv_)->uncore, \ 2069 (reg_), (mask_), (value_), (timeout_)) 2070 2071 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \ 2072 u32 mask__ = (mask_); \ 2073 intel_de_wait_for_register((dev_priv_), (reg_), \ 2074 mask__, mask__, (timeout_)); \ 2075 }) 2076 2077 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ 2078 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_)) 2079 2080 /* i915_mm.c */ 2081 #ifndef __NetBSD__ 2082 int remap_io_mapping(struct vm_area_struct *vma, 2083 unsigned long addr, unsigned long pfn, unsigned long size, 2084 struct io_mapping *iomap); 2085 int remap_io_sg(struct vm_area_struct *vma, 2086 unsigned long addr, unsigned long size, 2087 struct scatterlist *sgl, resource_size_t iobase); 2088 #endif 2089 2090 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 2091 { 2092 if (INTEL_GEN(i915) >= 10) 2093 return CNL_HWS_CSB_WRITE_INDEX; 2094 else 2095 return I915_HWS_CSB_WRITE_INDEX; 2096 } 2097 2098 static inline enum i915_map_type 2099 i915_coherent_map_type(struct drm_i915_private *i915) 2100 { 2101 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 2102 } 2103 2104 static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc) 2105 { 2106 return intel_guc_is_submission_supported(guc) && 2107 intel_guc_is_running(guc); 2108 } 2109 2110 #endif 2111