1 /* $NetBSD: i915_cmd_parser.c,v 1.22 2020/02/14 14:34:58 maya Exp $ */ 2 3 /* 4 * Copyright © 2013 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Brad Volkin <bradley.d.volkin@intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: i915_cmd_parser.c,v 1.22 2020/02/14 14:34:58 maya Exp $"); 32 33 #include "i915_drv.h" 34 #include <linux/bitmap.h> 35 36 /** 37 * DOC: batch buffer command parser 38 * 39 * Motivation: 40 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 41 * require userspace code to submit batches containing commands such as 42 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 43 * generations of the hardware will noop these commands in "unsecure" batches 44 * (which includes all userspace batches submitted via i915) even though the 45 * commands may be safe and represent the intended programming model of the 46 * device. 47 * 48 * The software command parser is similar in operation to the command parsing 49 * done in hardware for unsecure batches. However, the software parser allows 50 * some operations that would be noop'd by hardware, if the parser determines 51 * the operation is safe, and submits the batch as "secure" to prevent hardware 52 * parsing. 53 * 54 * Threats: 55 * At a high level, the hardware (and software) checks attempt to prevent 56 * granting userspace undue privileges. There are three categories of privilege. 57 * 58 * First, commands which are explicitly defined as privileged or which should 59 * only be used by the kernel driver. The parser rejects such commands 60 * 61 * Second, commands which access registers. To support correct/enhanced 62 * userspace functionality, particularly certain OpenGL extensions, the parser 63 * provides a whitelist of registers which userspace may safely access 64 * 65 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 66 * The parser always rejects such commands. 67 * 68 * The majority of the problematic commands fall in the MI_* range, with only a 69 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). 70 * 71 * Implementation: 72 * Each ring maintains tables of commands and registers which the parser uses in 73 * scanning batch buffers submitted to that ring. 74 * 75 * Since the set of commands that the parser must check for is significantly 76 * smaller than the number of commands supported, the parser tables contain only 77 * those commands required by the parser. This generally works because command 78 * opcode ranges have standard command length encodings. So for commands that 79 * the parser does not need to check, it can easily skip them. This is 80 * implemented via a per-ring length decoding vfunc. 81 * 82 * Unfortunately, there are a number of commands that do not follow the standard 83 * length encoding for their opcode range, primarily amongst the MI_* commands. 84 * To handle this, the parser provides a way to define explicit "skip" entries 85 * in the per-ring command tables. 86 * 87 * Other command table entries map fairly directly to high level categories 88 * mentioned above: rejected, register whitelist. The parser implements a number 89 * of checks, including the privileged memory checks, via a general bitmasking 90 * mechanism. 91 */ 92 93 #define STD_MI_OPCODE_MASK 0xFF800000 94 #define STD_3D_OPCODE_MASK 0xFFFF0000 95 #define STD_2D_OPCODE_MASK 0xFFC00000 96 #define STD_MFX_OPCODE_MASK 0xFFFF0000 97 98 #define CMD(op, opm, f, lm, fl, ...) \ 99 { \ 100 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 101 .cmd = { (op) & (opm), (opm) }, \ 102 .length = { (lm) }, \ 103 __VA_ARGS__ \ 104 } 105 106 /* Convenience macros to compress the tables */ 107 #define SMI STD_MI_OPCODE_MASK 108 #define S3D STD_3D_OPCODE_MASK 109 #define S2D STD_2D_OPCODE_MASK 110 #define SMFX STD_MFX_OPCODE_MASK 111 #define F true 112 #define S CMD_DESC_SKIP 113 #define R CMD_DESC_REJECT 114 #define W CMD_DESC_REGISTER 115 #define B CMD_DESC_BITMASK 116 117 /* Command Mask Fixed Len Action 118 ---------------------------------------------------------- */ 119 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = { 120 CMD( MI_NOOP, SMI, F, 1, S ), 121 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 122 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ), 123 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 124 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 125 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 126 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 127 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 128 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 129 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 130 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 131 .reg = { .offset = 1, .mask = 0x007FFFFC }, 132 .bits = {{ 133 .offset = 0, 134 .mask = MI_GLOBAL_GTT, 135 .expected = 0, 136 }}, ), 137 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 138 .reg = { .offset = 1, .mask = 0x007FFFFC }, 139 .bits = {{ 140 .offset = 0, 141 .mask = MI_GLOBAL_GTT, 142 .expected = 0, 143 }}, ), 144 /* 145 * MI_BATCH_BUFFER_START requires some special handling. It's not 146 * really a 'skip' action but it doesn't seem like it's worth adding 147 * a new action. See i915_parse_cmds(). 148 */ 149 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 150 }; 151 152 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = { 153 CMD( MI_FLUSH, SMI, F, 1, S ), 154 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 155 CMD( MI_PREDICATE, SMI, F, 1, S ), 156 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 157 CMD( MI_SET_APPID, SMI, F, 1, S ), 158 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 159 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 160 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 161 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 162 .bits = {{ 163 .offset = 0, 164 .mask = MI_GLOBAL_GTT, 165 .expected = 0, 166 }}, ), 167 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 168 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 169 .bits = {{ 170 .offset = 0, 171 .mask = MI_GLOBAL_GTT, 172 .expected = 0, 173 }}, ), 174 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 175 .bits = {{ 176 .offset = 1, 177 .mask = MI_REPORT_PERF_COUNT_GGTT, 178 .expected = 0, 179 }}, ), 180 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 181 .bits = {{ 182 .offset = 0, 183 .mask = MI_GLOBAL_GTT, 184 .expected = 0, 185 }}, ), 186 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 187 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 188 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 189 .bits = {{ 190 .offset = 2, 191 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 192 .expected = 0, 193 }}, ), 194 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 195 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 196 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 197 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 198 .bits = {{ 199 .offset = 1, 200 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 201 .expected = 0, 202 }, 203 { 204 .offset = 1, 205 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 206 PIPE_CONTROL_STORE_DATA_INDEX), 207 .expected = 0, 208 .condition_offset = 1, 209 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 210 }}, ), 211 }; 212 213 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 214 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 215 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 216 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 217 CMD( MI_SET_APPID, SMI, F, 1, S ), 218 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 219 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 220 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 221 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), 222 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 223 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 224 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 225 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 226 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 227 228 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 229 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 230 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 231 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 232 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 233 }; 234 235 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = { 236 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 237 CMD( MI_SET_APPID, SMI, F, 1, S ), 238 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 239 .bits = {{ 240 .offset = 0, 241 .mask = MI_GLOBAL_GTT, 242 .expected = 0, 243 }}, ), 244 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 245 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 246 .bits = {{ 247 .offset = 0, 248 .mask = MI_FLUSH_DW_NOTIFY, 249 .expected = 0, 250 }, 251 { 252 .offset = 1, 253 .mask = MI_FLUSH_DW_USE_GTT, 254 .expected = 0, 255 .condition_offset = 0, 256 .condition_mask = MI_FLUSH_DW_OP_MASK, 257 }, 258 { 259 .offset = 0, 260 .mask = MI_FLUSH_DW_STORE_INDEX, 261 .expected = 0, 262 .condition_offset = 0, 263 .condition_mask = MI_FLUSH_DW_OP_MASK, 264 }}, ), 265 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 266 .bits = {{ 267 .offset = 0, 268 .mask = MI_GLOBAL_GTT, 269 .expected = 0, 270 }}, ), 271 /* 272 * MFX_WAIT doesn't fit the way we handle length for most commands. 273 * It has a length field but it uses a non-standard length bias. 274 * It is always 1 dword though, so just treat it as fixed length. 275 */ 276 CMD( MFX_WAIT, SMFX, F, 1, S ), 277 }; 278 279 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = { 280 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 281 CMD( MI_SET_APPID, SMI, F, 1, S ), 282 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 283 .bits = {{ 284 .offset = 0, 285 .mask = MI_GLOBAL_GTT, 286 .expected = 0, 287 }}, ), 288 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 289 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 290 .bits = {{ 291 .offset = 0, 292 .mask = MI_FLUSH_DW_NOTIFY, 293 .expected = 0, 294 }, 295 { 296 .offset = 1, 297 .mask = MI_FLUSH_DW_USE_GTT, 298 .expected = 0, 299 .condition_offset = 0, 300 .condition_mask = MI_FLUSH_DW_OP_MASK, 301 }, 302 { 303 .offset = 0, 304 .mask = MI_FLUSH_DW_STORE_INDEX, 305 .expected = 0, 306 .condition_offset = 0, 307 .condition_mask = MI_FLUSH_DW_OP_MASK, 308 }}, ), 309 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 310 .bits = {{ 311 .offset = 0, 312 .mask = MI_GLOBAL_GTT, 313 .expected = 0, 314 }}, ), 315 }; 316 317 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = { 318 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 319 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 320 .bits = {{ 321 .offset = 0, 322 .mask = MI_GLOBAL_GTT, 323 .expected = 0, 324 }}, ), 325 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 326 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 327 .bits = {{ 328 .offset = 0, 329 .mask = MI_FLUSH_DW_NOTIFY, 330 .expected = 0, 331 }, 332 { 333 .offset = 1, 334 .mask = MI_FLUSH_DW_USE_GTT, 335 .expected = 0, 336 .condition_offset = 0, 337 .condition_mask = MI_FLUSH_DW_OP_MASK, 338 }, 339 { 340 .offset = 0, 341 .mask = MI_FLUSH_DW_STORE_INDEX, 342 .expected = 0, 343 .condition_offset = 0, 344 .condition_mask = MI_FLUSH_DW_OP_MASK, 345 }}, ), 346 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 347 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 348 }; 349 350 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 351 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 352 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 353 }; 354 355 /* 356 * For Gen9 we can still rely on the h/w to enforce cmd security, and only 357 * need to re-enforce the register access checks. We therefore only need to 358 * teach the cmdparser how to find the end of each command, and identify 359 * register accesses. The table doesn't need to reject any commands, and so 360 * the only commands listed here are: 361 * 1) Those that touch registers 362 * 2) Those that do not have the default 8-bit length 363 * 364 * Note that the default MI length mask chosen for this table is 0xFF, not 365 * the 0x3F used on older devices. This is because the vast majority of MI 366 * cmds on Gen9 use a standard 8-bit Length field. 367 * All the Gen9 blitter instructions are standard 0xFF length mask, and 368 * none allow access to non-general registers, so in fact no BLT cmds are 369 * included in the table at all. 370 * 371 */ 372 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = { 373 CMD( MI_NOOP, SMI, F, 1, S ), 374 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), 375 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), 376 CMD( MI_FLUSH, SMI, F, 1, S ), 377 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 378 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 379 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), 380 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 381 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ), 382 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ), 383 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), 384 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 385 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 386 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ), 387 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W, 388 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 389 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ), 390 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W, 391 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 392 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 393 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 394 395 /* 396 * We allow BB_START but apply further checks. We just sanitize the 397 * basic fields here. 398 */ 399 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B, 400 .bits = {{ 401 .offset = 0, 402 .mask = ~SMI, 403 .expected = (MI_BATCH_PPGTT_HSW | 1), 404 }}, ), 405 }; 406 407 #undef CMD 408 #undef SMI 409 #undef S3D 410 #undef S2D 411 #undef SMFX 412 #undef F 413 #undef S 414 #undef R 415 #undef W 416 #undef B 417 418 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = { 419 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 420 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 421 }; 422 423 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = { 424 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 425 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 426 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 427 }; 428 429 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = { 430 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 431 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) }, 432 }; 433 434 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = { 435 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 436 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) }, 437 }; 438 439 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = { 440 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 441 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 442 }; 443 444 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = { 445 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 446 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 447 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 448 }; 449 450 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = { 451 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) }, 452 }; 453 454 455 /* 456 * Register whitelists, sorted by increasing register offset. 457 */ 458 459 /* 460 * An individual whitelist entry granting access to register addr. If 461 * mask is non-zero the argument of immediate register writes will be 462 * AND-ed with mask, and the command will be rejected if the result 463 * doesn't match value. 464 * 465 * Registers with non-zero mask are only allowed to be written using 466 * LRI. 467 */ 468 struct drm_i915_reg_descriptor { 469 u32 addr; 470 u32 mask; 471 u32 value; 472 }; 473 474 /* Convenience macro for adding 32-bit registers. */ 475 #define REG32(address, ...) \ 476 { .addr = address, __VA_ARGS__ } 477 478 /* 479 * Convenience macro for adding 64-bit registers. 480 * 481 * Some registers that userspace accesses are 64 bits. The register 482 * access commands only allow 32-bit accesses. Hence, we have to include 483 * entries for both halves of the 64-bit registers. 484 */ 485 #define REG64(addr) \ 486 REG32(addr), REG32(addr + sizeof(u32)) 487 488 #define REG64_IDX(_reg, idx) \ 489 { .addr = _reg(idx) }, \ 490 { .addr = _reg ## _UDW(idx) } 491 492 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 493 REG64(GPGPU_THREADS_DISPATCHED), 494 REG64(HS_INVOCATION_COUNT), 495 REG64(DS_INVOCATION_COUNT), 496 REG64(IA_VERTICES_COUNT), 497 REG64(IA_PRIMITIVES_COUNT), 498 REG64(VS_INVOCATION_COUNT), 499 REG64(GS_INVOCATION_COUNT), 500 REG64(GS_PRIMITIVES_COUNT), 501 REG64(CL_INVOCATION_COUNT), 502 REG64(CL_PRIMITIVES_COUNT), 503 REG64(PS_INVOCATION_COUNT), 504 REG64(PS_DEPTH_COUNT), 505 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */ 506 REG64(MI_PREDICATE_SRC0), 507 REG64(MI_PREDICATE_SRC1), 508 REG32(GEN7_3DPRIM_END_OFFSET), 509 REG32(GEN7_3DPRIM_START_VERTEX), 510 REG32(GEN7_3DPRIM_VERTEX_COUNT), 511 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 512 REG32(GEN7_3DPRIM_START_INSTANCE), 513 REG32(GEN7_3DPRIM_BASE_VERTEX), 514 REG32(GEN7_GPGPU_DISPATCHDIMX), 515 REG32(GEN7_GPGPU_DISPATCHDIMY), 516 REG32(GEN7_GPGPU_DISPATCHDIMZ), 517 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), 518 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), 519 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), 520 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), 521 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)), 522 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)), 523 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)), 524 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)), 525 REG32(GEN7_SO_WRITE_OFFSET(0)), 526 REG32(GEN7_SO_WRITE_OFFSET(1)), 527 REG32(GEN7_SO_WRITE_OFFSET(2)), 528 REG32(GEN7_SO_WRITE_OFFSET(3)), 529 REG32(GEN7_L3SQCREG1), 530 REG32(GEN7_L3CNTLREG2), 531 REG32(GEN7_L3CNTLREG3), 532 REG32(HSW_SCRATCH1, 533 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 534 .value = 0), 535 REG32(HSW_ROW_CHICKEN3, 536 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 537 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 538 .value = 0), 539 }; 540 541 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 542 REG32(BCS_SWCTRL), 543 }; 544 545 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { 546 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 547 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 548 REG32(BCS_SWCTRL), 549 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 550 REG64_IDX(BCS_GPR, 0), 551 REG64_IDX(BCS_GPR, 1), 552 REG64_IDX(BCS_GPR, 2), 553 REG64_IDX(BCS_GPR, 3), 554 REG64_IDX(BCS_GPR, 4), 555 REG64_IDX(BCS_GPR, 5), 556 REG64_IDX(BCS_GPR, 6), 557 REG64_IDX(BCS_GPR, 7), 558 REG64_IDX(BCS_GPR, 8), 559 REG64_IDX(BCS_GPR, 9), 560 REG64_IDX(BCS_GPR, 10), 561 REG64_IDX(BCS_GPR, 11), 562 REG64_IDX(BCS_GPR, 12), 563 REG64_IDX(BCS_GPR, 13), 564 REG64_IDX(BCS_GPR, 14), 565 REG64_IDX(BCS_GPR, 15), 566 }; 567 568 #undef REG64 569 #undef REG32 570 571 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 572 { 573 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 574 u32 subclient = 575 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 576 577 if (client == INSTR_MI_CLIENT) 578 return 0x3F; 579 else if (client == INSTR_RC_CLIENT) { 580 if (subclient == INSTR_MEDIA_SUBCLIENT) 581 return 0xFFFF; 582 else 583 return 0xFF; 584 } 585 586 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 587 return 0; 588 } 589 590 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 591 { 592 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 593 u32 subclient = 594 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 595 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 596 597 if (client == INSTR_MI_CLIENT) 598 return 0x3F; 599 else if (client == INSTR_RC_CLIENT) { 600 if (subclient == INSTR_MEDIA_SUBCLIENT) { 601 if (op == 6) 602 return 0xFFFF; 603 else 604 return 0xFFF; 605 } else 606 return 0xFF; 607 } 608 609 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 610 return 0; 611 } 612 613 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 614 { 615 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 616 617 if (client == INSTR_MI_CLIENT) 618 return 0x3F; 619 else if (client == INSTR_BC_CLIENT) 620 return 0xFF; 621 622 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 623 return 0; 624 } 625 626 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header) 627 { 628 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 629 630 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT) 631 return 0xFF; 632 633 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 634 return 0; 635 } 636 637 __diagused 638 static bool validate_cmds_sorted(struct intel_engine_cs *ring, 639 const struct drm_i915_cmd_table *cmd_tables, 640 int cmd_table_count) 641 { 642 int i; 643 bool ret = true; 644 645 if (!cmd_tables || cmd_table_count == 0) 646 return true; 647 648 for (i = 0; i < cmd_table_count; i++) { 649 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 650 u32 previous = 0; 651 int j; 652 653 for (j = 0; j < table->count; j++) { 654 const struct drm_i915_cmd_descriptor *desc = 655 &table->table[j]; 656 u32 curr = desc->cmd.value & desc->cmd.mask; 657 658 if (curr < previous) { 659 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 660 ring->id, i, j, curr, previous); 661 ret = false; 662 } 663 664 previous = curr; 665 } 666 } 667 668 return ret; 669 } 670 671 static bool check_sorted(int ring_id, 672 const struct drm_i915_reg_descriptor *reg_table, 673 int reg_count) 674 { 675 int i; 676 u32 previous = 0; 677 bool ret = true; 678 679 for (i = 0; i < reg_count; i++) { 680 u32 curr = reg_table[i].addr; 681 682 if (curr < previous) { 683 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", 684 ring_id, i, curr, previous); 685 ret = false; 686 } 687 688 previous = curr; 689 } 690 691 return ret; 692 } 693 694 __diagused 695 static bool validate_regs_sorted(struct intel_engine_cs *ring) 696 { 697 return check_sorted(ring->id, ring->reg_table, ring->reg_count); 698 } 699 700 struct cmd_node { 701 const struct drm_i915_cmd_descriptor *desc; 702 struct hlist_node node; 703 }; 704 705 /* 706 * Different command ranges have different numbers of bits for the opcode. For 707 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 708 * problem is that, for example, MI commands use bits 22:16 for other fields 709 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 710 * we mask a command from a batch it could hash to the wrong bucket due to 711 * non-opcode bits being set. But if we don't include those bits, some 3D 712 * commands may hash to the same bucket due to not including opcode bits that 713 * make the command unique. For now, we will risk hashing to the same bucket. 714 * 715 * If we attempt to generate a perfect hash, we should be able to look at bits 716 * 31:29 of a command from a batch buffer and use the full mask for that 717 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this. 718 */ 719 #define CMD_HASH_MASK STD_MI_OPCODE_MASK 720 721 static int init_hash_table(struct intel_engine_cs *ring, 722 const struct drm_i915_cmd_table *cmd_tables, 723 int cmd_table_count) 724 { 725 int i, j; 726 727 hash_init(ring->cmd_hash); 728 729 for (i = 0; i < cmd_table_count; i++) { 730 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 731 732 for (j = 0; j < table->count; j++) { 733 const struct drm_i915_cmd_descriptor *desc = 734 &table->table[j]; 735 struct cmd_node *desc_node = 736 kmalloc(sizeof(*desc_node), GFP_KERNEL); 737 738 if (!desc_node) 739 return -ENOMEM; 740 741 desc_node->desc = desc; 742 hash_add(ring->cmd_hash, &desc_node->node, 743 desc->cmd.value & CMD_HASH_MASK); 744 } 745 } 746 747 return 0; 748 } 749 750 static void fini_hash_table(struct intel_engine_cs *ring) 751 { 752 struct hlist_node *tmp; 753 struct cmd_node *desc_node; 754 int i; 755 756 hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) { 757 hash_del(&desc_node->node); 758 kfree(desc_node); 759 } 760 } 761 762 /** 763 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer 764 * @ring: the ringbuffer to initialize 765 * 766 * Optionally initializes fields related to batch buffer command parsing in the 767 * struct intel_engine_cs based on whether the platform requires software 768 * command parsing. 769 * 770 * Return: non-zero if initialization fails 771 */ 772 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring) 773 { 774 const struct drm_i915_cmd_table *cmd_tables; 775 int cmd_table_count; 776 int ret; 777 778 if (!IS_GEN7(ring->dev) && !(IS_GEN9(ring->dev) && ring->id == BCS)) 779 return 0; 780 781 switch (ring->id) { 782 case RCS: 783 if (IS_HASWELL(ring->dev)) { 784 cmd_tables = hsw_render_ring_cmd_table; 785 cmd_table_count = 786 ARRAY_SIZE(hsw_render_ring_cmd_table); 787 } else { 788 cmd_tables = gen7_render_cmd_table; 789 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table); 790 } 791 792 ring->reg_table = gen7_render_regs; 793 ring->reg_count = ARRAY_SIZE(gen7_render_regs); 794 795 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 796 break; 797 case VCS: 798 cmd_tables = gen7_video_cmd_table; 799 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table); 800 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 801 break; 802 case BCS: 803 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 804 if (IS_GEN9(ring->dev)) { 805 cmd_tables = gen9_blt_cmd_table; 806 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table); 807 ring->get_cmd_length_mask = 808 gen9_blt_get_cmd_length_mask; 809 810 /* BCS Engine unsafe without parser */ 811 ring->requires_cmd_parser = 1; 812 } 813 else if (IS_HASWELL(ring->dev)) { 814 cmd_tables = hsw_blt_ring_cmd_table; 815 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table); 816 } else { 817 cmd_tables = gen7_blt_cmd_table; 818 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table); 819 } 820 821 if (IS_GEN9(ring->dev)) { 822 ring->reg_table = gen9_blt_regs; 823 ring->reg_count = ARRAY_SIZE(gen9_blt_regs); 824 } else { 825 ring->reg_table = gen7_blt_regs; 826 ring->reg_count = ARRAY_SIZE(gen7_blt_regs); 827 } 828 829 break; 830 case VECS: 831 cmd_tables = hsw_vebox_cmd_table; 832 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table); 833 /* VECS can use the same length_mask function as VCS */ 834 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 835 break; 836 default: 837 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", 838 ring->id); 839 BUG(); 840 } 841 842 BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count)); 843 BUG_ON(!validate_regs_sorted(ring)); 844 845 WARN_ON(!hash_empty(ring->cmd_hash)); 846 847 ret = init_hash_table(ring, cmd_tables, cmd_table_count); 848 if (ret) { 849 DRM_ERROR("CMD: cmd_parser_init failed!\n"); 850 fini_hash_table(ring); 851 return ret; 852 } 853 854 ring->using_cmd_parser = true; 855 856 return 0; 857 } 858 859 /** 860 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields 861 * @ring: the ringbuffer to clean up 862 * 863 * Releases any resources related to command parsing that may have been 864 * initialized for the specified ring. 865 */ 866 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring) 867 { 868 if (!ring->using_cmd_parser) 869 return; 870 871 fini_hash_table(ring); 872 } 873 874 static const struct drm_i915_cmd_descriptor* 875 find_cmd_in_table(struct intel_engine_cs *ring, 876 u32 cmd_header) 877 { 878 struct cmd_node *desc_node; 879 880 hash_for_each_possible(ring->cmd_hash, desc_node, node, 881 cmd_header & CMD_HASH_MASK) { 882 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 883 u32 masked_cmd = desc->cmd.mask & cmd_header; 884 u32 masked_value = desc->cmd.value & desc->cmd.mask; 885 886 if (masked_cmd == masked_value) 887 return desc; 888 } 889 890 return NULL; 891 } 892 893 /* 894 * Returns a pointer to a descriptor for the command specified by cmd_header. 895 * 896 * The caller must supply space for a default descriptor via the default_desc 897 * parameter. If no descriptor for the specified command exists in the ring's 898 * command parser tables, this function fills in default_desc based on the 899 * ring's default length encoding and returns default_desc. 900 */ 901 static const struct drm_i915_cmd_descriptor* 902 find_cmd(struct intel_engine_cs *ring, 903 u32 cmd_header, 904 struct drm_i915_cmd_descriptor *default_desc) 905 { 906 const struct drm_i915_cmd_descriptor *desc; 907 u32 mask; 908 909 desc = find_cmd_in_table(ring, cmd_header); 910 if (desc) 911 return desc; 912 913 mask = ring->get_cmd_length_mask(cmd_header); 914 if (!mask) 915 return NULL; 916 917 BUG_ON(!default_desc); 918 default_desc->flags = CMD_DESC_SKIP; 919 default_desc->length.mask = mask; 920 921 return default_desc; 922 } 923 924 static const struct drm_i915_reg_descriptor * 925 find_reg(const struct drm_i915_reg_descriptor *table, 926 int count, u32 addr) 927 { 928 if (table) { 929 int i; 930 931 for (i = 0; i < count; i++) { 932 if (table[i].addr == addr) 933 return &table[i]; 934 } 935 } 936 937 return NULL; 938 } 939 940 #ifndef __NetBSD__ 941 static u32 *vmap_batch(struct drm_i915_gem_object *obj, 942 unsigned start, unsigned len) 943 { 944 int i; 945 void *addr = NULL; 946 struct sg_page_iter sg_iter; 947 int first_page = start >> PAGE_SHIFT; 948 int last_page = (len + start + 4095) >> PAGE_SHIFT; 949 int npages = last_page - first_page; 950 struct page **pages; 951 952 pages = drm_malloc_ab(npages, sizeof(*pages)); 953 if (pages == NULL) { 954 DRM_DEBUG_DRIVER("Failed to get space for pages\n"); 955 goto finish; 956 } 957 958 i = 0; 959 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) { 960 pages[i++] = sg_page_iter_page(&sg_iter); 961 if (i == npages) 962 break; 963 } 964 965 addr = vmap(pages, i, 0, PAGE_KERNEL); 966 if (addr == NULL) { 967 DRM_DEBUG_DRIVER("Failed to vmap pages\n"); 968 goto finish; 969 } 970 971 finish: 972 if (pages) 973 drm_free_large(pages); 974 return (u32*)addr; 975 } 976 #endif /* __NetBSD__ */ 977 978 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */ 979 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, 980 struct drm_i915_gem_object *src_obj, 981 u32 batch_start_offset, 982 u32 batch_len) 983 { 984 int needs_clflush = 0; 985 const void *src_base, *src; 986 void *dst = NULL; 987 int ret; 988 989 if (batch_len > dest_obj->base.size || 990 batch_len + batch_start_offset > src_obj->base.size) 991 return ERR_PTR(-E2BIG); 992 993 if (WARN_ON(dest_obj->pages_pin_count == 0)) 994 return ERR_PTR(-ENODEV); 995 996 ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush); 997 if (ret) { 998 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n"); 999 return ERR_PTR(ret); 1000 } 1001 1002 #ifdef __NetBSD__ 1003 const u32 srcstart = rounddown(batch_start_offset, PAGE_SIZE); 1004 const u32 srclen = roundup(batch_start_offset + batch_len, PAGE_SIZE) 1005 - srcstart; 1006 vaddr_t srcva = 0; /* hint */ 1007 1008 /* Acquire a reference for uvm_map to consume. */ 1009 uao_reference(src_obj->base.filp); 1010 1011 /* XXX errno NetBSD->Linux */ 1012 ret = -uvm_map(kernel_map, &srcva, srclen, src_obj->base.filp, 1013 srcstart, PAGE_SIZE, UVM_MAPFLAG(UVM_PROT_RW, UVM_PROT_RW, 1014 UVM_INH_NONE, UVM_ADV_SEQUENTIAL, UVM_FLAG_NOWAIT)); 1015 if (ret) { 1016 uao_detach(src_obj->base.filp); 1017 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch: %d\n", ret); 1018 goto unpin_src; 1019 } 1020 src_base = (const void *)srcva; 1021 #else 1022 src_base = vmap_batch(src_obj, batch_start_offset, batch_len); 1023 if (!src_base) { 1024 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); 1025 ret = -ENOMEM; 1026 goto unpin_src; 1027 } 1028 #endif 1029 1030 ret = i915_gem_object_set_to_cpu_domain(dest_obj, true); 1031 if (ret) { 1032 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n"); 1033 goto unmap_src; 1034 } 1035 1036 #ifdef __NetBSD__ 1037 const u32 dststart = rounddown(0, PAGE_SIZE); 1038 const u32 dstlen = roundup(0 + batch_len, PAGE_SIZE) - dststart; 1039 vaddr_t dstva = 0; /* hint */ 1040 1041 /* Acquire a reference for uvm_map to consume. */ 1042 uao_reference(dest_obj->base.filp); 1043 1044 /* XXX errno NetBSD->Linux */ 1045 ret = -uvm_map(kernel_map, &dstva, dstlen, dest_obj->base.filp, 1046 dststart, PAGE_SIZE, UVM_MAPFLAG(UVM_PROT_RW, UVM_PROT_RW, 1047 UVM_INH_NONE, UVM_ADV_SEQUENTIAL, UVM_FLAG_NOWAIT)); 1048 if (ret) { 1049 uao_detach(dest_obj->base.filp); 1050 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch: %d\n", ret); 1051 goto unmap_src; 1052 } 1053 dst = (void *)dstva; 1054 #else 1055 dst = vmap_batch(dest_obj, 0, batch_len); 1056 if (!dst) { 1057 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n"); 1058 ret = -ENOMEM; 1059 goto unmap_src; 1060 } 1061 #endif 1062 1063 src = src_base + offset_in_page(batch_start_offset); 1064 if (needs_clflush) 1065 drm_clflush_virt_range(src, batch_len); 1066 1067 #ifdef __NetBSD__ 1068 ret = -kcopy(src, dst, batch_len); 1069 if (ret) { 1070 uvm_unmap(kernel_map, dstva, dstva + dstlen); 1071 goto unmap_src; 1072 } 1073 #else 1074 memcpy(dst, src, batch_len); 1075 #endif 1076 1077 unmap_src: 1078 #ifdef __NetBSD__ 1079 uvm_unmap(kernel_map, srcva, srcva + srclen); 1080 #else 1081 vunmap(src_base); 1082 #endif 1083 unpin_src: 1084 i915_gem_object_unpin_pages(src_obj); 1085 1086 return ret ? ERR_PTR(ret) : dst; 1087 } 1088 1089 static int check_cmd(const struct intel_engine_cs *ring, 1090 const struct drm_i915_cmd_descriptor *desc, 1091 const u32 *cmd, u32 length, 1092 bool *oacontrol_set) 1093 { 1094 if (desc->flags & CMD_DESC_REJECT) { 1095 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 1096 return false; 1097 } 1098 1099 if (desc->flags & CMD_DESC_REGISTER) { 1100 /* 1101 * Get the distance between individual register offset 1102 * fields if the command can perform more than one 1103 * access at a time. 1104 */ 1105 const u32 step = desc->reg.step ? desc->reg.step : length; 1106 u32 offset; 1107 1108 for (offset = desc->reg.offset; offset < length; 1109 offset += step) { 1110 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1111 const struct drm_i915_reg_descriptor *reg = 1112 find_reg(ring->reg_table, ring->reg_count, 1113 reg_addr); 1114 1115 if (!reg) { 1116 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", 1117 reg_addr, *cmd, ring->id); 1118 return false; 1119 } 1120 1121 /* 1122 * OACONTROL requires some special handling for 1123 * writes. We want to make sure that any batch which 1124 * enables OA also disables it before the end of the 1125 * batch. The goal is to prevent one process from 1126 * snooping on the perf data from another process. To do 1127 * that, we need to check the value that will be written 1128 * to the register. Hence, limit OACONTROL writes to 1129 * only MI_LOAD_REGISTER_IMM commands. 1130 */ 1131 if (reg_addr == OACONTROL) { 1132 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1133 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); 1134 return false; 1135 } 1136 1137 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) 1138 *oacontrol_set = (cmd[offset + 1] != 0); 1139 } 1140 1141 /* 1142 * Check the value written to the register against the 1143 * allowed mask/value pair given in the whitelist entry. 1144 */ 1145 if (reg->mask) { 1146 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1147 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", 1148 reg_addr); 1149 return false; 1150 } 1151 1152 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1153 (offset + 2 > length || 1154 (cmd[offset + 1] & reg->mask) != reg->value)) { 1155 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", 1156 reg_addr); 1157 return false; 1158 } 1159 } 1160 } 1161 } 1162 1163 if (desc->flags & CMD_DESC_BITMASK) { 1164 int i; 1165 1166 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1167 u32 dword; 1168 1169 if (desc->bits[i].mask == 0) 1170 break; 1171 1172 if (desc->bits[i].condition_mask != 0) { 1173 u32 offset = 1174 desc->bits[i].condition_offset; 1175 u32 condition = cmd[offset] & 1176 desc->bits[i].condition_mask; 1177 1178 if (condition == 0) 1179 continue; 1180 } 1181 1182 dword = cmd[desc->bits[i].offset] & 1183 desc->bits[i].mask; 1184 1185 if (dword != desc->bits[i].expected) { 1186 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", 1187 *cmd, 1188 desc->bits[i].mask, 1189 desc->bits[i].expected, 1190 dword, ring->id); 1191 return false; 1192 } 1193 } 1194 } 1195 1196 return true; 1197 } 1198 1199 static int check_bbstart(struct intel_context *ctx, 1200 u32 *cmd, u64 offset, u32 length, 1201 u32 batch_len, 1202 u64 batch_start, 1203 u64 shadow_batch_start) 1204 { 1205 1206 u64 jump_offset, jump_target; 1207 u32 target_cmd_offset, target_cmd_index; 1208 1209 /* For igt compatibility on older platforms */ 1210 if (CMDPARSER_USES_GGTT(ctx->i915)) { 1211 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n"); 1212 return -EACCES; 1213 } 1214 1215 if (length != 3) { 1216 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n", 1217 length); 1218 return -EINVAL; 1219 } 1220 1221 jump_target = *(u64*)(cmd+1); 1222 jump_offset = jump_target - batch_start; 1223 1224 /* 1225 * Any underflow of jump_target is guaranteed to be outside the range 1226 * of a u32, so >= test catches both too large and too small 1227 */ 1228 if (jump_offset >= batch_len) { 1229 DRM_DEBUG("CMD: BB_START to 0x%"PRIx64" jumps out of BB\n", 1230 jump_target); 1231 return -EINVAL; 1232 } 1233 1234 /* 1235 * This cannot overflow a u32 because we already checked jump_offset 1236 * is within the BB, and the batch_len is a u32 1237 */ 1238 target_cmd_offset = lower_32_bits(jump_offset); 1239 target_cmd_index = target_cmd_offset / sizeof(u32); 1240 1241 *(u64*)(cmd + 1) = shadow_batch_start + target_cmd_offset; 1242 1243 if (target_cmd_index == offset) 1244 return 0; 1245 1246 if (ctx->jump_whitelist_cmds <= target_cmd_index) { 1247 DRM_DEBUG("CMD: Rejecting BB_START - truncated whitelist array\n"); 1248 return -EINVAL; 1249 } else if (!test_bit(target_cmd_index, ctx->jump_whitelist)) { 1250 DRM_DEBUG("CMD: BB_START to 0x%"PRIx64" not a previously executed cmd\n", 1251 jump_target); 1252 return -EINVAL; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static void init_whitelist(struct intel_context *ctx, u32 batch_len) 1259 { 1260 const u32 batch_cmds = DIV_ROUND_UP(batch_len, sizeof(u32)); 1261 const u32 exact_size = BITS_TO_LONGS(batch_cmds); 1262 u32 next_size = BITS_TO_LONGS(roundup_pow_of_two(batch_cmds)); 1263 unsigned long *next_whitelist; 1264 1265 if (CMDPARSER_USES_GGTT(ctx->i915)) 1266 return; 1267 1268 if (batch_cmds <= ctx->jump_whitelist_cmds) { 1269 bitmap_zero(ctx->jump_whitelist, batch_cmds); 1270 return; 1271 } 1272 1273 again: 1274 next_whitelist = kcalloc(next_size, sizeof(long), GFP_KERNEL); 1275 if (next_whitelist) { 1276 kfree(ctx->jump_whitelist); 1277 ctx->jump_whitelist = next_whitelist; 1278 ctx->jump_whitelist_cmds = 1279 next_size * BITS_PER_BYTE * sizeof(long); 1280 return; 1281 } 1282 1283 if (next_size > exact_size) { 1284 next_size = exact_size; 1285 goto again; 1286 } 1287 1288 DRM_DEBUG("CMD: Failed to extend whitelist. BB_START may be disallowed\n"); 1289 bitmap_zero(ctx->jump_whitelist, ctx->jump_whitelist_cmds); 1290 1291 return; 1292 } 1293 1294 #define LENGTH_BIAS 2 1295 1296 /** 1297 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 1298 * @ctx: the context in which the batch is to execute 1299 * @ring: the ring on which the batch is to execute 1300 * @batch_obj: the batch buffer in question 1301 * @user_batch_start: Canonical base address of original user batch 1302 * @batch_start_offset: byte offset in the batch at which execution starts 1303 * @batch_len: length of the commands in batch_obj 1304 * @shadow_batch_obj: copy of the batch buffer in question 1305 * @shadow_batch_start: Canonical base address of shadow_batch_obj 1306 * 1307 * Parses the specified batch buffer looking for privilege violations as 1308 * described in the overview. 1309 * 1310 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1311 * if the batch appears legal but should use hardware parsing 1312 */ 1313 int i915_parse_cmds(struct intel_context *ctx, 1314 struct intel_engine_cs *ring, 1315 struct drm_i915_gem_object *batch_obj, 1316 u64 user_batch_start, 1317 u32 batch_start_offset, 1318 u32 batch_len, 1319 struct drm_i915_gem_object *shadow_batch_obj, 1320 u64 shadow_batch_start) 1321 { 1322 u32 *cmd, *batch_base, *batch_end, offset = 0; 1323 static const struct drm_i915_cmd_descriptor zero_default_desc; 1324 struct drm_i915_cmd_descriptor default_desc = zero_default_desc; 1325 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ 1326 int ret = 0; 1327 1328 batch_base = copy_batch(shadow_batch_obj, batch_obj, 1329 batch_start_offset, batch_len); 1330 if (IS_ERR(batch_base)) { 1331 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); 1332 return PTR_ERR(batch_base); 1333 } 1334 1335 init_whitelist(ctx, batch_len); 1336 1337 /* 1338 * We use the batch length as size because the shadow object is as 1339 * large or larger and copy_batch() will write MI_NOPs to the extra 1340 * space. Parsing should be faster in some cases this way. 1341 */ 1342 batch_end = batch_base + (batch_len / sizeof(*batch_end)); 1343 1344 cmd = batch_base; 1345 while (cmd < batch_end) { 1346 const struct drm_i915_cmd_descriptor *desc; 1347 u32 length; 1348 1349 if (*cmd == MI_BATCH_BUFFER_END) 1350 break; 1351 1352 desc = find_cmd(ring, *cmd, &default_desc); 1353 if (!desc) { 1354 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1355 *cmd); 1356 ret = -EINVAL; 1357 break; 1358 } 1359 1360 if (desc->flags & CMD_DESC_FIXED) 1361 length = desc->length.fixed; 1362 else 1363 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1364 1365 if ((batch_end - cmd) < length) { 1366 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1367 *cmd, 1368 length, 1369 batch_end - cmd); 1370 ret = -EINVAL; 1371 break; 1372 } 1373 1374 if (!check_cmd(ring, desc, cmd, length, &oacontrol_set)) { 1375 ret = CMDPARSER_USES_GGTT(ring->dev) ? -EINVAL : -EACCES; 1376 break; 1377 } 1378 1379 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1380 ret = check_bbstart(ctx, cmd, offset, length, 1381 batch_len, user_batch_start, 1382 shadow_batch_start); 1383 break; 1384 } 1385 1386 if (ctx->jump_whitelist_cmds > offset) 1387 set_bit(offset, ctx->jump_whitelist); 1388 1389 cmd += length; 1390 offset += length; 1391 } 1392 1393 if (oacontrol_set) { 1394 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); 1395 ret = -EINVAL; 1396 } 1397 1398 if (cmd >= batch_end) { 1399 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1400 ret = -EINVAL; 1401 } 1402 1403 #ifdef __NetBSD__ 1404 uvm_unmap(kernel_map, (vaddr_t)batch_base, 1405 (vaddr_t)batch_base + roundup(batch_len, PAGE_SIZE)); 1406 #else 1407 vunmap(batch_base); 1408 #endif 1409 1410 return ret; 1411 } 1412 1413 /** 1414 * i915_cmd_parser_get_version() - get the cmd parser version number 1415 * 1416 * The cmd parser maintains a simple increasing integer version number suitable 1417 * for passing to userspace clients to determine what operations are permitted. 1418 * 1419 * Return: the current version number of the cmd parser 1420 */ 1421 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1422 { 1423 /* 1424 * Command parser version history 1425 * 1426 * 1. Initial version. Checks batches and reports violations, but leaves 1427 * hardware parsing enabled (so does not allow new use cases). 1428 * 2. Allow access to the MI_PREDICATE_SRC0 and 1429 * MI_PREDICATE_SRC1 registers. 1430 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1431 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1432 * 5. GPGPU dispatch compute indirect registers. 1433 * 10. Gen9 only - Supports the new ppgtt based BLIT parser 1434 */ 1435 return CMDPARSER_USES_GGTT(dev_priv) ? 5 : 10; 1436 } 1437