1 /* $NetBSD: drm_dp_helper.c,v 1.16 2021/12/19 12:41:54 riastradh Exp $ */ 2 3 /* 4 * Copyright © 2009 Keith Packard 5 * 6 * Permission to use, copy, modify, distribute, and sell this software and its 7 * documentation for any purpose is hereby granted without fee, provided that 8 * the above copyright notice appear in all copies and that both that copyright 9 * notice and this permission notice appear in supporting documentation, and 10 * that the name of the copyright holders not be used in advertising or 11 * publicity pertaining to distribution of the software without specific, 12 * written prior permission. The copyright holders make no representations 13 * about the suitability of this software for any purpose. It is provided "as 14 * is" without express or implied warranty. 15 * 16 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 17 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 18 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 19 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 20 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 21 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 22 * OF THIS SOFTWARE. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: drm_dp_helper.c,v 1.16 2021/12/19 12:41:54 riastradh Exp $"); 27 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/i2c.h> 31 #include <linux/init.h> 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_print.h> 39 #include <drm/drm_vblank.h> 40 #include <drm/drm_dp_mst_helper.h> 41 42 #include "drm_crtc_helper_internal.h" 43 44 #include <linux/nbsd-namespace.h> 45 46 /** 47 * DOC: dp helpers 48 * 49 * These functions contain some common logic and helpers at various abstraction 50 * levels to deal with Display Port sink devices and related things like DP aux 51 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 52 * blocks, ... 53 */ 54 55 /* Helpers for DP link training */ 56 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 57 { 58 return link_status[r - DP_LANE0_1_STATUS]; 59 } 60 61 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 62 int lane) 63 { 64 int i = DP_LANE0_1_STATUS + (lane >> 1); 65 int s = (lane & 1) * 4; 66 u8 l = dp_link_status(link_status, i); 67 return (l >> s) & 0xf; 68 } 69 70 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 71 int lane_count) 72 { 73 u8 lane_align; 74 u8 lane_status; 75 int lane; 76 77 lane_align = dp_link_status(link_status, 78 DP_LANE_ALIGN_STATUS_UPDATED); 79 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 80 return false; 81 for (lane = 0; lane < lane_count; lane++) { 82 lane_status = dp_get_lane_status(link_status, lane); 83 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 84 return false; 85 } 86 return true; 87 } 88 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 89 90 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 91 int lane_count) 92 { 93 int lane; 94 u8 lane_status; 95 96 for (lane = 0; lane < lane_count; lane++) { 97 lane_status = dp_get_lane_status(link_status, lane); 98 if ((lane_status & DP_LANE_CR_DONE) == 0) 99 return false; 100 } 101 return true; 102 } 103 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 104 105 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 106 int lane) 107 { 108 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 109 int s = ((lane & 1) ? 110 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 111 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 112 u8 l = dp_link_status(link_status, i); 113 114 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 115 } 116 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 117 118 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 119 int lane) 120 { 121 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 122 int s = ((lane & 1) ? 123 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 124 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 125 u8 l = dp_link_status(link_status, i); 126 127 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 128 } 129 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 130 131 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], 132 unsigned int lane) 133 { 134 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2; 135 u8 value = dp_link_status(link_status, offset); 136 137 return (value >> (lane << 1)) & 0x3; 138 } 139 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor); 140 141 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 142 { 143 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 144 DP_TRAINING_AUX_RD_MASK; 145 146 if (rd_interval > 4) 147 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", 148 rd_interval); 149 150 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 151 rd_interval = 100; 152 else 153 rd_interval *= 4 * USEC_PER_MSEC; 154 155 usleep_range(rd_interval, rd_interval * 2); 156 } 157 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 158 159 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 160 { 161 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 162 DP_TRAINING_AUX_RD_MASK; 163 164 if (rd_interval > 4) 165 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", 166 rd_interval); 167 168 if (rd_interval == 0) 169 rd_interval = 400; 170 else 171 rd_interval *= 4 * USEC_PER_MSEC; 172 173 usleep_range(rd_interval, rd_interval * 2); 174 } 175 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 176 177 u8 drm_dp_link_rate_to_bw_code(int link_rate) 178 { 179 /* Spec says link_bw = link_rate / 0.27Gbps */ 180 return link_rate / 27000; 181 } 182 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 183 184 int drm_dp_bw_code_to_link_rate(u8 link_bw) 185 { 186 /* Spec says link_rate = link_bw * 0.27Gbps */ 187 return link_bw * 27000; 188 } 189 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 190 191 #define AUX_RETRY_INTERVAL 500 /* us */ 192 193 static inline void 194 drm_dp_dump_access(const struct drm_dp_aux *aux, 195 u8 request, uint offset, void *buffer, int ret) 196 { 197 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 198 199 if (ret > 0) 200 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 201 aux->name, offset, arrow, ret, min(ret, 20), buffer); 202 else 203 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n", 204 aux->name, offset, arrow, ret); 205 } 206 207 /** 208 * DOC: dp helpers 209 * 210 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 211 * independent access to AUX functionality. Drivers can take advantage of 212 * this by filling in the fields of the drm_dp_aux structure. 213 * 214 * Transactions are described using a hardware-independent drm_dp_aux_msg 215 * structure, which is passed into a driver's .transfer() implementation. 216 * Both native and I2C-over-AUX transactions are supported. 217 */ 218 219 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 220 unsigned int offset, void *buffer, size_t size) 221 { 222 struct drm_dp_aux_msg msg; 223 unsigned int retry, native_reply; 224 int err = 0, ret = 0; 225 226 memset(&msg, 0, sizeof(msg)); 227 msg.address = offset; 228 msg.request = request; 229 msg.buffer = buffer; 230 msg.size = size; 231 232 mutex_lock(&aux->hw_mutex); 233 234 /* 235 * The specification doesn't give any recommendation on how often to 236 * retry native transactions. We used to retry 7 times like for 237 * aux i2c transactions but real world devices this wasn't 238 * sufficient, bump to 32 which makes Dell 4k monitors happier. 239 */ 240 for (retry = 0; retry < 32; retry++) { 241 if (ret != 0 && ret != -ETIMEDOUT) { 242 usleep_range(AUX_RETRY_INTERVAL, 243 AUX_RETRY_INTERVAL + 100); 244 } 245 246 ret = aux->transfer(aux, &msg); 247 if (ret >= 0) { 248 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 249 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 250 if (ret == size) 251 goto unlock; 252 253 ret = -EPROTO; 254 } else 255 ret = -EIO; 256 } 257 258 /* 259 * We want the error we return to be the error we received on 260 * the first transaction, since we may get a different error the 261 * next time we retry 262 */ 263 if (!err) 264 err = ret; 265 } 266 267 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err); 268 ret = err; 269 270 unlock: 271 mutex_unlock(&aux->hw_mutex); 272 return ret; 273 } 274 275 /** 276 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 277 * @aux: DisplayPort AUX channel (SST or MST) 278 * @offset: address of the (first) register to read 279 * @buffer: buffer to store the register values 280 * @size: number of bytes in @buffer 281 * 282 * Returns the number of bytes transferred on success, or a negative error 283 * code on failure. -EIO is returned if the request was NAKed by the sink or 284 * if the retry count was exceeded. If not all bytes were transferred, this 285 * function returns -EPROTO. Errors from the underlying AUX channel transfer 286 * function, with the exception of -EBUSY (which causes the transaction to 287 * be retried), are propagated to the caller. 288 */ 289 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 290 void *buffer, size_t size) 291 { 292 int ret; 293 294 /* 295 * HP ZR24w corrupts the first DPCD access after entering power save 296 * mode. Eg. on a read, the entire buffer will be filled with the same 297 * byte. Do a throw away read to avoid corrupting anything we care 298 * about. Afterwards things will work correctly until the monitor 299 * gets woken up and subsequently re-enters power save mode. 300 * 301 * The user pressing any button on the monitor is enough to wake it 302 * up, so there is no particularly good place to do the workaround. 303 * We just have to do it before any DPCD access and hope that the 304 * monitor doesn't power down exactly after the throw away read. 305 */ 306 if (!aux->is_remote) { 307 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, 308 buffer, 1); 309 if (ret != 1) 310 goto out; 311 } 312 313 if (aux->is_remote) 314 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 315 else 316 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 317 buffer, size); 318 319 out: 320 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 321 return ret; 322 } 323 EXPORT_SYMBOL(drm_dp_dpcd_read); 324 325 /** 326 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 327 * @aux: DisplayPort AUX channel (SST or MST) 328 * @offset: address of the (first) register to write 329 * @buffer: buffer containing the values to write 330 * @size: number of bytes in @buffer 331 * 332 * Returns the number of bytes transferred on success, or a negative error 333 * code on failure. -EIO is returned if the request was NAKed by the sink or 334 * if the retry count was exceeded. If not all bytes were transferred, this 335 * function returns -EPROTO. Errors from the underlying AUX channel transfer 336 * function, with the exception of -EBUSY (which causes the transaction to 337 * be retried), are propagated to the caller. 338 */ 339 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 340 void *buffer, size_t size) 341 { 342 int ret; 343 344 if (aux->is_remote) 345 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 346 else 347 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 348 buffer, size); 349 350 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 351 return ret; 352 } 353 EXPORT_SYMBOL(drm_dp_dpcd_write); 354 355 /** 356 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 357 * @aux: DisplayPort AUX channel 358 * @status: buffer to store the link status in (must be at least 6 bytes) 359 * 360 * Returns the number of bytes transferred on success or a negative error 361 * code on failure. 362 */ 363 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 364 u8 status[DP_LINK_STATUS_SIZE]) 365 { 366 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 367 DP_LINK_STATUS_SIZE); 368 } 369 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 370 371 /** 372 * drm_dp_downstream_max_clock() - extract branch device max 373 * pixel rate for legacy VGA 374 * converter or max TMDS clock 375 * rate for others 376 * @dpcd: DisplayPort configuration data 377 * @port_cap: port capabilities 378 * 379 * Returns max clock in kHz on success or 0 if max clock not defined 380 */ 381 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 382 const u8 port_cap[4]) 383 { 384 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 385 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 386 DP_DETAILED_CAP_INFO_AVAILABLE; 387 388 if (!detailed_cap_info) 389 return 0; 390 391 switch (type) { 392 case DP_DS_PORT_TYPE_VGA: 393 return port_cap[1] * 8 * 1000; 394 case DP_DS_PORT_TYPE_DVI: 395 case DP_DS_PORT_TYPE_HDMI: 396 case DP_DS_PORT_TYPE_DP_DUALMODE: 397 return port_cap[1] * 2500; 398 default: 399 return 0; 400 } 401 } 402 EXPORT_SYMBOL(drm_dp_downstream_max_clock); 403 404 /** 405 * drm_dp_downstream_max_bpc() - extract branch device max 406 * bits per component 407 * @dpcd: DisplayPort configuration data 408 * @port_cap: port capabilities 409 * 410 * Returns max bpc on success or 0 if max bpc not defined 411 */ 412 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 413 const u8 port_cap[4]) 414 { 415 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 416 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 417 DP_DETAILED_CAP_INFO_AVAILABLE; 418 int bpc; 419 420 if (!detailed_cap_info) 421 return 0; 422 423 switch (type) { 424 case DP_DS_PORT_TYPE_VGA: 425 case DP_DS_PORT_TYPE_DVI: 426 case DP_DS_PORT_TYPE_HDMI: 427 case DP_DS_PORT_TYPE_DP_DUALMODE: 428 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK; 429 430 switch (bpc) { 431 case DP_DS_8BPC: 432 return 8; 433 case DP_DS_10BPC: 434 return 10; 435 case DP_DS_12BPC: 436 return 12; 437 case DP_DS_16BPC: 438 return 16; 439 } 440 /* fall through */ 441 default: 442 return 0; 443 } 444 } 445 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 446 447 /** 448 * drm_dp_downstream_id() - identify branch device 449 * @aux: DisplayPort AUX channel 450 * @id: DisplayPort branch device id 451 * 452 * Returns branch device id on success or NULL on failure 453 */ 454 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 455 { 456 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 457 } 458 EXPORT_SYMBOL(drm_dp_downstream_id); 459 460 /** 461 * drm_dp_downstream_debug() - debug DP branch devices 462 * @m: pointer for debugfs file 463 * @dpcd: DisplayPort configuration data 464 * @port_cap: port capabilities 465 * @aux: DisplayPort AUX channel 466 * 467 */ 468 #ifndef __NetBSD__ 469 void drm_dp_downstream_debug(struct seq_file *m, 470 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 471 const u8 port_cap[4], struct drm_dp_aux *aux) 472 { 473 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 474 DP_DETAILED_CAP_INFO_AVAILABLE; 475 int clk; 476 int bpc; 477 char id[7]; 478 int len; 479 uint8_t rev[2]; 480 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 481 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 482 DP_DWN_STRM_PORT_PRESENT; 483 484 seq_printf(m, "\tDP branch device present: %s\n", 485 branch_device ? "yes" : "no"); 486 487 if (!branch_device) 488 return; 489 490 switch (type) { 491 case DP_DS_PORT_TYPE_DP: 492 seq_puts(m, "\t\tType: DisplayPort\n"); 493 break; 494 case DP_DS_PORT_TYPE_VGA: 495 seq_puts(m, "\t\tType: VGA\n"); 496 break; 497 case DP_DS_PORT_TYPE_DVI: 498 seq_puts(m, "\t\tType: DVI\n"); 499 break; 500 case DP_DS_PORT_TYPE_HDMI: 501 seq_puts(m, "\t\tType: HDMI\n"); 502 break; 503 case DP_DS_PORT_TYPE_NON_EDID: 504 seq_puts(m, "\t\tType: others without EDID support\n"); 505 break; 506 case DP_DS_PORT_TYPE_DP_DUALMODE: 507 seq_puts(m, "\t\tType: DP++\n"); 508 break; 509 case DP_DS_PORT_TYPE_WIRELESS: 510 seq_puts(m, "\t\tType: Wireless\n"); 511 break; 512 default: 513 seq_puts(m, "\t\tType: N/A\n"); 514 } 515 516 memset(id, 0, sizeof(id)); 517 drm_dp_downstream_id(aux, id); 518 seq_printf(m, "\t\tID: %s\n", id); 519 520 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 521 if (len > 0) 522 seq_printf(m, "\t\tHW: %d.%d\n", 523 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 524 525 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 526 if (len > 0) 527 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 528 529 if (detailed_cap_info) { 530 clk = drm_dp_downstream_max_clock(dpcd, port_cap); 531 532 if (clk > 0) { 533 if (type == DP_DS_PORT_TYPE_VGA) 534 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 535 else 536 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 537 } 538 539 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap); 540 541 if (bpc > 0) 542 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 543 } 544 } 545 EXPORT_SYMBOL(drm_dp_downstream_debug); 546 #endif 547 548 /* 549 * I2C-over-AUX implementation 550 */ 551 552 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 553 { 554 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 555 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 556 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 557 I2C_FUNC_10BIT_ADDR; 558 } 559 560 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 561 { 562 /* 563 * In case of i2c defer or short i2c ack reply to a write, 564 * we need to switch to WRITE_STATUS_UPDATE to drain the 565 * rest of the message 566 */ 567 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 568 msg->request &= DP_AUX_I2C_MOT; 569 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 570 } 571 } 572 573 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 574 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 575 #define AUX_STOP_LEN 4 576 #define AUX_CMD_LEN 4 577 #define AUX_ADDRESS_LEN 20 578 #define AUX_REPLY_PAD_LEN 4 579 #define AUX_LENGTH_LEN 8 580 581 /* 582 * Calculate the duration of the AUX request/reply in usec. Gives the 583 * "best" case estimate, ie. successful while as short as possible. 584 */ 585 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 586 { 587 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 588 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 589 590 if ((msg->request & DP_AUX_I2C_READ) == 0) 591 len += msg->size * 8; 592 593 return len; 594 } 595 596 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 597 { 598 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 599 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 600 601 /* 602 * For read we expect what was asked. For writes there will 603 * be 0 or 1 data bytes. Assume 0 for the "best" case. 604 */ 605 if (msg->request & DP_AUX_I2C_READ) 606 len += msg->size * 8; 607 608 return len; 609 } 610 611 #define I2C_START_LEN 1 612 #define I2C_STOP_LEN 1 613 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 614 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 615 616 /* 617 * Calculate the length of the i2c transfer in usec, assuming 618 * the i2c bus speed is as specified. Gives the the "worst" 619 * case estimate, ie. successful while as long as possible. 620 * Doesn't account the the "MOT" bit, and instead assumes each 621 * message includes a START, ADDRESS and STOP. Neither does it 622 * account for additional random variables such as clock stretching. 623 */ 624 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 625 int i2c_speed_khz) 626 { 627 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 628 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 629 msg->size * I2C_DATA_LEN + 630 I2C_STOP_LEN) * 1000, i2c_speed_khz); 631 } 632 633 /* 634 * Deterine how many retries should be attempted to successfully transfer 635 * the specified message, based on the estimated durations of the 636 * i2c and AUX transfers. 637 */ 638 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 639 int i2c_speed_khz) 640 { 641 int aux_time_us = drm_dp_aux_req_duration(msg) + 642 drm_dp_aux_reply_duration(msg); 643 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 644 645 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 646 } 647 648 /* 649 * FIXME currently assumes 10 kHz as some real world devices seem 650 * to require it. We should query/set the speed via DPCD if supported. 651 */ 652 static int dp_aux_i2c_speed_khz __read_mostly = 10; 653 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 654 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 655 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 656 657 /* 658 * Transfer a single I2C-over-AUX message and handle various error conditions, 659 * retrying the transaction as appropriate. It is assumed that the 660 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 661 * reply field. 662 * 663 * Returns bytes transferred on success, or a negative error code on failure. 664 */ 665 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 666 { 667 unsigned int retry, defer_i2c; 668 int ret; 669 /* 670 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 671 * is required to retry at least seven times upon receiving AUX_DEFER 672 * before giving up the AUX transaction. 673 * 674 * We also try to account for the i2c bus speed. 675 */ 676 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 677 678 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 679 ret = aux->transfer(aux, msg); 680 if (ret < 0) { 681 if (ret == -EBUSY) 682 continue; 683 684 /* 685 * While timeouts can be errors, they're usually normal 686 * behavior (for instance, when a driver tries to 687 * communicate with a non-existant DisplayPort device). 688 * Avoid spamming the kernel log with timeout errors. 689 */ 690 if (ret == -ETIMEDOUT) 691 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n"); 692 else 693 DRM_DEBUG_KMS("transaction failed: %d\n", ret); 694 695 return ret; 696 } 697 698 699 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 700 case DP_AUX_NATIVE_REPLY_ACK: 701 /* 702 * For I2C-over-AUX transactions this isn't enough, we 703 * need to check for the I2C ACK reply. 704 */ 705 break; 706 707 case DP_AUX_NATIVE_REPLY_NACK: 708 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size); 709 return -EREMOTEIO; 710 711 case DP_AUX_NATIVE_REPLY_DEFER: 712 DRM_DEBUG_KMS("native defer\n"); 713 /* 714 * We could check for I2C bit rate capabilities and if 715 * available adjust this interval. We could also be 716 * more careful with DP-to-legacy adapters where a 717 * long legacy cable may force very low I2C bit rates. 718 * 719 * For now just defer for long enough to hopefully be 720 * safe for all use-cases. 721 */ 722 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 723 continue; 724 725 default: 726 DRM_ERROR("invalid native reply %#04x\n", msg->reply); 727 return -EREMOTEIO; 728 } 729 730 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 731 case DP_AUX_I2C_REPLY_ACK: 732 /* 733 * Both native ACK and I2C ACK replies received. We 734 * can assume the transfer was successful. 735 */ 736 if (ret != msg->size) 737 drm_dp_i2c_msg_write_status_update(msg); 738 return ret; 739 740 case DP_AUX_I2C_REPLY_NACK: 741 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n", 742 ret, msg->size); 743 aux->i2c_nack_count++; 744 return -EREMOTEIO; 745 746 case DP_AUX_I2C_REPLY_DEFER: 747 DRM_DEBUG_KMS("I2C defer\n"); 748 /* DP Compliance Test 4.2.2.5 Requirement: 749 * Must have at least 7 retries for I2C defers on the 750 * transaction to pass this test 751 */ 752 aux->i2c_defer_count++; 753 if (defer_i2c < 7) 754 defer_i2c++; 755 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 756 drm_dp_i2c_msg_write_status_update(msg); 757 758 continue; 759 760 default: 761 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply); 762 return -EREMOTEIO; 763 } 764 } 765 766 DRM_DEBUG_KMS("too many retries, giving up\n"); 767 return -EREMOTEIO; 768 } 769 770 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 771 const struct i2c_msg *i2c_msg) 772 { 773 msg->request = (i2c_msg->flags & I2C_M_RD) ? 774 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 775 if (!(i2c_msg->flags & I2C_M_STOP)) 776 msg->request |= DP_AUX_I2C_MOT; 777 } 778 779 /* 780 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 781 * 782 * Returns an error code on failure, or a recommended transfer size on success. 783 */ 784 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 785 { 786 int err, ret = orig_msg->size; 787 struct drm_dp_aux_msg msg = *orig_msg; 788 789 while (msg.size > 0) { 790 err = drm_dp_i2c_do_msg(aux, &msg); 791 if (err <= 0) 792 return err == 0 ? -EPROTO : err; 793 794 if (err < msg.size && err < ret) { 795 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n", 796 msg.size, err); 797 ret = err; 798 } 799 800 msg.size -= err; 801 msg.buffer += err; 802 } 803 804 return ret; 805 } 806 807 /* 808 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 809 * packets to be as large as possible. If not, the I2C transactions never 810 * succeed. Hence the default is maximum. 811 */ 812 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 813 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 814 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 815 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 816 817 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 818 int num) 819 { 820 struct drm_dp_aux *aux = adapter->algo_data; 821 unsigned int i, j; 822 unsigned transfer_size; 823 struct drm_dp_aux_msg msg; 824 int err = 0; 825 826 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 827 828 memset(&msg, 0, sizeof(msg)); 829 830 for (i = 0; i < num; i++) { 831 msg.address = msgs[i].addr; 832 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 833 /* Send a bare address packet to start the transaction. 834 * Zero sized messages specify an address only (bare 835 * address) transaction. 836 */ 837 msg.buffer = NULL; 838 msg.size = 0; 839 err = drm_dp_i2c_do_msg(aux, &msg); 840 841 /* 842 * Reset msg.request in case in case it got 843 * changed into a WRITE_STATUS_UPDATE. 844 */ 845 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 846 847 if (err < 0) 848 break; 849 /* We want each transaction to be as large as possible, but 850 * we'll go to smaller sizes if the hardware gives us a 851 * short reply. 852 */ 853 transfer_size = dp_aux_i2c_transfer_size; 854 for (j = 0; j < msgs[i].len; j += msg.size) { 855 msg.buffer = msgs[i].buf + j; 856 msg.size = min(transfer_size, msgs[i].len - j); 857 858 err = drm_dp_i2c_drain_msg(aux, &msg); 859 860 /* 861 * Reset msg.request in case in case it got 862 * changed into a WRITE_STATUS_UPDATE. 863 */ 864 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 865 866 if (err < 0) 867 break; 868 transfer_size = err; 869 } 870 if (err < 0) 871 break; 872 } 873 if (err >= 0) 874 err = num; 875 /* Send a bare address packet to close out the transaction. 876 * Zero sized messages specify an address only (bare 877 * address) transaction. 878 */ 879 msg.request &= ~DP_AUX_I2C_MOT; 880 msg.buffer = NULL; 881 msg.size = 0; 882 (void)drm_dp_i2c_do_msg(aux, &msg); 883 884 return err; 885 } 886 887 static const struct i2c_algorithm drm_dp_i2c_algo = { 888 .functionality = drm_dp_i2c_functionality, 889 .master_xfer = drm_dp_i2c_xfer, 890 }; 891 892 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 893 { 894 return container_of(i2c, struct drm_dp_aux, ddc); 895 } 896 897 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 898 { 899 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 900 } 901 902 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 903 { 904 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 905 } 906 907 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 908 { 909 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 910 } 911 912 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 913 .lock_bus = lock_bus, 914 .trylock_bus = trylock_bus, 915 .unlock_bus = unlock_bus, 916 }; 917 918 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 919 { 920 u8 buf, count; 921 int ret; 922 923 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 924 if (ret < 0) 925 return ret; 926 927 WARN_ON(!(buf & DP_TEST_SINK_START)); 928 929 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 930 if (ret < 0) 931 return ret; 932 933 count = buf & DP_TEST_COUNT_MASK; 934 if (count == aux->crc_count) 935 return -EAGAIN; /* No CRC yet */ 936 937 aux->crc_count = count; 938 939 /* 940 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 941 * per component (RGB or CrYCb). 942 */ 943 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 944 if (ret < 0) 945 return ret; 946 947 return 0; 948 } 949 950 static void drm_dp_aux_crc_work(struct work_struct *work) 951 { 952 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 953 crc_work); 954 struct drm_crtc *crtc; 955 u8 crc_bytes[6]; 956 uint32_t crcs[3]; 957 int ret; 958 959 if (WARN_ON(!aux->crtc)) 960 return; 961 962 crtc = aux->crtc; 963 while (crtc->crc.opened) { 964 drm_crtc_wait_one_vblank(crtc); 965 if (!crtc->crc.opened) 966 break; 967 968 ret = drm_dp_aux_get_crc(aux, crc_bytes); 969 if (ret == -EAGAIN) { 970 usleep_range(1000, 2000); 971 ret = drm_dp_aux_get_crc(aux, crc_bytes); 972 } 973 974 if (ret == -EAGAIN) { 975 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n", 976 ret); 977 continue; 978 } else if (ret) { 979 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret); 980 continue; 981 } 982 983 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 984 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 985 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 986 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 987 } 988 } 989 990 /** 991 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 992 * @aux: DisplayPort AUX channel 993 * 994 * Used for remote aux channel in general. Merely initialize the crc work 995 * struct. 996 */ 997 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 998 { 999 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 1000 } 1001 EXPORT_SYMBOL(drm_dp_remote_aux_init); 1002 1003 /** 1004 * drm_dp_aux_init() - minimally initialise an aux channel 1005 * @aux: DisplayPort AUX channel 1006 * 1007 * If you need to use the drm_dp_aux's i2c adapter prior to registering it 1008 * with the outside world, call drm_dp_aux_init() first. You must still 1009 * call drm_dp_aux_register() once the connector has been registered to 1010 * allow userspace access to the auxiliary DP channel. 1011 */ 1012 void drm_dp_aux_init(struct drm_dp_aux *aux) 1013 { 1014 mutex_init(&aux->hw_mutex); 1015 mutex_init(&aux->cec.lock); 1016 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 1017 1018 aux->ddc.algo = &drm_dp_i2c_algo; 1019 aux->ddc.algo_data = aux; 1020 aux->ddc.retries = 3; 1021 1022 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 1023 } 1024 EXPORT_SYMBOL(drm_dp_aux_init); 1025 1026 /** 1027 * drm_dp_aux_fini() - undo what drm_dp_aux_init() does. 1028 * @aux: DisplayPort AUX channel 1029 */ 1030 void drm_dp_aux_fini(struct drm_dp_aux *aux) 1031 { 1032 mutex_destroy(&aux->cec.lock); 1033 mutex_destroy(&aux->hw_mutex); 1034 } 1035 EXPORT_SYMBOL(drm_dp_aux_fini); 1036 1037 /** 1038 * drm_dp_aux_register() - initialise and register aux channel 1039 * @aux: DisplayPort AUX channel 1040 * 1041 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. 1042 * This should only be called when the underlying &struct drm_connector is 1043 * initialiazed already. Therefore the best place to call this is from 1044 * &drm_connector_funcs.late_register. Not that drivers which don't follow this 1045 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled. 1046 * 1047 * Drivers which need to use the aux channel before that point (e.g. at driver 1048 * load time, before drm_dev_register() has been called) need to call 1049 * drm_dp_aux_init(). 1050 * 1051 * Returns 0 on success or a negative error code on failure. 1052 */ 1053 int drm_dp_aux_register(struct drm_dp_aux *aux) 1054 { 1055 int ret; 1056 1057 if (!aux->ddc.algo) 1058 drm_dp_aux_init(aux); 1059 1060 aux->ddc.class = I2C_CLASS_DDC; 1061 aux->ddc.owner = THIS_MODULE; 1062 aux->ddc.dev.parent = aux->dev; 1063 1064 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 1065 sizeof(aux->ddc.name)); 1066 1067 ret = drm_dp_aux_register_devnode(aux); 1068 if (ret) 1069 return ret; 1070 1071 ret = i2c_add_adapter(&aux->ddc); 1072 if (ret) { 1073 drm_dp_aux_unregister_devnode(aux); 1074 return ret; 1075 } 1076 1077 return 0; 1078 } 1079 EXPORT_SYMBOL(drm_dp_aux_register); 1080 1081 /** 1082 * drm_dp_aux_unregister() - unregister an AUX adapter 1083 * @aux: DisplayPort AUX channel 1084 */ 1085 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 1086 { 1087 drm_dp_aux_unregister_devnode(aux); 1088 i2c_del_adapter(&aux->ddc); 1089 drm_dp_aux_fini(aux); 1090 } 1091 EXPORT_SYMBOL(drm_dp_aux_unregister); 1092 1093 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 1094 1095 /** 1096 * drm_dp_psr_setup_time() - PSR setup in time usec 1097 * @psr_cap: PSR capabilities from DPCD 1098 * 1099 * Returns: 1100 * PSR setup time for the panel in microseconds, negative 1101 * error code on failure. 1102 */ 1103 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 1104 { 1105 static const u16 psr_setup_time_us[] = { 1106 PSR_SETUP_TIME(330), 1107 PSR_SETUP_TIME(275), 1108 PSR_SETUP_TIME(220), 1109 PSR_SETUP_TIME(165), 1110 PSR_SETUP_TIME(110), 1111 PSR_SETUP_TIME(55), 1112 PSR_SETUP_TIME(0), 1113 }; 1114 int i; 1115 1116 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 1117 if (i >= ARRAY_SIZE(psr_setup_time_us)) 1118 return -EINVAL; 1119 1120 return psr_setup_time_us[i]; 1121 } 1122 EXPORT_SYMBOL(drm_dp_psr_setup_time); 1123 1124 #undef PSR_SETUP_TIME 1125 1126 /** 1127 * drm_dp_start_crc() - start capture of frame CRCs 1128 * @aux: DisplayPort AUX channel 1129 * @crtc: CRTC displaying the frames whose CRCs are to be captured 1130 * 1131 * Returns 0 on success or a negative error code on failure. 1132 */ 1133 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 1134 { 1135 u8 buf; 1136 int ret; 1137 1138 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1139 if (ret < 0) 1140 return ret; 1141 1142 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 1143 if (ret < 0) 1144 return ret; 1145 1146 aux->crc_count = 0; 1147 aux->crtc = crtc; 1148 schedule_work(&aux->crc_work); 1149 1150 return 0; 1151 } 1152 EXPORT_SYMBOL(drm_dp_start_crc); 1153 1154 /** 1155 * drm_dp_stop_crc() - stop capture of frame CRCs 1156 * @aux: DisplayPort AUX channel 1157 * 1158 * Returns 0 on success or a negative error code on failure. 1159 */ 1160 int drm_dp_stop_crc(struct drm_dp_aux *aux) 1161 { 1162 u8 buf; 1163 int ret; 1164 1165 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1166 if (ret < 0) 1167 return ret; 1168 1169 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 1170 if (ret < 0) 1171 return ret; 1172 1173 flush_work(&aux->crc_work); 1174 aux->crtc = NULL; 1175 1176 return 0; 1177 } 1178 EXPORT_SYMBOL(drm_dp_stop_crc); 1179 1180 struct dpcd_quirk { 1181 u8 oui[3]; 1182 u8 device_id[6]; 1183 bool is_branch; 1184 u32 quirks; 1185 }; 1186 1187 #define OUI(first, second, third) { (first), (second), (third) } 1188 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 1189 { (first), (second), (third), (fourth), (fifth), (sixth) } 1190 1191 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 1192 1193 static const struct dpcd_quirk dpcd_quirk_list[] = { 1194 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 1195 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 1196 /* LG LP140WF6-SPM1 eDP panel */ 1197 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 1198 /* Apple panels need some additional handling to support PSR */ 1199 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 1200 /* CH7511 seems to leave SINK_COUNT zeroed */ 1201 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 1202 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 1203 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 1204 }; 1205 1206 #undef OUI 1207 1208 /* 1209 * Get a bit mask of DPCD quirks for the sink/branch device identified by 1210 * ident. The quirk data is shared but it's up to the drivers to act on the 1211 * data. 1212 * 1213 * For now, only the OUI (first three bytes) is used, but this may be extended 1214 * to device identification string and hardware/firmware revisions later. 1215 */ 1216 static u32 1217 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 1218 { 1219 const struct dpcd_quirk *quirk; 1220 u32 quirks = 0; 1221 int i; 1222 u8 any_device[] = DEVICE_ID_ANY; 1223 1224 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 1225 quirk = &dpcd_quirk_list[i]; 1226 1227 if (quirk->is_branch != is_branch) 1228 continue; 1229 1230 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 1231 continue; 1232 1233 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 1234 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 1235 continue; 1236 1237 quirks |= quirk->quirks; 1238 } 1239 1240 return quirks; 1241 } 1242 1243 #undef DEVICE_ID_ANY 1244 #undef DEVICE_ID 1245 1246 /** 1247 * drm_dp_read_desc - read sink/branch descriptor from DPCD 1248 * @aux: DisplayPort AUX channel 1249 * @desc: Device decriptor to fill from DPCD 1250 * @is_branch: true for branch devices, false for sink devices 1251 * 1252 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 1253 * identification. 1254 * 1255 * Returns 0 on success or a negative error code on failure. 1256 */ 1257 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 1258 bool is_branch) 1259 { 1260 struct drm_dp_dpcd_ident *ident = &desc->ident; 1261 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 1262 int ret, dev_id_len; 1263 1264 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 1265 if (ret < 0) 1266 return ret; 1267 1268 desc->quirks = drm_dp_get_quirks(ident, is_branch); 1269 1270 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); 1271 1272 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 1273 is_branch ? "branch" : "sink", 1274 (int)sizeof(ident->oui), ident->oui, 1275 dev_id_len, ident->device_id, 1276 ident->hw_rev >> 4, ident->hw_rev & 0xf, 1277 ident->sw_major_rev, ident->sw_minor_rev, 1278 desc->quirks); 1279 1280 return 0; 1281 } 1282 EXPORT_SYMBOL(drm_dp_read_desc); 1283 1284 /** 1285 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 1286 * supported by the DSC sink. 1287 * @dsc_dpcd: DSC capabilities from DPCD 1288 * @is_edp: true if its eDP, false for DP 1289 * 1290 * Read the slice capabilities DPCD register from DSC sink to get 1291 * the maximum slice count supported. This is used to populate 1292 * the DSC parameters in the &struct drm_dsc_config by the driver. 1293 * Driver creates an infoframe using these parameters to populate 1294 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 1295 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 1296 * 1297 * Returns: 1298 * Maximum slice count supported by DSC sink or 0 its invalid 1299 */ 1300 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 1301 bool is_edp) 1302 { 1303 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 1304 1305 if (is_edp) { 1306 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 1307 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 1308 return 4; 1309 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 1310 return 2; 1311 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 1312 return 1; 1313 } else { 1314 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 1315 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 1316 1317 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 1318 return 24; 1319 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 1320 return 20; 1321 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 1322 return 16; 1323 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 1324 return 12; 1325 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 1326 return 10; 1327 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 1328 return 8; 1329 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 1330 return 6; 1331 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 1332 return 4; 1333 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 1334 return 2; 1335 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 1336 return 1; 1337 } 1338 1339 return 0; 1340 } 1341 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 1342 1343 /** 1344 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 1345 * @dsc_dpcd: DSC capabilities from DPCD 1346 * 1347 * Read the DSC DPCD register to parse the line buffer depth in bits which is 1348 * number of bits of precision within the decoder line buffer supported by 1349 * the DSC sink. This is used to populate the DSC parameters in the 1350 * &struct drm_dsc_config by the driver. 1351 * Driver creates an infoframe using these parameters to populate 1352 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 1353 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 1354 * 1355 * Returns: 1356 * Line buffer depth supported by DSC panel or 0 its invalid 1357 */ 1358 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1359 { 1360 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 1361 1362 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 1363 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 1364 return 9; 1365 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 1366 return 10; 1367 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 1368 return 11; 1369 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 1370 return 12; 1371 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 1372 return 13; 1373 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 1374 return 14; 1375 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 1376 return 15; 1377 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 1378 return 16; 1379 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 1380 return 8; 1381 } 1382 1383 return 0; 1384 } 1385 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 1386 1387 /** 1388 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 1389 * values supported by the DSC sink. 1390 * @dsc_dpcd: DSC capabilities from DPCD 1391 * @dsc_bpc: An array to be filled by this helper with supported 1392 * input bpcs. 1393 * 1394 * Read the DSC DPCD from the sink device to parse the supported bits per 1395 * component values. This is used to populate the DSC parameters 1396 * in the &struct drm_dsc_config by the driver. 1397 * Driver creates an infoframe using these parameters to populate 1398 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 1399 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 1400 * 1401 * Returns: 1402 * Number of input BPC values parsed from the DPCD 1403 */ 1404 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 1405 u8 dsc_bpc[3]) 1406 { 1407 int num_bpc = 0; 1408 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 1409 1410 if (color_depth & DP_DSC_12_BPC) 1411 dsc_bpc[num_bpc++] = 12; 1412 if (color_depth & DP_DSC_10_BPC) 1413 dsc_bpc[num_bpc++] = 10; 1414 if (color_depth & DP_DSC_8_BPC) 1415 dsc_bpc[num_bpc++] = 8; 1416 1417 return num_bpc; 1418 } 1419 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 1420