1 /* $NetBSD: ast_mode.c,v 1.2 2018/08/27 04:58:23 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * Parts based on xf86-video-ast 6 * Copyright (c) 2005 ASPEED Technology Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * The above copyright notice and this permission notice (including the 25 * next paragraph) shall be included in all copies or substantial portions 26 * of the Software. 27 * 28 */ 29 /* 30 * Authors: Dave Airlie <airlied@redhat.com> 31 */ 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ast_mode.c,v 1.2 2018/08/27 04:58:23 riastradh Exp $"); 34 35 #include <linux/export.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include "ast_drv.h" 41 42 #include "ast_tables.h" 43 44 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 45 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 46 static int ast_cursor_set(struct drm_crtc *crtc, 47 struct drm_file *file_priv, 48 uint32_t handle, 49 uint32_t width, 50 uint32_t height); 51 static int ast_cursor_move(struct drm_crtc *crtc, 52 int x, int y); 53 54 static inline void ast_load_palette_index(struct ast_private *ast, 55 u8 index, u8 red, u8 green, 56 u8 blue) 57 { 58 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 59 ast_io_read8(ast, AST_IO_SEQ_PORT); 60 ast_io_write8(ast, AST_IO_DAC_DATA, red); 61 ast_io_read8(ast, AST_IO_SEQ_PORT); 62 ast_io_write8(ast, AST_IO_DAC_DATA, green); 63 ast_io_read8(ast, AST_IO_SEQ_PORT); 64 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 65 ast_io_read8(ast, AST_IO_SEQ_PORT); 66 } 67 68 static void ast_crtc_load_lut(struct drm_crtc *crtc) 69 { 70 struct ast_private *ast = crtc->dev->dev_private; 71 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 72 int i; 73 74 if (!crtc->enabled) 75 return; 76 77 for (i = 0; i < 256; i++) 78 ast_load_palette_index(ast, i, ast_crtc->lut_r[i], 79 ast_crtc->lut_g[i], ast_crtc->lut_b[i]); 80 } 81 82 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, 83 struct drm_display_mode *adjusted_mode, 84 struct ast_vbios_mode_info *vbios_mode) 85 { 86 struct ast_private *ast = crtc->dev->dev_private; 87 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 88 u32 hborder, vborder; 89 bool check_sync; 90 struct ast_vbios_enhtable *best = NULL; 91 92 switch (crtc->primary->fb->bits_per_pixel) { 93 case 8: 94 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 95 color_index = VGAModeIndex - 1; 96 break; 97 case 16: 98 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 99 color_index = HiCModeIndex; 100 break; 101 case 24: 102 case 32: 103 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 104 color_index = TrueCModeIndex; 105 break; 106 default: 107 return false; 108 } 109 110 switch (crtc->mode.crtc_hdisplay) { 111 case 640: 112 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 113 break; 114 case 800: 115 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 116 break; 117 case 1024: 118 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 119 break; 120 case 1280: 121 if (crtc->mode.crtc_vdisplay == 800) 122 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 123 else 124 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 125 break; 126 case 1360: 127 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 128 break; 129 case 1440: 130 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 131 break; 132 case 1600: 133 if (crtc->mode.crtc_vdisplay == 900) 134 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 135 else 136 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 137 break; 138 case 1680: 139 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 140 break; 141 case 1920: 142 if (crtc->mode.crtc_vdisplay == 1080) 143 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 144 else 145 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 146 break; 147 default: 148 return false; 149 } 150 151 refresh_rate = drm_mode_vrefresh(mode); 152 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 153 do { 154 struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 155 156 while (loop->refresh_rate != 0xff) { 157 if ((check_sync) && 158 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 159 (loop->flags & PVSync)) || 160 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 161 (loop->flags & NVSync)) || 162 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 163 (loop->flags & PHSync)) || 164 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 165 (loop->flags & NHSync)))) { 166 loop++; 167 continue; 168 } 169 if (loop->refresh_rate <= refresh_rate 170 && (!best || loop->refresh_rate > best->refresh_rate)) 171 best = loop; 172 loop++; 173 } 174 if (best || !check_sync) 175 break; 176 check_sync = 0; 177 } while (1); 178 if (best) 179 vbios_mode->enh_table = best; 180 181 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 182 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 183 184 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 185 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 186 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 187 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 188 vbios_mode->enh_table->hfp; 189 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 190 vbios_mode->enh_table->hfp + 191 vbios_mode->enh_table->hsync); 192 193 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 194 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 195 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 196 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 197 vbios_mode->enh_table->vfp; 198 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 199 vbios_mode->enh_table->vfp + 200 vbios_mode->enh_table->vsync); 201 202 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 203 mode_id = vbios_mode->enh_table->mode_id; 204 205 if (ast->chip == AST1180) { 206 /* TODO 1180 */ 207 } else { 208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); 209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 211 212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 213 if (vbios_mode->enh_table->flags & NewModeInfo) { 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel); 216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 219 220 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 221 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 222 } 223 } 224 225 return true; 226 227 228 } 229 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 230 struct ast_vbios_mode_info *vbios_mode) 231 { 232 struct ast_private *ast = crtc->dev->dev_private; 233 struct ast_vbios_stdtable *stdtable; 234 u32 i; 235 u8 jreg; 236 237 stdtable = vbios_mode->std_table; 238 239 jreg = stdtable->misc; 240 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 241 242 /* Set SEQ */ 243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 244 for (i = 0; i < 4; i++) { 245 jreg = stdtable->seq[i]; 246 if (!i) 247 jreg |= 0x20; 248 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 249 } 250 251 /* Set CRTC */ 252 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 253 for (i = 0; i < 25; i++) 254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 255 256 /* set AR */ 257 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 258 for (i = 0; i < 20; i++) { 259 jreg = stdtable->ar[i]; 260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 262 } 263 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 265 266 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 267 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 268 269 /* Set GR */ 270 for (i = 0; i < 9; i++) 271 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 272 } 273 274 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 275 struct ast_vbios_mode_info *vbios_mode) 276 { 277 struct ast_private *ast = crtc->dev->dev_private; 278 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 279 u16 temp; 280 281 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 282 283 temp = (mode->crtc_htotal >> 3) - 5; 284 if (temp & 0x100) 285 jregAC |= 0x01; /* HT D[8] */ 286 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 287 288 temp = (mode->crtc_hdisplay >> 3) - 1; 289 if (temp & 0x100) 290 jregAC |= 0x04; /* HDE D[8] */ 291 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 292 293 temp = (mode->crtc_hblank_start >> 3) - 1; 294 if (temp & 0x100) 295 jregAC |= 0x10; /* HBS D[8] */ 296 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 297 298 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 299 if (temp & 0x20) 300 jreg05 |= 0x80; /* HBE D[5] */ 301 if (temp & 0x40) 302 jregAD |= 0x01; /* HBE D[5] */ 303 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 304 305 temp = (mode->crtc_hsync_start >> 3) - 1; 306 if (temp & 0x100) 307 jregAC |= 0x40; /* HRS D[5] */ 308 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 309 310 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f; 311 if (temp & 0x20) 312 jregAD |= 0x04; /* HRE D[5] */ 313 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 314 315 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 316 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 317 318 /* vert timings */ 319 temp = (mode->crtc_vtotal) - 2; 320 if (temp & 0x100) 321 jreg07 |= 0x01; 322 if (temp & 0x200) 323 jreg07 |= 0x20; 324 if (temp & 0x400) 325 jregAE |= 0x01; 326 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 327 328 temp = (mode->crtc_vsync_start) - 1; 329 if (temp & 0x100) 330 jreg07 |= 0x04; 331 if (temp & 0x200) 332 jreg07 |= 0x80; 333 if (temp & 0x400) 334 jregAE |= 0x08; 335 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 336 337 temp = (mode->crtc_vsync_end - 1) & 0x3f; 338 if (temp & 0x10) 339 jregAE |= 0x20; 340 if (temp & 0x20) 341 jregAE |= 0x40; 342 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 343 344 temp = mode->crtc_vdisplay - 1; 345 if (temp & 0x100) 346 jreg07 |= 0x02; 347 if (temp & 0x200) 348 jreg07 |= 0x40; 349 if (temp & 0x400) 350 jregAE |= 0x02; 351 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 352 353 temp = mode->crtc_vblank_start - 1; 354 if (temp & 0x100) 355 jreg07 |= 0x08; 356 if (temp & 0x200) 357 jreg09 |= 0x20; 358 if (temp & 0x400) 359 jregAE |= 0x04; 360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 361 362 temp = mode->crtc_vblank_end - 1; 363 if (temp & 0x100) 364 jregAE |= 0x10; 365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 366 367 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 368 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 370 371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 372 } 373 374 static void ast_set_offset_reg(struct drm_crtc *crtc) 375 { 376 struct ast_private *ast = crtc->dev->dev_private; 377 378 u16 offset; 379 380 offset = crtc->primary->fb->pitches[0] >> 3; 381 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 382 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 383 } 384 385 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, 386 struct ast_vbios_mode_info *vbios_mode) 387 { 388 struct ast_private *ast = dev->dev_private; 389 struct ast_vbios_dclk_info *clk_info; 390 391 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 392 393 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 394 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 395 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 396 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4)); 397 } 398 399 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 400 struct ast_vbios_mode_info *vbios_mode) 401 { 402 struct ast_private *ast = crtc->dev->dev_private; 403 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 404 405 switch (crtc->primary->fb->bits_per_pixel) { 406 case 8: 407 jregA0 = 0x70; 408 jregA3 = 0x01; 409 jregA8 = 0x00; 410 break; 411 case 15: 412 case 16: 413 jregA0 = 0x70; 414 jregA3 = 0x04; 415 jregA8 = 0x02; 416 break; 417 case 32: 418 jregA0 = 0x70; 419 jregA3 = 0x08; 420 jregA8 = 0x02; 421 break; 422 } 423 424 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 425 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 426 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 427 428 /* Set Threshold */ 429 if (ast->chip == AST2300 || ast->chip == AST2400) { 430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 432 } else if (ast->chip == AST2100 || 433 ast->chip == AST1100 || 434 ast->chip == AST2200 || 435 ast->chip == AST2150) { 436 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 437 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 438 } else { 439 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 440 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 441 } 442 } 443 444 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, 445 struct ast_vbios_mode_info *vbios_mode) 446 { 447 struct ast_private *ast = dev->dev_private; 448 u8 jreg; 449 450 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 451 jreg &= ~0xC0; 452 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 453 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 454 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 455 } 456 457 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 458 struct ast_vbios_mode_info *vbios_mode) 459 { 460 switch (crtc->primary->fb->bits_per_pixel) { 461 case 8: 462 break; 463 default: 464 return false; 465 } 466 return true; 467 } 468 469 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset) 470 { 471 struct ast_private *ast = crtc->dev->dev_private; 472 u32 addr; 473 474 addr = offset >> 2; 475 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 476 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 477 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 478 479 } 480 481 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 482 { 483 struct ast_private *ast = crtc->dev->dev_private; 484 485 if (ast->chip == AST1180) 486 return; 487 488 switch (mode) { 489 case DRM_MODE_DPMS_ON: 490 case DRM_MODE_DPMS_STANDBY: 491 case DRM_MODE_DPMS_SUSPEND: 492 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 493 if (ast->tx_chip_type == AST_TX_DP501) 494 ast_set_dp501_video_output(crtc->dev, 1); 495 ast_crtc_load_lut(crtc); 496 break; 497 case DRM_MODE_DPMS_OFF: 498 if (ast->tx_chip_type == AST_TX_DP501) 499 ast_set_dp501_video_output(crtc->dev, 0); 500 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 501 break; 502 } 503 } 504 505 static bool ast_crtc_mode_fixup(struct drm_crtc *crtc, 506 const struct drm_display_mode *mode, 507 struct drm_display_mode *adjusted_mode) 508 { 509 return true; 510 } 511 512 /* ast is different - we will force move buffers out of VRAM */ 513 static int ast_crtc_do_set_base(struct drm_crtc *crtc, 514 struct drm_framebuffer *fb, 515 int x, int y, int atomic) 516 { 517 struct ast_private *ast = crtc->dev->dev_private; 518 struct drm_gem_object *obj; 519 struct ast_framebuffer *ast_fb; 520 struct ast_bo *bo; 521 int ret; 522 u64 gpu_addr; 523 524 /* push the previous fb to system ram */ 525 if (!atomic && fb) { 526 ast_fb = to_ast_framebuffer(fb); 527 obj = ast_fb->obj; 528 bo = gem_to_ast_bo(obj); 529 ret = ast_bo_reserve(bo, false); 530 if (ret) 531 return ret; 532 ast_bo_push_sysram(bo); 533 ast_bo_unreserve(bo); 534 } 535 536 ast_fb = to_ast_framebuffer(crtc->primary->fb); 537 obj = ast_fb->obj; 538 bo = gem_to_ast_bo(obj); 539 540 ret = ast_bo_reserve(bo, false); 541 if (ret) 542 return ret; 543 544 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 545 if (ret) { 546 ast_bo_unreserve(bo); 547 return ret; 548 } 549 550 if (&ast->fbdev->afb == ast_fb) { 551 /* if pushing console in kmap it */ 552 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 553 if (ret) 554 DRM_ERROR("failed to kmap fbcon\n"); 555 else 556 ast_fbdev_set_base(ast, gpu_addr); 557 } 558 ast_bo_unreserve(bo); 559 560 ast_set_start_address_crt1(crtc, (u32)gpu_addr); 561 562 return 0; 563 } 564 565 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 566 struct drm_framebuffer *old_fb) 567 { 568 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); 569 } 570 571 static int ast_crtc_mode_set(struct drm_crtc *crtc, 572 struct drm_display_mode *mode, 573 struct drm_display_mode *adjusted_mode, 574 int x, int y, 575 struct drm_framebuffer *old_fb) 576 { 577 struct drm_device *dev = crtc->dev; 578 struct ast_private *ast = crtc->dev->dev_private; 579 struct ast_vbios_mode_info vbios_mode; 580 bool ret; 581 if (ast->chip == AST1180) { 582 DRM_ERROR("AST 1180 modesetting not supported\n"); 583 return -EINVAL; 584 } 585 586 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); 587 if (ret == false) 588 return -EINVAL; 589 ast_open_key(ast); 590 591 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); 592 593 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); 594 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); 595 ast_set_offset_reg(crtc); 596 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); 597 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); 598 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); 599 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); 600 601 ast_crtc_mode_set_base(crtc, x, y, old_fb); 602 603 return 0; 604 } 605 606 static void ast_crtc_disable(struct drm_crtc *crtc) 607 { 608 609 } 610 611 static void ast_crtc_prepare(struct drm_crtc *crtc) 612 { 613 614 } 615 616 static void ast_crtc_commit(struct drm_crtc *crtc) 617 { 618 struct ast_private *ast = crtc->dev->dev_private; 619 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 620 } 621 622 623 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 624 .dpms = ast_crtc_dpms, 625 .mode_fixup = ast_crtc_mode_fixup, 626 .mode_set = ast_crtc_mode_set, 627 .mode_set_base = ast_crtc_mode_set_base, 628 .disable = ast_crtc_disable, 629 .load_lut = ast_crtc_load_lut, 630 .prepare = ast_crtc_prepare, 631 .commit = ast_crtc_commit, 632 633 }; 634 635 static void ast_crtc_reset(struct drm_crtc *crtc) 636 { 637 638 } 639 640 static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 641 u16 *blue, uint32_t start, uint32_t size) 642 { 643 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 644 int end = (start + size > 256) ? 256 : start + size, i; 645 646 /* userspace palettes are always correct as is */ 647 for (i = start; i < end; i++) { 648 ast_crtc->lut_r[i] = red[i] >> 8; 649 ast_crtc->lut_g[i] = green[i] >> 8; 650 ast_crtc->lut_b[i] = blue[i] >> 8; 651 } 652 ast_crtc_load_lut(crtc); 653 } 654 655 656 static void ast_crtc_destroy(struct drm_crtc *crtc) 657 { 658 drm_crtc_cleanup(crtc); 659 kfree(crtc); 660 } 661 662 static const struct drm_crtc_funcs ast_crtc_funcs = { 663 .cursor_set = ast_cursor_set, 664 .cursor_move = ast_cursor_move, 665 .reset = ast_crtc_reset, 666 .set_config = drm_crtc_helper_set_config, 667 .gamma_set = ast_crtc_gamma_set, 668 .destroy = ast_crtc_destroy, 669 }; 670 671 static int ast_crtc_init(struct drm_device *dev) 672 { 673 struct ast_crtc *crtc; 674 int i; 675 676 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 677 if (!crtc) 678 return -ENOMEM; 679 680 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); 681 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 682 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 683 684 for (i = 0; i < 256; i++) { 685 crtc->lut_r[i] = i; 686 crtc->lut_g[i] = i; 687 crtc->lut_b[i] = i; 688 } 689 return 0; 690 } 691 692 static void ast_encoder_destroy(struct drm_encoder *encoder) 693 { 694 drm_encoder_cleanup(encoder); 695 kfree(encoder); 696 } 697 698 699 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector) 700 { 701 int enc_id = connector->encoder_ids[0]; 702 /* pick the encoder ids */ 703 if (enc_id) 704 return drm_encoder_find(connector->dev, enc_id); 705 return NULL; 706 } 707 708 709 static const struct drm_encoder_funcs ast_enc_funcs = { 710 .destroy = ast_encoder_destroy, 711 }; 712 713 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) 714 { 715 716 } 717 718 static bool ast_mode_fixup(struct drm_encoder *encoder, 719 const struct drm_display_mode *mode, 720 struct drm_display_mode *adjusted_mode) 721 { 722 return true; 723 } 724 725 static void ast_encoder_mode_set(struct drm_encoder *encoder, 726 struct drm_display_mode *mode, 727 struct drm_display_mode *adjusted_mode) 728 { 729 } 730 731 static void ast_encoder_prepare(struct drm_encoder *encoder) 732 { 733 734 } 735 736 static void ast_encoder_commit(struct drm_encoder *encoder) 737 { 738 739 } 740 741 742 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { 743 .dpms = ast_encoder_dpms, 744 .mode_fixup = ast_mode_fixup, 745 .prepare = ast_encoder_prepare, 746 .commit = ast_encoder_commit, 747 .mode_set = ast_encoder_mode_set, 748 }; 749 750 static int ast_encoder_init(struct drm_device *dev) 751 { 752 struct ast_encoder *ast_encoder; 753 754 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL); 755 if (!ast_encoder) 756 return -ENOMEM; 757 758 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, 759 DRM_MODE_ENCODER_DAC); 760 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); 761 762 ast_encoder->base.possible_crtcs = 1; 763 return 0; 764 } 765 766 static int ast_get_modes(struct drm_connector *connector) 767 { 768 struct ast_connector *ast_connector = to_ast_connector(connector); 769 struct ast_private *ast = connector->dev->dev_private; 770 struct edid *edid; 771 int ret; 772 bool flags = false; 773 if (ast->tx_chip_type == AST_TX_DP501) { 774 ast->dp501_maxclk = 0xff; 775 edid = kmalloc(128, GFP_KERNEL); 776 if (!edid) 777 return -ENOMEM; 778 779 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 780 if (flags) 781 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 782 else 783 kfree(edid); 784 } 785 if (!flags) 786 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 787 if (edid) { 788 drm_mode_connector_update_edid_property(&ast_connector->base, edid); 789 ret = drm_add_edid_modes(connector, edid); 790 kfree(edid); 791 return ret; 792 } else 793 drm_mode_connector_update_edid_property(&ast_connector->base, NULL); 794 return 0; 795 } 796 797 static int ast_mode_valid(struct drm_connector *connector, 798 struct drm_display_mode *mode) 799 { 800 struct ast_private *ast = connector->dev->dev_private; 801 int flags = MODE_NOMODE; 802 uint32_t jtemp; 803 804 if (ast->support_wide_screen) { 805 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 806 return MODE_OK; 807 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 808 return MODE_OK; 809 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 810 return MODE_OK; 811 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 812 return MODE_OK; 813 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 814 return MODE_OK; 815 816 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) { 817 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 818 return MODE_OK; 819 820 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 821 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 822 if (jtemp & 0x01) 823 return MODE_NOMODE; 824 else 825 return MODE_OK; 826 } 827 } 828 } 829 switch (mode->hdisplay) { 830 case 640: 831 if (mode->vdisplay == 480) flags = MODE_OK; 832 break; 833 case 800: 834 if (mode->vdisplay == 600) flags = MODE_OK; 835 break; 836 case 1024: 837 if (mode->vdisplay == 768) flags = MODE_OK; 838 break; 839 case 1280: 840 if (mode->vdisplay == 1024) flags = MODE_OK; 841 break; 842 case 1600: 843 if (mode->vdisplay == 1200) flags = MODE_OK; 844 break; 845 default: 846 return flags; 847 } 848 849 return flags; 850 } 851 852 static void ast_connector_destroy(struct drm_connector *connector) 853 { 854 struct ast_connector *ast_connector = to_ast_connector(connector); 855 ast_i2c_destroy(ast_connector->i2c); 856 drm_connector_unregister(connector); 857 drm_connector_cleanup(connector); 858 kfree(connector); 859 } 860 861 static enum drm_connector_status 862 ast_connector_detect(struct drm_connector *connector, bool force) 863 { 864 return connector_status_connected; 865 } 866 867 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 868 .mode_valid = ast_mode_valid, 869 .get_modes = ast_get_modes, 870 .best_encoder = ast_best_single_encoder, 871 }; 872 873 static const struct drm_connector_funcs ast_connector_funcs = { 874 .dpms = drm_helper_connector_dpms, 875 .detect = ast_connector_detect, 876 .fill_modes = drm_helper_probe_single_connector_modes, 877 .destroy = ast_connector_destroy, 878 }; 879 880 static int ast_connector_init(struct drm_device *dev) 881 { 882 struct ast_connector *ast_connector; 883 struct drm_connector *connector; 884 struct drm_encoder *encoder; 885 886 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 887 if (!ast_connector) 888 return -ENOMEM; 889 890 connector = &ast_connector->base; 891 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA); 892 893 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 894 895 connector->interlace_allowed = 0; 896 connector->doublescan_allowed = 0; 897 898 drm_connector_register(connector); 899 900 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 901 902 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 903 drm_mode_connector_attach_encoder(connector, encoder); 904 905 ast_connector->i2c = ast_i2c_create(dev); 906 if (!ast_connector->i2c) 907 DRM_ERROR("failed to add ddc bus for connector\n"); 908 909 return 0; 910 } 911 912 /* allocate cursor cache and pin at start of VRAM */ 913 static int ast_cursor_init(struct drm_device *dev) 914 { 915 struct ast_private *ast = dev->dev_private; 916 int size; 917 int ret; 918 struct drm_gem_object *obj; 919 struct ast_bo *bo; 920 uint64_t gpu_addr; 921 922 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM; 923 924 ret = ast_gem_create(dev, size, true, &obj); 925 if (ret) 926 return ret; 927 bo = gem_to_ast_bo(obj); 928 ret = ast_bo_reserve(bo, false); 929 if (unlikely(ret != 0)) 930 goto fail; 931 932 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 933 ast_bo_unreserve(bo); 934 if (ret) 935 goto fail; 936 937 /* kmap the object */ 938 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap); 939 if (ret) 940 goto fail; 941 942 ast->cursor_cache = obj; 943 ast->cursor_cache_gpu_addr = gpu_addr; 944 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 945 return 0; 946 fail: 947 return ret; 948 } 949 950 static void ast_cursor_fini(struct drm_device *dev) 951 { 952 struct ast_private *ast = dev->dev_private; 953 ttm_bo_kunmap(&ast->cache_kmap); 954 drm_gem_object_unreference_unlocked(ast->cursor_cache); 955 } 956 957 int ast_mode_init(struct drm_device *dev) 958 { 959 ast_cursor_init(dev); 960 ast_crtc_init(dev); 961 ast_encoder_init(dev); 962 ast_connector_init(dev); 963 return 0; 964 } 965 966 void ast_mode_fini(struct drm_device *dev) 967 { 968 ast_cursor_fini(dev); 969 } 970 971 static int get_clock(void *i2c_priv) 972 { 973 struct ast_i2c_chan *i2c = i2c_priv; 974 struct ast_private *ast = i2c->dev->dev_private; 975 uint32_t val; 976 977 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4; 978 return val & 1 ? 1 : 0; 979 } 980 981 static int get_data(void *i2c_priv) 982 { 983 struct ast_i2c_chan *i2c = i2c_priv; 984 struct ast_private *ast = i2c->dev->dev_private; 985 uint32_t val; 986 987 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5; 988 return val & 1 ? 1 : 0; 989 } 990 991 static void set_clock(void *i2c_priv, int clock) 992 { 993 struct ast_i2c_chan *i2c = i2c_priv; 994 struct ast_private *ast = i2c->dev->dev_private; 995 int i; 996 u8 ujcrb7, jtemp; 997 998 for (i = 0; i < 0x10000; i++) { 999 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1000 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7); 1001 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1002 if (ujcrb7 == jtemp) 1003 break; 1004 } 1005 } 1006 1007 static void set_data(void *i2c_priv, int data) 1008 { 1009 struct ast_i2c_chan *i2c = i2c_priv; 1010 struct ast_private *ast = i2c->dev->dev_private; 1011 int i; 1012 u8 ujcrb7, jtemp; 1013 1014 for (i = 0; i < 0x10000; i++) { 1015 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1016 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7); 1017 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1018 if (ujcrb7 == jtemp) 1019 break; 1020 } 1021 } 1022 1023 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1024 { 1025 struct ast_i2c_chan *i2c; 1026 int ret; 1027 1028 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1029 if (!i2c) 1030 return NULL; 1031 1032 i2c->adapter.owner = THIS_MODULE; 1033 i2c->adapter.class = I2C_CLASS_DDC; 1034 i2c->adapter.dev.parent = &dev->pdev->dev; 1035 i2c->dev = dev; 1036 i2c_set_adapdata(&i2c->adapter, i2c); 1037 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1038 "AST i2c bit bus"); 1039 i2c->adapter.algo_data = &i2c->bit; 1040 1041 i2c->bit.udelay = 20; 1042 i2c->bit.timeout = 2; 1043 i2c->bit.data = i2c; 1044 i2c->bit.setsda = set_data; 1045 i2c->bit.setscl = set_clock; 1046 i2c->bit.getsda = get_data; 1047 i2c->bit.getscl = get_clock; 1048 ret = i2c_bit_add_bus(&i2c->adapter); 1049 if (ret) { 1050 DRM_ERROR("Failed to register bit i2c\n"); 1051 goto out_free; 1052 } 1053 1054 return i2c; 1055 out_free: 1056 kfree(i2c); 1057 return NULL; 1058 } 1059 1060 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1061 { 1062 if (!i2c) 1063 return; 1064 i2c_del_adapter(&i2c->adapter); 1065 kfree(i2c); 1066 } 1067 1068 static void ast_show_cursor(struct drm_crtc *crtc) 1069 { 1070 struct ast_private *ast = crtc->dev->dev_private; 1071 u8 jreg; 1072 1073 jreg = 0x2; 1074 /* enable ARGB cursor */ 1075 jreg |= 1; 1076 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1077 } 1078 1079 static void ast_hide_cursor(struct drm_crtc *crtc) 1080 { 1081 struct ast_private *ast = crtc->dev->dev_private; 1082 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 1083 } 1084 1085 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1086 { 1087 union { 1088 u32 ul; 1089 u8 b[4]; 1090 } srcdata32[2], data32; 1091 union { 1092 u16 us; 1093 u8 b[2]; 1094 } data16; 1095 u32 csum = 0; 1096 s32 alpha_dst_delta, last_alpha_dst_delta; 1097 u8 *srcxor, *dstxor; 1098 int i, j; 1099 u32 per_pixel_copy, two_pixel_copy; 1100 1101 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1102 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1103 1104 srcxor = src; 1105 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1106 per_pixel_copy = width & 1; 1107 two_pixel_copy = width >> 1; 1108 1109 for (j = 0; j < height; j++) { 1110 for (i = 0; i < two_pixel_copy; i++) { 1111 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1112 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1113 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1114 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1115 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1116 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1117 1118 writel(data32.ul, dstxor); 1119 csum += data32.ul; 1120 1121 dstxor += 4; 1122 srcxor += 8; 1123 1124 } 1125 1126 for (i = 0; i < per_pixel_copy; i++) { 1127 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1128 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1129 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1130 writew(data16.us, dstxor); 1131 csum += (u32)data16.us; 1132 1133 dstxor += 2; 1134 srcxor += 4; 1135 } 1136 dstxor += last_alpha_dst_delta; 1137 } 1138 return csum; 1139 } 1140 1141 static int ast_cursor_set(struct drm_crtc *crtc, 1142 struct drm_file *file_priv, 1143 uint32_t handle, 1144 uint32_t width, 1145 uint32_t height) 1146 { 1147 struct ast_private *ast = crtc->dev->dev_private; 1148 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1149 struct drm_gem_object *obj; 1150 struct ast_bo *bo; 1151 uint64_t gpu_addr; 1152 u32 csum; 1153 int ret; 1154 struct ttm_bo_kmap_obj uobj_map; 1155 u8 *src, *dst; 1156 bool src_isiomem, dst_isiomem; 1157 if (!handle) { 1158 ast_hide_cursor(crtc); 1159 return 0; 1160 } 1161 1162 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) 1163 return -EINVAL; 1164 1165 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 1166 if (!obj) { 1167 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); 1168 return -ENOENT; 1169 } 1170 bo = gem_to_ast_bo(obj); 1171 1172 ret = ast_bo_reserve(bo, false); 1173 if (ret) 1174 goto fail; 1175 1176 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map); 1177 1178 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem); 1179 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem); 1180 1181 if (src_isiomem == true) 1182 DRM_ERROR("src cursor bo should be in main memory\n"); 1183 if (dst_isiomem == false) 1184 DRM_ERROR("dst bo should be in VRAM\n"); 1185 1186 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1187 1188 /* do data transfer to cursor cache */ 1189 csum = copy_cursor_image(src, dst, width, height); 1190 1191 /* write checksum + signature */ 1192 ttm_bo_kunmap(&uobj_map); 1193 ast_bo_unreserve(bo); 1194 { 1195 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1196 writel(csum, dst); 1197 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1198 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1199 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1200 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1201 1202 /* set pattern offset */ 1203 gpu_addr = ast->cursor_cache_gpu_addr; 1204 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1205 gpu_addr >>= 3; 1206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff); 1207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff); 1208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff); 1209 } 1210 ast_crtc->cursor_width = width; 1211 ast_crtc->cursor_height = height; 1212 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width; 1213 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height; 1214 1215 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM; 1216 1217 ast_show_cursor(crtc); 1218 1219 drm_gem_object_unreference_unlocked(obj); 1220 return 0; 1221 fail: 1222 drm_gem_object_unreference_unlocked(obj); 1223 return ret; 1224 } 1225 1226 static int ast_cursor_move(struct drm_crtc *crtc, 1227 int x, int y) 1228 { 1229 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1230 struct ast_private *ast = crtc->dev->dev_private; 1231 int x_offset, y_offset; 1232 u8 *sig; 1233 1234 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1235 writel(x, sig + AST_HWC_SIGNATURE_X); 1236 writel(y, sig + AST_HWC_SIGNATURE_Y); 1237 1238 x_offset = ast_crtc->offset_x; 1239 y_offset = ast_crtc->offset_y; 1240 if (x < 0) { 1241 x_offset = (-x) + ast_crtc->offset_x; 1242 x = 0; 1243 } 1244 1245 if (y < 0) { 1246 y_offset = (-y) + ast_crtc->offset_y; 1247 y = 0; 1248 } 1249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1250 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1255 1256 /* dummy write to fire HWC */ 1257 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00); 1258 1259 return 0; 1260 } 1261