1 /* $NetBSD: amd_shared.h,v 1.2 2018/08/27 04:58:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __AMD_SHARED_H__ 26 #define __AMD_SHARED_H__ 27 28 #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 29 30 /* 31 * Supported GPU families (aligned with amdgpu_drm.h) 32 */ 33 #define AMD_FAMILY_UNKNOWN 0 34 #define AMD_FAMILY_CI 120 /* Bonaire, Hawaii */ 35 #define AMD_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 36 #define AMD_FAMILY_VI 130 /* Iceland, Tonga */ 37 #define AMD_FAMILY_CZ 135 /* Carrizo */ 38 39 /* 40 * Supported ASIC types 41 */ 42 enum amd_asic_type { 43 CHIP_BONAIRE = 0, 44 CHIP_KAVERI, 45 CHIP_KABINI, 46 CHIP_HAWAII, 47 CHIP_MULLINS, 48 CHIP_TOPAZ, 49 CHIP_TONGA, 50 CHIP_FIJI, 51 CHIP_CARRIZO, 52 CHIP_STONEY, 53 CHIP_LAST, 54 }; 55 56 /* 57 * Chip flags 58 */ 59 enum amd_chip_flags { 60 AMD_ASIC_MASK = 0x0000ffffUL, 61 AMD_FLAGS_MASK = 0xffff0000UL, 62 AMD_IS_MOBILITY = 0x00010000UL, 63 AMD_IS_APU = 0x00020000UL, 64 AMD_IS_PX = 0x00040000UL, 65 AMD_EXP_HW_SUPPORT = 0x00080000UL, 66 }; 67 68 enum amd_ip_block_type { 69 AMD_IP_BLOCK_TYPE_COMMON, 70 AMD_IP_BLOCK_TYPE_GMC, 71 AMD_IP_BLOCK_TYPE_IH, 72 AMD_IP_BLOCK_TYPE_SMC, 73 AMD_IP_BLOCK_TYPE_DCE, 74 AMD_IP_BLOCK_TYPE_GFX, 75 AMD_IP_BLOCK_TYPE_SDMA, 76 AMD_IP_BLOCK_TYPE_UVD, 77 AMD_IP_BLOCK_TYPE_VCE, 78 }; 79 80 enum amd_clockgating_state { 81 AMD_CG_STATE_GATE = 0, 82 AMD_CG_STATE_UNGATE, 83 }; 84 85 enum amd_powergating_state { 86 AMD_PG_STATE_GATE = 0, 87 AMD_PG_STATE_UNGATE, 88 }; 89 90 struct amd_ip_funcs { 91 /* sets up early driver state (pre sw_init), does not configure hw - Optional */ 92 int (*early_init)(void *handle); 93 /* sets up late driver/hw state (post hw_init) - Optional */ 94 int (*late_init)(void *handle); 95 /* sets up driver state, does not configure hw */ 96 int (*sw_init)(void *handle); 97 /* tears down driver state, does not configure hw */ 98 int (*sw_fini)(void *handle); 99 /* sets up the hw state */ 100 int (*hw_init)(void *handle); 101 /* tears down the hw state */ 102 int (*hw_fini)(void *handle); 103 /* handles IP specific hw/sw changes for suspend */ 104 int (*suspend)(void *handle); 105 /* handles IP specific hw/sw changes for resume */ 106 int (*resume)(void *handle); 107 /* returns current IP block idle status */ 108 bool (*is_idle)(void *handle); 109 /* poll for idle */ 110 int (*wait_for_idle)(void *handle); 111 /* soft reset the IP block */ 112 int (*soft_reset)(void *handle); 113 /* dump the IP block status registers */ 114 void (*print_status)(void *handle); 115 /* enable/disable cg for the IP block */ 116 int (*set_clockgating_state)(void *handle, 117 enum amd_clockgating_state state); 118 /* enable/disable pg for the IP block */ 119 int (*set_powergating_state)(void *handle, 120 enum amd_powergating_state state); 121 }; 122 123 #endif /* __AMD_SHARED_H__ */ 124