1 /* $NetBSD: amdgpu_ucode.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ucode.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <asm/byteorder.h> 33 #include <drm/drmP.h> 34 #include "amdgpu.h" 35 #include "amdgpu_ucode.h" 36 37 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 38 { 39 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 40 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 41 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 42 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 43 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 44 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 45 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 46 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 47 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 48 le32_to_cpu(hdr->ucode_array_offset_bytes)); 49 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 50 } 51 52 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 53 { 54 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 55 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 56 57 DRM_DEBUG("MC\n"); 58 amdgpu_ucode_print_common_hdr(hdr); 59 60 if (version_major == 1) { 61 const struct mc_firmware_header_v1_0 *mc_hdr = 62 const_container_of(hdr, struct mc_firmware_header_v1_0, header); 63 64 DRM_DEBUG("io_debug_size_bytes: %u\n", 65 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 66 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 67 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 68 } else { 69 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 70 } 71 } 72 73 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 74 { 75 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 76 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 77 78 DRM_DEBUG("SMC\n"); 79 amdgpu_ucode_print_common_hdr(hdr); 80 81 if (version_major == 1) { 82 const struct smc_firmware_header_v1_0 *smc_hdr = 83 const_container_of(hdr, struct smc_firmware_header_v1_0, header); 84 85 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); 86 } else { 87 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 88 } 89 } 90 91 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 92 { 93 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 94 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 95 96 DRM_DEBUG("GFX\n"); 97 amdgpu_ucode_print_common_hdr(hdr); 98 99 if (version_major == 1) { 100 const struct gfx_firmware_header_v1_0 *gfx_hdr = 101 const_container_of(hdr, struct gfx_firmware_header_v1_0, header); 102 103 DRM_DEBUG("ucode_feature_version: %u\n", 104 le32_to_cpu(gfx_hdr->ucode_feature_version)); 105 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 106 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 107 } else { 108 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 109 } 110 } 111 112 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 113 { 114 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 115 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 116 117 DRM_DEBUG("RLC\n"); 118 amdgpu_ucode_print_common_hdr(hdr); 119 120 if (version_major == 1) { 121 const struct rlc_firmware_header_v1_0 *rlc_hdr = 122 const_container_of(hdr, struct rlc_firmware_header_v1_0, header); 123 124 DRM_DEBUG("ucode_feature_version: %u\n", 125 le32_to_cpu(rlc_hdr->ucode_feature_version)); 126 DRM_DEBUG("save_and_restore_offset: %u\n", 127 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 128 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 129 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 130 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 131 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 132 DRM_DEBUG("master_pkt_description_offset: %u\n", 133 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 134 } else if (version_major == 2) { 135 const struct rlc_firmware_header_v2_0 *rlc_hdr = 136 const_container_of(hdr, struct rlc_firmware_header_v2_0, header); 137 138 DRM_DEBUG("ucode_feature_version: %u\n", 139 le32_to_cpu(rlc_hdr->ucode_feature_version)); 140 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 141 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 142 DRM_DEBUG("save_and_restore_offset: %u\n", 143 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 144 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 145 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 146 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 147 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 148 DRM_DEBUG("reg_restore_list_size: %u\n", 149 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 150 DRM_DEBUG("reg_list_format_start: %u\n", 151 le32_to_cpu(rlc_hdr->reg_list_format_start)); 152 DRM_DEBUG("reg_list_format_separate_start: %u\n", 153 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 154 DRM_DEBUG("starting_offsets_start: %u\n", 155 le32_to_cpu(rlc_hdr->starting_offsets_start)); 156 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 157 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 158 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 159 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 160 DRM_DEBUG("reg_list_size_bytes: %u\n", 161 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 162 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 163 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 164 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 165 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 166 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 167 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 168 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 169 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 170 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 171 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 172 } else { 173 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 174 } 175 } 176 177 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 178 { 179 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 180 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 181 182 DRM_DEBUG("SDMA\n"); 183 amdgpu_ucode_print_common_hdr(hdr); 184 185 if (version_major == 1) { 186 const struct sdma_firmware_header_v1_0 *sdma_hdr = 187 const_container_of(hdr, struct sdma_firmware_header_v1_0, header); 188 189 DRM_DEBUG("ucode_feature_version: %u\n", 190 le32_to_cpu(sdma_hdr->ucode_feature_version)); 191 DRM_DEBUG("ucode_change_version: %u\n", 192 le32_to_cpu(sdma_hdr->ucode_change_version)); 193 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 194 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 195 if (version_minor >= 1) { 196 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 197 const_container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 198 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 199 } 200 } else { 201 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 202 version_major, version_minor); 203 } 204 } 205 206 int amdgpu_ucode_validate(const struct firmware *fw) 207 { 208 const struct common_firmware_header *hdr = 209 (const struct common_firmware_header *)fw->data; 210 211 if (fw->size == le32_to_cpu(hdr->size_bytes)) 212 return 0; 213 214 return -EINVAL; 215 } 216 217 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 218 uint16_t hdr_major, uint16_t hdr_minor) 219 { 220 if ((hdr->common.header_version_major == hdr_major) && 221 (hdr->common.header_version_minor == hdr_minor)) 222 return false; 223 return true; 224 } 225 226 static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, 227 uint64_t mc_addr, void *kptr) 228 { 229 const struct common_firmware_header *header = NULL; 230 231 if (NULL == ucode->fw) 232 return 0; 233 234 ucode->mc_addr = mc_addr; 235 ucode->kaddr = kptr; 236 237 header = (const struct common_firmware_header *)ucode->fw->data; 238 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 239 le32_to_cpu(header->ucode_array_offset_bytes)), 240 le32_to_cpu(header->ucode_size_bytes)); 241 242 return 0; 243 } 244 245 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 246 { 247 struct amdgpu_bo **bo = &adev->firmware.fw_buf; 248 uint64_t fw_mc_addr; 249 void *fw_buf_ptr = NULL; 250 uint64_t fw_offset = 0; 251 int i, err; 252 struct amdgpu_firmware_info *ucode = NULL; 253 const struct common_firmware_header *header = NULL; 254 255 err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, 256 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, bo); 257 if (err) { 258 dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); 259 err = -ENOMEM; 260 goto failed; 261 } 262 263 err = amdgpu_bo_reserve(*bo, false); 264 if (err) { 265 amdgpu_bo_unref(bo); 266 dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); 267 goto failed; 268 } 269 270 err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr); 271 if (err) { 272 amdgpu_bo_unreserve(*bo); 273 amdgpu_bo_unref(bo); 274 dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); 275 goto failed; 276 } 277 278 err = amdgpu_bo_kmap(*bo, &fw_buf_ptr); 279 if (err) { 280 dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); 281 amdgpu_bo_unpin(*bo); 282 amdgpu_bo_unreserve(*bo); 283 amdgpu_bo_unref(bo); 284 goto failed; 285 } 286 287 amdgpu_bo_unreserve(*bo); 288 289 fw_offset = 0; 290 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { 291 ucode = &adev->firmware.ucode[i]; 292 if (ucode->fw) { 293 header = (const struct common_firmware_header *)ucode->fw->data; 294 amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset, 295 (char *)fw_buf_ptr + fw_offset); 296 #ifdef __NetBSD__ /* XXX ALIGN means something else */ 297 fw_offset += round_up(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 298 #else 299 fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 300 #endif 301 } 302 } 303 304 failed: 305 if (err) 306 adev->firmware.smu_load = false; 307 308 return err; 309 } 310 311 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev) 312 { 313 int i; 314 struct amdgpu_firmware_info *ucode = NULL; 315 316 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { 317 ucode = &adev->firmware.ucode[i]; 318 if (ucode->fw) { 319 ucode->mc_addr = 0; 320 ucode->kaddr = NULL; 321 } 322 } 323 amdgpu_bo_unref(&adev->firmware.fw_buf); 324 adev->firmware.fw_buf = NULL; 325 326 return 0; 327 } 328