1 /* $NetBSD: amdgpu_ucode.c,v 1.6 2020/02/14 14:34:58 maya Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ucode.c,v 1.6 2020/02/14 14:34:58 maya Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <drm/drmP.h> 33 #include "amdgpu.h" 34 #include "amdgpu_ucode.h" 35 36 #include <linux/nbsd-namespace.h> 37 38 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 39 { 40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 42 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 43 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 44 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 45 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 48 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 49 le32_to_cpu(hdr->ucode_array_offset_bytes)); 50 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 51 } 52 53 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 54 { 55 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 56 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 57 58 DRM_DEBUG("MC\n"); 59 amdgpu_ucode_print_common_hdr(hdr); 60 61 if (version_major == 1) { 62 const struct mc_firmware_header_v1_0 *mc_hdr = 63 const_container_of(hdr, struct mc_firmware_header_v1_0, header); 64 65 DRM_DEBUG("io_debug_size_bytes: %u\n", 66 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 67 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 68 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 69 } else { 70 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 71 } 72 } 73 74 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 75 { 76 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 77 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 78 79 DRM_DEBUG("SMC\n"); 80 amdgpu_ucode_print_common_hdr(hdr); 81 82 if (version_major == 1) { 83 const struct smc_firmware_header_v1_0 *smc_hdr = 84 const_container_of(hdr, struct smc_firmware_header_v1_0, header); 85 86 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); 87 } else { 88 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 89 } 90 } 91 92 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 93 { 94 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 95 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 96 97 DRM_DEBUG("GFX\n"); 98 amdgpu_ucode_print_common_hdr(hdr); 99 100 if (version_major == 1) { 101 const struct gfx_firmware_header_v1_0 *gfx_hdr = 102 const_container_of(hdr, struct gfx_firmware_header_v1_0, header); 103 104 DRM_DEBUG("ucode_feature_version: %u\n", 105 le32_to_cpu(gfx_hdr->ucode_feature_version)); 106 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 107 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 108 } else { 109 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 110 } 111 } 112 113 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 114 { 115 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 116 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 117 118 DRM_DEBUG("RLC\n"); 119 amdgpu_ucode_print_common_hdr(hdr); 120 121 if (version_major == 1) { 122 const struct rlc_firmware_header_v1_0 *rlc_hdr = 123 const_container_of(hdr, struct rlc_firmware_header_v1_0, header); 124 125 DRM_DEBUG("ucode_feature_version: %u\n", 126 le32_to_cpu(rlc_hdr->ucode_feature_version)); 127 DRM_DEBUG("save_and_restore_offset: %u\n", 128 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 129 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 130 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 131 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 132 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 133 DRM_DEBUG("master_pkt_description_offset: %u\n", 134 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 135 } else if (version_major == 2) { 136 const struct rlc_firmware_header_v2_0 *rlc_hdr = 137 const_container_of(hdr, struct rlc_firmware_header_v2_0, header); 138 139 DRM_DEBUG("ucode_feature_version: %u\n", 140 le32_to_cpu(rlc_hdr->ucode_feature_version)); 141 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 142 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 143 DRM_DEBUG("save_and_restore_offset: %u\n", 144 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 145 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 146 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 147 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 148 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 149 DRM_DEBUG("reg_restore_list_size: %u\n", 150 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 151 DRM_DEBUG("reg_list_format_start: %u\n", 152 le32_to_cpu(rlc_hdr->reg_list_format_start)); 153 DRM_DEBUG("reg_list_format_separate_start: %u\n", 154 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 155 DRM_DEBUG("starting_offsets_start: %u\n", 156 le32_to_cpu(rlc_hdr->starting_offsets_start)); 157 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 158 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 159 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 160 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 161 DRM_DEBUG("reg_list_size_bytes: %u\n", 162 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 163 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 164 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 165 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 166 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 167 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 168 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 169 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 170 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 171 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 172 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 173 } else { 174 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 175 } 176 } 177 178 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 179 { 180 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 181 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 182 183 DRM_DEBUG("SDMA\n"); 184 amdgpu_ucode_print_common_hdr(hdr); 185 186 if (version_major == 1) { 187 const struct sdma_firmware_header_v1_0 *sdma_hdr = 188 const_container_of(hdr, struct sdma_firmware_header_v1_0, header); 189 190 DRM_DEBUG("ucode_feature_version: %u\n", 191 le32_to_cpu(sdma_hdr->ucode_feature_version)); 192 DRM_DEBUG("ucode_change_version: %u\n", 193 le32_to_cpu(sdma_hdr->ucode_change_version)); 194 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 195 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 196 if (version_minor >= 1) { 197 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 198 const_container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 199 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 200 } 201 } else { 202 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 203 version_major, version_minor); 204 } 205 } 206 207 int amdgpu_ucode_validate(const struct firmware *fw) 208 { 209 const struct common_firmware_header *hdr = 210 (const struct common_firmware_header *)fw->data; 211 212 if (fw->size == le32_to_cpu(hdr->size_bytes)) 213 return 0; 214 215 return -EINVAL; 216 } 217 218 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 219 uint16_t hdr_major, uint16_t hdr_minor) 220 { 221 if ((hdr->common.header_version_major == hdr_major) && 222 (hdr->common.header_version_minor == hdr_minor)) 223 return false; 224 return true; 225 } 226 227 static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, 228 uint64_t mc_addr, void *kptr) 229 { 230 const struct common_firmware_header *header = NULL; 231 232 if (NULL == ucode->fw) 233 return 0; 234 235 ucode->mc_addr = mc_addr; 236 ucode->kaddr = kptr; 237 238 header = (const struct common_firmware_header *)ucode->fw->data; 239 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 240 le32_to_cpu(header->ucode_array_offset_bytes)), 241 le32_to_cpu(header->ucode_size_bytes)); 242 243 return 0; 244 } 245 246 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 247 { 248 struct amdgpu_bo **bo = &adev->firmware.fw_buf; 249 uint64_t fw_mc_addr; 250 void *fw_buf_ptr = NULL; 251 uint64_t fw_offset = 0; 252 int i, err; 253 struct amdgpu_firmware_info *ucode = NULL; 254 const struct common_firmware_header *header = NULL; 255 256 err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, 257 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, bo); 258 if (err) { 259 dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); 260 err = -ENOMEM; 261 goto failed; 262 } 263 264 err = amdgpu_bo_reserve(*bo, false); 265 if (err) { 266 amdgpu_bo_unref(bo); 267 dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); 268 goto failed; 269 } 270 271 err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr); 272 if (err) { 273 amdgpu_bo_unreserve(*bo); 274 amdgpu_bo_unref(bo); 275 dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); 276 goto failed; 277 } 278 279 err = amdgpu_bo_kmap(*bo, &fw_buf_ptr); 280 if (err) { 281 dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); 282 amdgpu_bo_unpin(*bo); 283 amdgpu_bo_unreserve(*bo); 284 amdgpu_bo_unref(bo); 285 goto failed; 286 } 287 288 amdgpu_bo_unreserve(*bo); 289 290 fw_offset = 0; 291 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { 292 ucode = &adev->firmware.ucode[i]; 293 if (ucode->fw) { 294 header = (const struct common_firmware_header *)ucode->fw->data; 295 amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset, 296 fw_buf_ptr + fw_offset); 297 fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 298 } 299 } 300 301 failed: 302 if (err) 303 adev->firmware.smu_load = false; 304 305 return err; 306 } 307 308 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev) 309 { 310 int i; 311 struct amdgpu_firmware_info *ucode = NULL; 312 313 for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { 314 ucode = &adev->firmware.ucode[i]; 315 if (ucode->fw) { 316 ucode->mc_addr = 0; 317 ucode->kaddr = NULL; 318 } 319 } 320 amdgpu_bo_unref(&adev->firmware.fw_buf); 321 adev->firmware.fw_buf = NULL; 322 323 return 0; 324 } 325