1 /* $NetBSD: amdgpu_ttm.c,v 1.4 2018/08/27 15:22:54 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 Jerome Glisse. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Jerome Glisse <glisse@freedesktop.org> 31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 32 * Dave Airlie 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ttm.c,v 1.4 2018/08/27 15:22:54 riastradh Exp $"); 36 37 #include <ttm/ttm_bo_api.h> 38 #include <ttm/ttm_bo_driver.h> 39 #include <ttm/ttm_placement.h> 40 #include <ttm/ttm_module.h> 41 #include <ttm/ttm_page_alloc.h> 42 #include <drm/drmP.h> 43 #include <drm/amdgpu_drm.h> 44 #include <linux/seq_file.h> 45 #include <linux/slab.h> 46 #include <linux/swiotlb.h> 47 #include <linux/swap.h> 48 #include <linux/pagemap.h> 49 #include <linux/debugfs.h> 50 #include "amdgpu.h" 51 #include "bif/bif_4_1_d.h" 52 53 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 54 55 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 56 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); 57 58 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev) 59 { 60 struct amdgpu_mman *mman; 61 struct amdgpu_device *adev; 62 63 mman = container_of(bdev, struct amdgpu_mman, bdev); 64 adev = container_of(mman, struct amdgpu_device, mman); 65 return adev; 66 } 67 68 69 /* 70 * Global memory. 71 */ 72 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) 73 { 74 return ttm_mem_global_init(ref->object); 75 } 76 77 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) 78 { 79 ttm_mem_global_release(ref->object); 80 } 81 82 static int amdgpu_ttm_global_init(struct amdgpu_device *adev) 83 { 84 struct drm_global_reference *global_ref; 85 int r; 86 87 adev->mman.mem_global_referenced = false; 88 global_ref = &adev->mman.mem_global_ref; 89 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 90 global_ref->size = sizeof(struct ttm_mem_global); 91 global_ref->init = &amdgpu_ttm_mem_global_init; 92 global_ref->release = &amdgpu_ttm_mem_global_release; 93 r = drm_global_item_ref(global_ref); 94 if (r != 0) { 95 DRM_ERROR("Failed setting up TTM memory accounting " 96 "subsystem.\n"); 97 return r; 98 } 99 100 adev->mman.bo_global_ref.mem_glob = 101 adev->mman.mem_global_ref.object; 102 global_ref = &adev->mman.bo_global_ref.ref; 103 global_ref->global_type = DRM_GLOBAL_TTM_BO; 104 global_ref->size = sizeof(struct ttm_bo_global); 105 global_ref->init = &ttm_bo_global_init; 106 global_ref->release = &ttm_bo_global_release; 107 r = drm_global_item_ref(global_ref); 108 if (r != 0) { 109 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 110 drm_global_item_unref(&adev->mman.mem_global_ref); 111 return r; 112 } 113 114 adev->mman.mem_global_referenced = true; 115 return 0; 116 } 117 118 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) 119 { 120 if (adev->mman.mem_global_referenced) { 121 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 122 drm_global_item_unref(&adev->mman.mem_global_ref); 123 adev->mman.mem_global_referenced = false; 124 } 125 } 126 127 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 128 { 129 return 0; 130 } 131 132 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 133 struct ttm_mem_type_manager *man) 134 { 135 struct amdgpu_device *adev; 136 137 adev = amdgpu_get_adev(bdev); 138 139 switch (type) { 140 case TTM_PL_SYSTEM: 141 /* System memory */ 142 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 143 man->available_caching = TTM_PL_MASK_CACHING; 144 man->default_caching = TTM_PL_FLAG_CACHED; 145 break; 146 case TTM_PL_TT: 147 man->func = &ttm_bo_manager_func; 148 man->gpu_offset = adev->mc.gtt_start; 149 man->available_caching = TTM_PL_MASK_CACHING; 150 man->default_caching = TTM_PL_FLAG_CACHED; 151 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 152 break; 153 case TTM_PL_VRAM: 154 /* "On-card" video ram */ 155 man->func = &ttm_bo_manager_func; 156 man->gpu_offset = adev->mc.vram_start; 157 man->flags = TTM_MEMTYPE_FLAG_FIXED | 158 TTM_MEMTYPE_FLAG_MAPPABLE; 159 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 160 man->default_caching = TTM_PL_FLAG_WC; 161 break; 162 case AMDGPU_PL_GDS: 163 case AMDGPU_PL_GWS: 164 case AMDGPU_PL_OA: 165 /* On-chip GDS memory*/ 166 man->func = &ttm_bo_manager_func; 167 man->gpu_offset = 0; 168 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; 169 man->available_caching = TTM_PL_FLAG_UNCACHED; 170 man->default_caching = TTM_PL_FLAG_UNCACHED; 171 break; 172 default: 173 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 174 return -EINVAL; 175 } 176 return 0; 177 } 178 179 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 180 struct ttm_placement *placement) 181 { 182 struct amdgpu_bo *rbo; 183 static struct ttm_place placements = { 184 .fpfn = 0, 185 .lpfn = 0, 186 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 187 }; 188 189 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { 190 placement->placement = &placements; 191 placement->busy_placement = &placements; 192 placement->num_placement = 1; 193 placement->num_busy_placement = 1; 194 return; 195 } 196 rbo = container_of(bo, struct amdgpu_bo, tbo); 197 switch (bo->mem.mem_type) { 198 case TTM_PL_VRAM: 199 if (rbo->adev->mman.buffer_funcs_ring->ready == false) 200 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); 201 else 202 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT); 203 break; 204 case TTM_PL_TT: 205 default: 206 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); 207 } 208 *placement = rbo->placement; 209 } 210 211 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 212 { 213 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); 214 215 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 216 } 217 218 static void amdgpu_move_null(struct ttm_buffer_object *bo, 219 struct ttm_mem_reg *new_mem) 220 { 221 struct ttm_mem_reg *old_mem = &bo->mem; 222 223 BUG_ON(old_mem->mm_node != NULL); 224 *old_mem = *new_mem; 225 new_mem->mm_node = NULL; 226 } 227 228 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 229 bool evict, bool no_wait_gpu, 230 struct ttm_mem_reg *new_mem, 231 struct ttm_mem_reg *old_mem) 232 { 233 struct amdgpu_device *adev; 234 struct amdgpu_ring *ring; 235 uint64_t old_start, new_start; 236 struct fence *fence; 237 int r; 238 239 adev = amdgpu_get_adev(bo->bdev); 240 ring = adev->mman.buffer_funcs_ring; 241 old_start = (u64)old_mem->start << PAGE_SHIFT; 242 new_start = (u64)new_mem->start << PAGE_SHIFT; 243 244 switch (old_mem->mem_type) { 245 case TTM_PL_VRAM: 246 old_start += adev->mc.vram_start; 247 break; 248 case TTM_PL_TT: 249 old_start += adev->mc.gtt_start; 250 break; 251 default: 252 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 253 return -EINVAL; 254 } 255 switch (new_mem->mem_type) { 256 case TTM_PL_VRAM: 257 new_start += adev->mc.vram_start; 258 break; 259 case TTM_PL_TT: 260 new_start += adev->mc.gtt_start; 261 break; 262 default: 263 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 264 return -EINVAL; 265 } 266 if (!ring->ready) { 267 DRM_ERROR("Trying to move memory with ring turned off.\n"); 268 return -EINVAL; 269 } 270 271 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); 272 273 r = amdgpu_copy_buffer(ring, old_start, new_start, 274 new_mem->num_pages * PAGE_SIZE, /* bytes */ 275 bo->resv, &fence); 276 /* FIXME: handle copy error */ 277 r = ttm_bo_move_accel_cleanup(bo, fence, 278 evict, no_wait_gpu, new_mem); 279 fence_put(fence); 280 return r; 281 } 282 283 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, 284 bool evict, bool interruptible, 285 bool no_wait_gpu, 286 struct ttm_mem_reg *new_mem) 287 { 288 struct amdgpu_device *adev __unused; 289 struct ttm_mem_reg *old_mem = &bo->mem; 290 struct ttm_mem_reg tmp_mem; 291 struct ttm_place placements; 292 struct ttm_placement placement; 293 int r; 294 295 adev = amdgpu_get_adev(bo->bdev); 296 tmp_mem = *new_mem; 297 tmp_mem.mm_node = NULL; 298 placement.num_placement = 1; 299 placement.placement = &placements; 300 placement.num_busy_placement = 1; 301 placement.busy_placement = &placements; 302 placements.fpfn = 0; 303 placements.lpfn = 0; 304 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 305 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 306 interruptible, no_wait_gpu); 307 if (unlikely(r)) { 308 return r; 309 } 310 311 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 312 if (unlikely(r)) { 313 goto out_cleanup; 314 } 315 316 r = ttm_tt_bind(bo->ttm, &tmp_mem); 317 if (unlikely(r)) { 318 goto out_cleanup; 319 } 320 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 321 if (unlikely(r)) { 322 goto out_cleanup; 323 } 324 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 325 out_cleanup: 326 ttm_bo_mem_put(bo, &tmp_mem); 327 return r; 328 } 329 330 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, 331 bool evict, bool interruptible, 332 bool no_wait_gpu, 333 struct ttm_mem_reg *new_mem) 334 { 335 struct amdgpu_device *adev __unused; 336 struct ttm_mem_reg *old_mem = &bo->mem; 337 struct ttm_mem_reg tmp_mem; 338 struct ttm_placement placement; 339 struct ttm_place placements; 340 int r; 341 342 adev = amdgpu_get_adev(bo->bdev); 343 tmp_mem = *new_mem; 344 tmp_mem.mm_node = NULL; 345 placement.num_placement = 1; 346 placement.placement = &placements; 347 placement.num_busy_placement = 1; 348 placement.busy_placement = &placements; 349 placements.fpfn = 0; 350 placements.lpfn = 0; 351 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 352 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 353 interruptible, no_wait_gpu); 354 if (unlikely(r)) { 355 return r; 356 } 357 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 358 if (unlikely(r)) { 359 goto out_cleanup; 360 } 361 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 362 if (unlikely(r)) { 363 goto out_cleanup; 364 } 365 out_cleanup: 366 ttm_bo_mem_put(bo, &tmp_mem); 367 return r; 368 } 369 370 static int amdgpu_bo_move(struct ttm_buffer_object *bo, 371 bool evict, bool interruptible, 372 bool no_wait_gpu, 373 struct ttm_mem_reg *new_mem) 374 { 375 struct amdgpu_device *adev; 376 struct ttm_mem_reg *old_mem = &bo->mem; 377 int r; 378 379 adev = amdgpu_get_adev(bo->bdev); 380 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 381 amdgpu_move_null(bo, new_mem); 382 return 0; 383 } 384 if ((old_mem->mem_type == TTM_PL_TT && 385 new_mem->mem_type == TTM_PL_SYSTEM) || 386 (old_mem->mem_type == TTM_PL_SYSTEM && 387 new_mem->mem_type == TTM_PL_TT)) { 388 /* bind is enough */ 389 amdgpu_move_null(bo, new_mem); 390 return 0; 391 } 392 if (adev->mman.buffer_funcs == NULL || 393 adev->mman.buffer_funcs_ring == NULL || 394 !adev->mman.buffer_funcs_ring->ready) { 395 /* use memcpy */ 396 goto memcpy; 397 } 398 399 if (old_mem->mem_type == TTM_PL_VRAM && 400 new_mem->mem_type == TTM_PL_SYSTEM) { 401 r = amdgpu_move_vram_ram(bo, evict, interruptible, 402 no_wait_gpu, new_mem); 403 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 404 new_mem->mem_type == TTM_PL_VRAM) { 405 r = amdgpu_move_ram_vram(bo, evict, interruptible, 406 no_wait_gpu, new_mem); 407 } else { 408 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 409 } 410 411 if (r) { 412 memcpy: 413 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 414 if (r) { 415 return r; 416 } 417 } 418 419 /* update statistics */ 420 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 421 return 0; 422 } 423 424 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 425 { 426 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 427 struct amdgpu_device *adev = amdgpu_get_adev(bdev); 428 429 mem->bus.addr = NULL; 430 mem->bus.offset = 0; 431 mem->bus.size = mem->num_pages << PAGE_SHIFT; 432 mem->bus.base = 0; 433 mem->bus.is_iomem = false; 434 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 435 return -EINVAL; 436 switch (mem->mem_type) { 437 case TTM_PL_SYSTEM: 438 /* system memory */ 439 return 0; 440 case TTM_PL_TT: 441 break; 442 case TTM_PL_VRAM: 443 mem->bus.offset = mem->start << PAGE_SHIFT; 444 /* check if it's visible */ 445 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) 446 return -EINVAL; 447 mem->bus.base = adev->mc.aper_base; 448 mem->bus.is_iomem = true; 449 #ifdef __alpha__ 450 /* 451 * Alpha: use bus.addr to hold the ioremap() return, 452 * so we can modify bus.base below. 453 */ 454 if (mem->placement & TTM_PL_FLAG_WC) 455 mem->bus.addr = 456 ioremap_wc(mem->bus.base + mem->bus.offset, 457 mem->bus.size); 458 else 459 mem->bus.addr = 460 ioremap_nocache(mem->bus.base + mem->bus.offset, 461 mem->bus.size); 462 463 /* 464 * Alpha: Use just the bus offset plus 465 * the hose/domain memory base for bus.base. 466 * It then can be used to build PTEs for VRAM 467 * access, as done in ttm_bo_vm_fault(). 468 */ 469 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 470 adev->ddev->hose->dense_mem_base; 471 #endif 472 break; 473 default: 474 return -EINVAL; 475 } 476 return 0; 477 } 478 479 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 480 { 481 } 482 483 /* 484 * TTM backend functions. 485 */ 486 struct amdgpu_ttm_tt { 487 struct ttm_dma_tt ttm; 488 struct amdgpu_device *adev; 489 u64 offset; 490 uint64_t userptr; 491 struct mm_struct *usermm; 492 uint32_t userflags; 493 }; 494 495 /* prepare the sg table with the user pages */ 496 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 497 { 498 #ifdef __NetBSD__ 499 panic("we don't handle user pointers round these parts"); 500 #else 501 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); 502 struct amdgpu_ttm_tt *gtt = (void *)ttm; 503 unsigned pinned = 0, nents; 504 int r; 505 506 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 507 enum dma_data_direction direction = write ? 508 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 509 510 if (current->mm != gtt->usermm) 511 return -EPERM; 512 513 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { 514 /* check that we only pin down anonymous memory 515 to prevent problems with writeback */ 516 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 517 struct vm_area_struct *vma; 518 519 vma = find_vma(gtt->usermm, gtt->userptr); 520 if (!vma || vma->vm_file || vma->vm_end < end) 521 return -EPERM; 522 } 523 524 do { 525 unsigned num_pages = ttm->num_pages - pinned; 526 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 527 struct page **pages = ttm->pages + pinned; 528 529 r = get_user_pages(current, current->mm, userptr, num_pages, 530 write, 0, pages, NULL); 531 if (r < 0) 532 goto release_pages; 533 534 pinned += r; 535 536 } while (pinned < ttm->num_pages); 537 538 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 539 ttm->num_pages << PAGE_SHIFT, 540 GFP_KERNEL); 541 if (r) 542 goto release_sg; 543 544 r = -ENOMEM; 545 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 546 if (nents != ttm->sg->nents) 547 goto release_sg; 548 549 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 550 gtt->ttm.dma_address, ttm->num_pages); 551 552 return 0; 553 554 release_sg: 555 kfree(ttm->sg); 556 557 release_pages: 558 release_pages(ttm->pages, pinned, 0); 559 return r; 560 #endif 561 } 562 563 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 564 { 565 #ifdef __NetBSD__ 566 panic("some varmint pinned a userptr to my hat"); 567 #else 568 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); 569 struct amdgpu_ttm_tt *gtt = (void *)ttm; 570 struct sg_page_iter sg_iter; 571 572 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 573 enum dma_data_direction direction = write ? 574 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 575 576 /* double check that we don't free the table twice */ 577 if (!ttm->sg->sgl) 578 return; 579 580 /* free the sg table and pages again */ 581 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 582 583 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { 584 struct page *page = sg_page_iter_page(&sg_iter); 585 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 586 set_page_dirty(page); 587 588 mark_page_accessed(page); 589 page_cache_release(page); 590 } 591 592 sg_free_table(ttm->sg); 593 #endif 594 } 595 596 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 597 struct ttm_mem_reg *bo_mem) 598 { 599 struct amdgpu_ttm_tt *gtt = (void*)ttm; 600 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 601 int r; 602 603 if (gtt->userptr) { 604 r = amdgpu_ttm_tt_pin_userptr(ttm); 605 if (r) { 606 DRM_ERROR("failed to pin userptr\n"); 607 return r; 608 } 609 } 610 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 611 if (!ttm->num_pages) { 612 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 613 ttm->num_pages, bo_mem, ttm); 614 } 615 616 if (bo_mem->mem_type == AMDGPU_PL_GDS || 617 bo_mem->mem_type == AMDGPU_PL_GWS || 618 bo_mem->mem_type == AMDGPU_PL_OA) 619 return -EINVAL; 620 621 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, 622 ttm->pages, gtt->ttm.dma_address, flags); 623 624 if (r) { 625 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 626 ttm->num_pages, (unsigned)gtt->offset); 627 return r; 628 } 629 return 0; 630 } 631 632 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 633 { 634 struct amdgpu_ttm_tt *gtt = (void *)ttm; 635 636 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 637 if (gtt->adev->gart.ready) 638 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); 639 640 if (gtt->userptr) 641 amdgpu_ttm_tt_unpin_userptr(ttm); 642 643 return 0; 644 } 645 646 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 647 { 648 struct amdgpu_ttm_tt *gtt = (void *)ttm; 649 650 ttm_dma_tt_fini(>t->ttm); 651 kfree(gtt); 652 } 653 654 static struct ttm_backend_func amdgpu_backend_func = { 655 .bind = &amdgpu_ttm_backend_bind, 656 .unbind = &amdgpu_ttm_backend_unbind, 657 .destroy = &amdgpu_ttm_backend_destroy, 658 }; 659 660 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, 661 unsigned long size, uint32_t page_flags, 662 struct page *dummy_read_page) 663 { 664 struct amdgpu_device *adev; 665 struct amdgpu_ttm_tt *gtt; 666 667 adev = amdgpu_get_adev(bdev); 668 669 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 670 if (gtt == NULL) { 671 return NULL; 672 } 673 gtt->ttm.ttm.func = &amdgpu_backend_func; 674 gtt->adev = adev; 675 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 676 kfree(gtt); 677 return NULL; 678 } 679 return >t->ttm.ttm; 680 } 681 682 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) 683 { 684 #ifndef __NetBSD__ 685 struct amdgpu_device *adev; 686 #endif 687 struct amdgpu_ttm_tt *gtt = (void *)ttm; 688 #ifndef __NetBSD__ 689 unsigned i; 690 #endif 691 int r; 692 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 693 694 if (ttm->state != tt_unpopulated) 695 return 0; 696 697 if (gtt && gtt->userptr) { 698 #ifdef __NetBSD__ 699 panic("don't point at users, it's not polite"); 700 #else 701 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 702 if (!ttm->sg) 703 return -ENOMEM; 704 705 ttm->page_flags |= TTM_PAGE_FLAG_SG; 706 ttm->state = tt_unbound; 707 return 0; 708 #endif 709 } 710 711 if (slave && ttm->sg) { 712 #ifdef __NetBSD__ 713 r = drm_prime_bus_dmamap_load_sgt(ttm->bdev->dmat, 714 gtt->ttm.dma_address, ttm->sg); 715 if (r) 716 return r; 717 #else 718 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 719 gtt->ttm.dma_address, ttm->num_pages); 720 #endif 721 ttm->state = tt_unbound; 722 return 0; 723 } 724 725 #ifdef __NetBSD__ 726 /* XXX errno NetBSD->Linux */ 727 return ttm_bus_dma_populate(>t->ttm); 728 #else 729 730 adev = amdgpu_get_adev(ttm->bdev); 731 732 #ifdef CONFIG_SWIOTLB 733 if (swiotlb_nr_tbl()) { 734 return ttm_dma_populate(>t->ttm, adev->dev); 735 } 736 #endif 737 738 r = ttm_pool_populate(ttm); 739 if (r) { 740 return r; 741 } 742 743 for (i = 0; i < ttm->num_pages; i++) { 744 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], 745 0, PAGE_SIZE, 746 PCI_DMA_BIDIRECTIONAL); 747 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { 748 while (i--) { 749 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 750 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 751 gtt->ttm.dma_address[i] = 0; 752 } 753 ttm_pool_unpopulate(ttm); 754 return -EFAULT; 755 } 756 } 757 return 0; 758 #endif /* __NetBSD__ */ 759 } 760 761 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 762 { 763 #ifndef __NetBSD__ 764 struct amdgpu_device *adev; 765 #endif 766 struct amdgpu_ttm_tt *gtt = (void *)ttm; 767 #ifndef __NetBSD__ 768 unsigned i; 769 #endif 770 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 771 772 if (gtt && gtt->userptr) { 773 kfree(ttm->sg); 774 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 775 return; 776 } 777 778 if (slave) 779 return; 780 781 #ifdef __NetBSD__ 782 ttm_bus_dma_unpopulate(>t->ttm); 783 return; 784 #else 785 786 adev = amdgpu_get_adev(ttm->bdev); 787 788 #ifdef CONFIG_SWIOTLB 789 if (swiotlb_nr_tbl()) { 790 ttm_dma_unpopulate(>t->ttm, adev->dev); 791 return; 792 } 793 #endif 794 795 for (i = 0; i < ttm->num_pages; i++) { 796 if (gtt->ttm.dma_address[i]) { 797 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 798 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 799 } 800 } 801 802 ttm_pool_unpopulate(ttm); 803 #endif /* __NetBSD__ */ 804 } 805 806 #ifdef __NetBSD__ 807 static void amdgpu_ttm_tt_swapout(struct ttm_tt *ttm) 808 { 809 struct amdgpu_ttm_tt *gtt = container_of(ttm, struct amdgpu_ttm_tt, 810 ttm.ttm); 811 struct ttm_dma_tt *ttm_dma = >t->ttm; 812 813 ttm_bus_dma_swapout(ttm_dma); 814 } 815 816 static const struct uvm_pagerops amdgpu_uvm_ops = { 817 .pgo_reference = &ttm_bo_uvm_reference, 818 .pgo_detach = &ttm_bo_uvm_detach, 819 .pgo_fault = &ttm_bo_uvm_fault, 820 }; 821 #endif 822 823 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 824 uint32_t flags) 825 { 826 #ifdef __NetBSD__ 827 return -ENODEV; 828 #else 829 struct amdgpu_ttm_tt *gtt = (void *)ttm; 830 831 if (gtt == NULL) 832 return -EINVAL; 833 834 gtt->userptr = addr; 835 gtt->usermm = current->mm; 836 gtt->userflags = flags; 837 return 0; 838 #endif 839 } 840 841 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm) 842 { 843 struct amdgpu_ttm_tt *gtt = (void *)ttm; 844 845 if (gtt == NULL) 846 return false; 847 848 return !!gtt->userptr; 849 } 850 851 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 852 unsigned long end) 853 { 854 struct amdgpu_ttm_tt *gtt = (void *)ttm; 855 unsigned long size; 856 857 if (gtt == NULL) 858 return false; 859 860 if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr) 861 return false; 862 863 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 864 if (gtt->userptr > end || gtt->userptr + size <= start) 865 return false; 866 867 return true; 868 } 869 870 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 871 { 872 struct amdgpu_ttm_tt *gtt = (void *)ttm; 873 874 if (gtt == NULL) 875 return false; 876 877 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 878 } 879 880 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 881 struct ttm_mem_reg *mem) 882 { 883 uint32_t flags = 0; 884 885 if (mem && mem->mem_type != TTM_PL_SYSTEM) 886 flags |= AMDGPU_PTE_VALID; 887 888 if (mem && mem->mem_type == TTM_PL_TT) { 889 flags |= AMDGPU_PTE_SYSTEM; 890 891 if (ttm->caching_state == tt_cached) 892 flags |= AMDGPU_PTE_SNOOPED; 893 } 894 895 if (adev->asic_type >= CHIP_TONGA) 896 flags |= AMDGPU_PTE_EXECUTABLE; 897 898 flags |= AMDGPU_PTE_READABLE; 899 900 if (!amdgpu_ttm_tt_is_readonly(ttm)) 901 flags |= AMDGPU_PTE_WRITEABLE; 902 903 return flags; 904 } 905 906 static struct ttm_bo_driver amdgpu_bo_driver = { 907 .ttm_tt_create = &amdgpu_ttm_tt_create, 908 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 909 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 910 #ifdef __NetBSD__ 911 .ttm_tt_swapout = &amdgpu_ttm_tt_swapout, 912 .ttm_uvm_ops = &amdgpu_uvm_ops, 913 #endif 914 .invalidate_caches = &amdgpu_invalidate_caches, 915 .init_mem_type = &amdgpu_init_mem_type, 916 .evict_flags = &amdgpu_evict_flags, 917 .move = &amdgpu_bo_move, 918 .verify_access = &amdgpu_verify_access, 919 .move_notify = &amdgpu_bo_move_notify, 920 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 921 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 922 .io_mem_free = &amdgpu_ttm_io_mem_free, 923 }; 924 925 int amdgpu_ttm_init(struct amdgpu_device *adev) 926 { 927 int r; 928 929 r = amdgpu_ttm_global_init(adev); 930 if (r) { 931 return r; 932 } 933 /* No others user of address space so set it to 0 */ 934 r = ttm_bo_device_init(&adev->mman.bdev, 935 adev->mman.bo_global_ref.ref.object, 936 &amdgpu_bo_driver, 937 #ifdef __NetBSD__ 938 adev->ddev->bst, 939 adev->ddev->dmat, 940 #else 941 adev->ddev->anon_inode->i_mapping, 942 #endif 943 DRM_FILE_PAGE_OFFSET, 944 adev->need_dma32); 945 if (r) { 946 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 947 return r; 948 } 949 adev->mman.initialized = true; 950 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 951 adev->mc.real_vram_size >> PAGE_SHIFT); 952 if (r) { 953 DRM_ERROR("Failed initializing VRAM heap.\n"); 954 return r; 955 } 956 /* Change the size here instead of the init above so only lpfn is affected */ 957 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 958 959 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, 960 AMDGPU_GEM_DOMAIN_VRAM, 961 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 962 NULL, NULL, &adev->stollen_vga_memory); 963 if (r) { 964 return r; 965 } 966 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 967 if (r) 968 return r; 969 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); 970 amdgpu_bo_unreserve(adev->stollen_vga_memory); 971 if (r) { 972 amdgpu_bo_unref(&adev->stollen_vga_memory); 973 return r; 974 } 975 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 976 (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); 977 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, 978 adev->mc.gtt_size >> PAGE_SHIFT); 979 if (r) { 980 DRM_ERROR("Failed initializing GTT heap.\n"); 981 return r; 982 } 983 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 984 (unsigned)(adev->mc.gtt_size / (1024 * 1024))); 985 986 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; 987 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; 988 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; 989 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; 990 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; 991 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; 992 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; 993 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; 994 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; 995 /* GDS Memory */ 996 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 997 adev->gds.mem.total_size >> PAGE_SHIFT); 998 if (r) { 999 DRM_ERROR("Failed initializing GDS heap.\n"); 1000 return r; 1001 } 1002 1003 /* GWS */ 1004 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 1005 adev->gds.gws.total_size >> PAGE_SHIFT); 1006 if (r) { 1007 DRM_ERROR("Failed initializing gws heap.\n"); 1008 return r; 1009 } 1010 1011 /* OA */ 1012 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 1013 adev->gds.oa.total_size >> PAGE_SHIFT); 1014 if (r) { 1015 DRM_ERROR("Failed initializing oa heap.\n"); 1016 return r; 1017 } 1018 1019 r = amdgpu_ttm_debugfs_init(adev); 1020 if (r) { 1021 DRM_ERROR("Failed to init debugfs\n"); 1022 return r; 1023 } 1024 return 0; 1025 } 1026 1027 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1028 { 1029 int r; 1030 1031 if (!adev->mman.initialized) 1032 return; 1033 amdgpu_ttm_debugfs_fini(adev); 1034 if (adev->stollen_vga_memory) { 1035 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1036 if (r == 0) { 1037 amdgpu_bo_unpin(adev->stollen_vga_memory); 1038 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1039 } 1040 amdgpu_bo_unref(&adev->stollen_vga_memory); 1041 } 1042 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 1043 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 1044 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 1045 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 1046 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 1047 ttm_bo_device_release(&adev->mman.bdev); 1048 amdgpu_gart_fini(adev); 1049 amdgpu_ttm_global_fini(adev); 1050 adev->mman.initialized = false; 1051 DRM_INFO("amdgpu: ttm finalized\n"); 1052 } 1053 1054 /* this should only be called at bootup or when userspace 1055 * isn't running */ 1056 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) 1057 { 1058 struct ttm_mem_type_manager *man; 1059 1060 if (!adev->mman.initialized) 1061 return; 1062 1063 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 1064 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1065 man->size = size >> PAGE_SHIFT; 1066 } 1067 1068 #ifdef __NetBSD__ 1069 1070 int 1071 amdgpu_mmap_object(struct drm_device *dev, off_t offset, size_t size, 1072 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp, 1073 struct file *file) 1074 { 1075 struct amdgpu_device *adev = dev->dev_private; 1076 1077 KASSERT(0 == (offset & (PAGE_SIZE - 1))); 1078 1079 if (__predict_false(adev == NULL)) /* XXX How?? */ 1080 return -EINVAL; 1081 1082 if (__predict_false((offset >> PAGE_SHIFT) < DRM_FILE_PAGE_OFFSET)) 1083 return -EINVAL; 1084 1085 return ttm_bo_mmap_object(&adev->mman.bdev, offset, size, prot, 1086 uobjp, uoffsetp, file); 1087 } 1088 1089 #else /* __NetBSD__ */ 1090 1091 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1092 { 1093 struct drm_file *file_priv; 1094 struct amdgpu_device *adev; 1095 1096 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 1097 return -EINVAL; 1098 1099 file_priv = filp->private_data; 1100 adev = file_priv->minor->dev->dev_private; 1101 if (adev == NULL) 1102 return -EINVAL; 1103 1104 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1105 } 1106 1107 #endif /* __NetBSD__ */ 1108 1109 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 1110 uint64_t src_offset, 1111 uint64_t dst_offset, 1112 uint32_t byte_count, 1113 struct reservation_object *resv, 1114 struct fence **fence) 1115 { 1116 struct amdgpu_device *adev = ring->adev; 1117 uint32_t max_bytes; 1118 unsigned num_loops, num_dw; 1119 struct amdgpu_ib *ib; 1120 unsigned i; 1121 int r; 1122 1123 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1124 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1125 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; 1126 1127 /* for IB padding */ 1128 while (num_dw & 0x7) 1129 num_dw++; 1130 1131 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); 1132 if (!ib) 1133 return -ENOMEM; 1134 1135 r = amdgpu_ib_get(ring, NULL, num_dw * 4, ib); 1136 if (r) { 1137 kfree(ib); 1138 return r; 1139 } 1140 1141 ib->length_dw = 0; 1142 1143 if (resv) { 1144 r = amdgpu_sync_resv(adev, &ib->sync, resv, 1145 AMDGPU_FENCE_OWNER_UNDEFINED); 1146 if (r) { 1147 DRM_ERROR("sync failed (%d).\n", r); 1148 goto error_free; 1149 } 1150 } 1151 1152 for (i = 0; i < num_loops; i++) { 1153 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1154 1155 amdgpu_emit_copy_buffer(adev, ib, src_offset, dst_offset, 1156 cur_size_in_bytes); 1157 1158 src_offset += cur_size_in_bytes; 1159 dst_offset += cur_size_in_bytes; 1160 byte_count -= cur_size_in_bytes; 1161 } 1162 1163 amdgpu_vm_pad_ib(adev, ib); 1164 WARN_ON(ib->length_dw > num_dw); 1165 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, 1166 &amdgpu_vm_free_job, 1167 AMDGPU_FENCE_OWNER_UNDEFINED, 1168 fence); 1169 if (r) 1170 goto error_free; 1171 1172 if (!amdgpu_enable_scheduler) { 1173 amdgpu_ib_free(adev, ib); 1174 kfree(ib); 1175 } 1176 return 0; 1177 error_free: 1178 amdgpu_ib_free(adev, ib); 1179 kfree(ib); 1180 return r; 1181 } 1182 1183 #if defined(CONFIG_DEBUG_FS) 1184 1185 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 1186 { 1187 struct drm_info_node *node = (struct drm_info_node *)m->private; 1188 unsigned ttm_pl = *(int *)node->info_ent->data; 1189 struct drm_device *dev = node->minor->dev; 1190 struct amdgpu_device *adev = dev->dev_private; 1191 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; 1192 int ret; 1193 struct ttm_bo_global *glob = adev->mman.bdev.glob; 1194 1195 spin_lock(&glob->lru_lock); 1196 ret = drm_mm_dump_table(m, mm); 1197 spin_unlock(&glob->lru_lock); 1198 if (ttm_pl == TTM_PL_VRAM) 1199 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", 1200 adev->mman.bdev.man[ttm_pl].size, 1201 (u64)atomic64_read(&adev->vram_usage) >> 20, 1202 (u64)atomic64_read(&adev->vram_vis_usage) >> 20); 1203 return ret; 1204 } 1205 1206 static int ttm_pl_vram = TTM_PL_VRAM; 1207 static int ttm_pl_tt = TTM_PL_TT; 1208 1209 static struct drm_info_list amdgpu_ttm_debugfs_list[] = { 1210 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, 1211 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, 1212 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 1213 #ifdef CONFIG_SWIOTLB 1214 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 1215 #endif 1216 }; 1217 1218 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 1219 size_t size, loff_t *pos) 1220 { 1221 struct amdgpu_device *adev = f->f_inode->i_private; 1222 ssize_t result = 0; 1223 int r; 1224 1225 if (size & 0x3 || *pos & 0x3) 1226 return -EINVAL; 1227 1228 if (*pos >= adev->mc.mc_vram_size) 1229 return -ENXIO; 1230 1231 while (size) { 1232 unsigned long flags; 1233 uint32_t value; 1234 1235 if (*pos >= adev->mc.mc_vram_size) 1236 return result; 1237 1238 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1239 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 1240 WREG32(mmMM_INDEX_HI, *pos >> 31); 1241 value = RREG32(mmMM_DATA); 1242 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1243 1244 r = put_user(value, (uint32_t *)buf); 1245 if (r) 1246 return r; 1247 1248 result += 4; 1249 buf += 4; 1250 *pos += 4; 1251 size -= 4; 1252 } 1253 1254 return result; 1255 } 1256 1257 static const struct file_operations amdgpu_ttm_vram_fops = { 1258 .owner = THIS_MODULE, 1259 .read = amdgpu_ttm_vram_read, 1260 .llseek = default_llseek 1261 }; 1262 1263 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 1264 size_t size, loff_t *pos) 1265 { 1266 struct amdgpu_device *adev = f->f_inode->i_private; 1267 ssize_t result = 0; 1268 int r; 1269 1270 while (size) { 1271 loff_t p = *pos / PAGE_SIZE; 1272 unsigned off = *pos & ~PAGE_MASK; 1273 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1274 struct page *page; 1275 void *ptr; 1276 1277 if (p >= adev->gart.num_cpu_pages) 1278 return result; 1279 1280 page = adev->gart.pages[p]; 1281 if (page) { 1282 ptr = kmap(page); 1283 ptr += off; 1284 1285 r = copy_to_user(buf, ptr, cur_size); 1286 kunmap(adev->gart.pages[p]); 1287 } else 1288 r = clear_user(buf, cur_size); 1289 1290 if (r) 1291 return -EFAULT; 1292 1293 result += cur_size; 1294 buf += cur_size; 1295 *pos += cur_size; 1296 size -= cur_size; 1297 } 1298 1299 return result; 1300 } 1301 1302 static const struct file_operations amdgpu_ttm_gtt_fops = { 1303 .owner = THIS_MODULE, 1304 .read = amdgpu_ttm_gtt_read, 1305 .llseek = default_llseek 1306 }; 1307 1308 #endif 1309 1310 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 1311 { 1312 #if defined(CONFIG_DEBUG_FS) 1313 unsigned count; 1314 1315 struct drm_minor *minor = adev->ddev->primary; 1316 struct dentry *ent, *root = minor->debugfs_root; 1317 1318 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, 1319 adev, &amdgpu_ttm_vram_fops); 1320 if (IS_ERR(ent)) 1321 return PTR_ERR(ent); 1322 i_size_write(ent->d_inode, adev->mc.mc_vram_size); 1323 adev->mman.vram = ent; 1324 1325 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, 1326 adev, &amdgpu_ttm_gtt_fops); 1327 if (IS_ERR(ent)) 1328 return PTR_ERR(ent); 1329 i_size_write(ent->d_inode, adev->mc.gtt_size); 1330 adev->mman.gtt = ent; 1331 1332 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 1333 1334 #ifdef CONFIG_SWIOTLB 1335 if (!swiotlb_nr_tbl()) 1336 --count; 1337 #endif 1338 1339 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 1340 #else 1341 1342 return 0; 1343 #endif 1344 } 1345 1346 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) 1347 { 1348 #if defined(CONFIG_DEBUG_FS) 1349 1350 debugfs_remove(adev->mman.vram); 1351 adev->mman.vram = NULL; 1352 1353 debugfs_remove(adev->mman.gtt); 1354 adev->mman.gtt = NULL; 1355 #endif 1356 } 1357