1 /* $NetBSD: amdgpu_ttm.c,v 1.5 2020/02/14 04:38:23 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 Jerome Glisse. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Jerome Glisse <glisse@freedesktop.org> 31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 32 * Dave Airlie 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ttm.c,v 1.5 2020/02/14 04:38:23 riastradh Exp $"); 36 37 #include <ttm/ttm_bo_api.h> 38 #include <ttm/ttm_bo_driver.h> 39 #include <ttm/ttm_placement.h> 40 #include <ttm/ttm_module.h> 41 #include <ttm/ttm_page_alloc.h> 42 #include <drm/drmP.h> 43 #include <drm/amdgpu_drm.h> 44 #include <linux/seq_file.h> 45 #include <linux/slab.h> 46 #include <linux/swiotlb.h> 47 #include <linux/swap.h> 48 #include <linux/pagemap.h> 49 #include <linux/debugfs.h> 50 #include "amdgpu.h" 51 #include "bif/bif_4_1_d.h" 52 53 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 54 55 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 56 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); 57 58 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev) 59 { 60 struct amdgpu_mman *mman; 61 struct amdgpu_device *adev; 62 63 mman = container_of(bdev, struct amdgpu_mman, bdev); 64 adev = container_of(mman, struct amdgpu_device, mman); 65 return adev; 66 } 67 68 69 /* 70 * Global memory. 71 */ 72 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) 73 { 74 return ttm_mem_global_init(ref->object); 75 } 76 77 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) 78 { 79 ttm_mem_global_release(ref->object); 80 } 81 82 static int amdgpu_ttm_global_init(struct amdgpu_device *adev) 83 { 84 struct drm_global_reference *global_ref; 85 int r; 86 87 adev->mman.mem_global_referenced = false; 88 global_ref = &adev->mman.mem_global_ref; 89 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 90 global_ref->size = sizeof(struct ttm_mem_global); 91 global_ref->init = &amdgpu_ttm_mem_global_init; 92 global_ref->release = &amdgpu_ttm_mem_global_release; 93 r = drm_global_item_ref(global_ref); 94 if (r != 0) { 95 DRM_ERROR("Failed setting up TTM memory accounting " 96 "subsystem.\n"); 97 return r; 98 } 99 100 adev->mman.bo_global_ref.mem_glob = 101 adev->mman.mem_global_ref.object; 102 global_ref = &adev->mman.bo_global_ref.ref; 103 global_ref->global_type = DRM_GLOBAL_TTM_BO; 104 global_ref->size = sizeof(struct ttm_bo_global); 105 global_ref->init = &ttm_bo_global_init; 106 global_ref->release = &ttm_bo_global_release; 107 r = drm_global_item_ref(global_ref); 108 if (r != 0) { 109 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 110 drm_global_item_unref(&adev->mman.mem_global_ref); 111 return r; 112 } 113 114 adev->mman.mem_global_referenced = true; 115 return 0; 116 } 117 118 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) 119 { 120 if (adev->mman.mem_global_referenced) { 121 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 122 drm_global_item_unref(&adev->mman.mem_global_ref); 123 adev->mman.mem_global_referenced = false; 124 } 125 } 126 127 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 128 { 129 return 0; 130 } 131 132 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 133 struct ttm_mem_type_manager *man) 134 { 135 struct amdgpu_device *adev; 136 137 adev = amdgpu_get_adev(bdev); 138 139 switch (type) { 140 case TTM_PL_SYSTEM: 141 /* System memory */ 142 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 143 man->available_caching = TTM_PL_MASK_CACHING; 144 man->default_caching = TTM_PL_FLAG_CACHED; 145 break; 146 case TTM_PL_TT: 147 man->func = &ttm_bo_manager_func; 148 man->gpu_offset = adev->mc.gtt_start; 149 man->available_caching = TTM_PL_MASK_CACHING; 150 man->default_caching = TTM_PL_FLAG_CACHED; 151 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 152 break; 153 case TTM_PL_VRAM: 154 /* "On-card" video ram */ 155 man->func = &ttm_bo_manager_func; 156 man->gpu_offset = adev->mc.vram_start; 157 man->flags = TTM_MEMTYPE_FLAG_FIXED | 158 TTM_MEMTYPE_FLAG_MAPPABLE; 159 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 160 man->default_caching = TTM_PL_FLAG_WC; 161 break; 162 case AMDGPU_PL_GDS: 163 case AMDGPU_PL_GWS: 164 case AMDGPU_PL_OA: 165 /* On-chip GDS memory*/ 166 man->func = &ttm_bo_manager_func; 167 man->gpu_offset = 0; 168 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; 169 man->available_caching = TTM_PL_FLAG_UNCACHED; 170 man->default_caching = TTM_PL_FLAG_UNCACHED; 171 break; 172 default: 173 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 174 return -EINVAL; 175 } 176 return 0; 177 } 178 179 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 180 struct ttm_placement *placement) 181 { 182 struct amdgpu_bo *rbo; 183 static struct ttm_place placements = { 184 .fpfn = 0, 185 .lpfn = 0, 186 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 187 }; 188 189 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { 190 placement->placement = &placements; 191 placement->busy_placement = &placements; 192 placement->num_placement = 1; 193 placement->num_busy_placement = 1; 194 return; 195 } 196 rbo = container_of(bo, struct amdgpu_bo, tbo); 197 switch (bo->mem.mem_type) { 198 case TTM_PL_VRAM: 199 if (rbo->adev->mman.buffer_funcs_ring->ready == false) 200 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); 201 else 202 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT); 203 break; 204 case TTM_PL_TT: 205 default: 206 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); 207 } 208 *placement = rbo->placement; 209 } 210 211 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 212 { 213 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); 214 215 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 216 } 217 218 static void amdgpu_move_null(struct ttm_buffer_object *bo, 219 struct ttm_mem_reg *new_mem) 220 { 221 struct ttm_mem_reg *old_mem = &bo->mem; 222 223 BUG_ON(old_mem->mm_node != NULL); 224 *old_mem = *new_mem; 225 new_mem->mm_node = NULL; 226 } 227 228 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 229 bool evict, bool no_wait_gpu, 230 struct ttm_mem_reg *new_mem, 231 struct ttm_mem_reg *old_mem) 232 { 233 struct amdgpu_device *adev; 234 struct amdgpu_ring *ring; 235 uint64_t old_start, new_start; 236 struct fence *fence; 237 int r; 238 239 adev = amdgpu_get_adev(bo->bdev); 240 ring = adev->mman.buffer_funcs_ring; 241 old_start = (u64)old_mem->start << PAGE_SHIFT; 242 new_start = (u64)new_mem->start << PAGE_SHIFT; 243 244 switch (old_mem->mem_type) { 245 case TTM_PL_VRAM: 246 old_start += adev->mc.vram_start; 247 break; 248 case TTM_PL_TT: 249 old_start += adev->mc.gtt_start; 250 break; 251 default: 252 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 253 return -EINVAL; 254 } 255 switch (new_mem->mem_type) { 256 case TTM_PL_VRAM: 257 new_start += adev->mc.vram_start; 258 break; 259 case TTM_PL_TT: 260 new_start += adev->mc.gtt_start; 261 break; 262 default: 263 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 264 return -EINVAL; 265 } 266 if (!ring->ready) { 267 DRM_ERROR("Trying to move memory with ring turned off.\n"); 268 return -EINVAL; 269 } 270 271 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); 272 273 r = amdgpu_copy_buffer(ring, old_start, new_start, 274 new_mem->num_pages * PAGE_SIZE, /* bytes */ 275 bo->resv, &fence); 276 /* FIXME: handle copy error */ 277 r = ttm_bo_move_accel_cleanup(bo, fence, 278 evict, no_wait_gpu, new_mem); 279 fence_put(fence); 280 return r; 281 } 282 283 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, 284 bool evict, bool interruptible, 285 bool no_wait_gpu, 286 struct ttm_mem_reg *new_mem) 287 { 288 struct amdgpu_device *adev __unused; 289 struct ttm_mem_reg *old_mem = &bo->mem; 290 struct ttm_mem_reg tmp_mem; 291 struct ttm_place placements; 292 struct ttm_placement placement; 293 int r; 294 295 adev = amdgpu_get_adev(bo->bdev); 296 tmp_mem = *new_mem; 297 tmp_mem.mm_node = NULL; 298 placement.num_placement = 1; 299 placement.placement = &placements; 300 placement.num_busy_placement = 1; 301 placement.busy_placement = &placements; 302 placements.fpfn = 0; 303 placements.lpfn = 0; 304 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 305 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 306 interruptible, no_wait_gpu); 307 if (unlikely(r)) { 308 return r; 309 } 310 311 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 312 if (unlikely(r)) { 313 goto out_cleanup; 314 } 315 316 r = ttm_tt_bind(bo->ttm, &tmp_mem); 317 if (unlikely(r)) { 318 goto out_cleanup; 319 } 320 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 321 if (unlikely(r)) { 322 goto out_cleanup; 323 } 324 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 325 out_cleanup: 326 ttm_bo_mem_put(bo, &tmp_mem); 327 return r; 328 } 329 330 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, 331 bool evict, bool interruptible, 332 bool no_wait_gpu, 333 struct ttm_mem_reg *new_mem) 334 { 335 struct amdgpu_device *adev __unused; 336 struct ttm_mem_reg *old_mem = &bo->mem; 337 struct ttm_mem_reg tmp_mem; 338 struct ttm_placement placement; 339 struct ttm_place placements; 340 int r; 341 342 adev = amdgpu_get_adev(bo->bdev); 343 tmp_mem = *new_mem; 344 tmp_mem.mm_node = NULL; 345 placement.num_placement = 1; 346 placement.placement = &placements; 347 placement.num_busy_placement = 1; 348 placement.busy_placement = &placements; 349 placements.fpfn = 0; 350 placements.lpfn = 0; 351 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 352 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 353 interruptible, no_wait_gpu); 354 if (unlikely(r)) { 355 return r; 356 } 357 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 358 if (unlikely(r)) { 359 goto out_cleanup; 360 } 361 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 362 if (unlikely(r)) { 363 goto out_cleanup; 364 } 365 out_cleanup: 366 ttm_bo_mem_put(bo, &tmp_mem); 367 return r; 368 } 369 370 static int amdgpu_bo_move(struct ttm_buffer_object *bo, 371 bool evict, bool interruptible, 372 bool no_wait_gpu, 373 struct ttm_mem_reg *new_mem) 374 { 375 struct amdgpu_device *adev; 376 struct ttm_mem_reg *old_mem = &bo->mem; 377 int r; 378 379 adev = amdgpu_get_adev(bo->bdev); 380 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 381 amdgpu_move_null(bo, new_mem); 382 return 0; 383 } 384 if ((old_mem->mem_type == TTM_PL_TT && 385 new_mem->mem_type == TTM_PL_SYSTEM) || 386 (old_mem->mem_type == TTM_PL_SYSTEM && 387 new_mem->mem_type == TTM_PL_TT)) { 388 /* bind is enough */ 389 amdgpu_move_null(bo, new_mem); 390 return 0; 391 } 392 if (adev->mman.buffer_funcs == NULL || 393 adev->mman.buffer_funcs_ring == NULL || 394 !adev->mman.buffer_funcs_ring->ready) { 395 /* use memcpy */ 396 goto memcpy; 397 } 398 399 if (old_mem->mem_type == TTM_PL_VRAM && 400 new_mem->mem_type == TTM_PL_SYSTEM) { 401 r = amdgpu_move_vram_ram(bo, evict, interruptible, 402 no_wait_gpu, new_mem); 403 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 404 new_mem->mem_type == TTM_PL_VRAM) { 405 r = amdgpu_move_ram_vram(bo, evict, interruptible, 406 no_wait_gpu, new_mem); 407 } else { 408 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 409 } 410 411 if (r) { 412 memcpy: 413 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 414 if (r) { 415 return r; 416 } 417 } 418 419 /* update statistics */ 420 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 421 return 0; 422 } 423 424 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 425 { 426 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 427 struct amdgpu_device *adev = amdgpu_get_adev(bdev); 428 429 mem->bus.addr = NULL; 430 mem->bus.offset = 0; 431 mem->bus.size = mem->num_pages << PAGE_SHIFT; 432 mem->bus.base = 0; 433 mem->bus.is_iomem = false; 434 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 435 return -EINVAL; 436 switch (mem->mem_type) { 437 case TTM_PL_SYSTEM: 438 /* system memory */ 439 return 0; 440 case TTM_PL_TT: 441 break; 442 case TTM_PL_VRAM: 443 mem->bus.offset = mem->start << PAGE_SHIFT; 444 /* check if it's visible */ 445 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) 446 return -EINVAL; 447 mem->bus.base = adev->mc.aper_base; 448 mem->bus.is_iomem = true; 449 #ifdef __alpha__ 450 /* 451 * Alpha: use bus.addr to hold the ioremap() return, 452 * so we can modify bus.base below. 453 */ 454 if (mem->placement & TTM_PL_FLAG_WC) 455 mem->bus.addr = 456 ioremap_wc(mem->bus.base + mem->bus.offset, 457 mem->bus.size); 458 else 459 mem->bus.addr = 460 ioremap_nocache(mem->bus.base + mem->bus.offset, 461 mem->bus.size); 462 463 /* 464 * Alpha: Use just the bus offset plus 465 * the hose/domain memory base for bus.base. 466 * It then can be used to build PTEs for VRAM 467 * access, as done in ttm_bo_vm_fault(). 468 */ 469 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 470 adev->ddev->hose->dense_mem_base; 471 #endif 472 break; 473 default: 474 return -EINVAL; 475 } 476 return 0; 477 } 478 479 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 480 { 481 } 482 483 /* 484 * TTM backend functions. 485 */ 486 struct amdgpu_ttm_tt { 487 struct ttm_dma_tt ttm; 488 struct amdgpu_device *adev; 489 u64 offset; 490 uint64_t userptr; 491 #ifdef __NetBSD__ 492 struct vmspace *usermm; 493 #else 494 struct mm_struct *usermm; 495 #endif 496 uint32_t userflags; 497 }; 498 499 /* prepare the sg table with the user pages */ 500 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 501 { 502 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); 503 struct amdgpu_ttm_tt *gtt = (void *)ttm; 504 #ifndef __NetBSD__ 505 unsigned pinned = 0, nents; 506 #endif 507 int r; 508 509 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 510 #ifndef __NetBSD__ 511 enum dma_data_direction direction = write ? 512 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 513 #endif 514 515 #ifdef __NetBSD__ 516 if (curproc->p_vmspace != gtt->usermm) 517 return -EPERM; 518 #else 519 if (current->mm != gtt->usermm) 520 return -EPERM; 521 #endif 522 523 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { 524 /* check that we only pin down anonymous memory 525 to prevent problems with writeback */ 526 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 527 #ifdef __NetBSD__ 528 /* XXX ??? TOCTOU, anyone? */ 529 /* XXX should do range_test */ 530 struct vm_map_entry *entry; 531 bool ok; 532 vm_map_lock_read(>t->usermm->vm_map); 533 ok = uvm_map_lookup_entry(>t->usermm->vm_map, 534 (vaddr_t)gtt->userptr, &entry); 535 if (ok) 536 ok = !UVM_ET_ISOBJ(entry) && end <= entry->end; 537 vm_map_unlock_read(>t->usermm->vm_map); 538 if (!ok) 539 return -EPERM; 540 #else 541 struct vm_area_struct *vma; 542 543 vma = find_vma(gtt->usermm, gtt->userptr); 544 if (!vma || vma->vm_file || vma->vm_end < end) 545 return -EPERM; 546 #endif 547 } 548 549 #ifdef __NetBSD__ 550 struct iovec iov = { 551 .iov_base = (void *)(vaddr_t)gtt->userptr, 552 .iov_len = ttm->num_pages << PAGE_SHIFT, 553 }; 554 struct uio uio = { 555 .uio_iov = &iov, 556 .uio_iovcnt = 1, 557 .uio_offset = 0, 558 .uio_resid = ttm->num_pages << PAGE_SHIFT, 559 .uio_rw = (write ? UIO_READ : UIO_WRITE), /* XXX ??? */ 560 .uio_vmspace = gtt->usermm, 561 }; 562 unsigned long i; 563 564 /* Wire the relevant part of the user's address space. */ 565 /* XXX What happens if user does munmap? */ 566 /* XXX errno NetBSD->Linux */ 567 r = -uvm_vslock(gtt->usermm, (void *)(vaddr_t)gtt->userptr, 568 ttm->num_pages << PAGE_SHIFT, 569 (write ? VM_PROT_WRITE : VM_PROT_READ)); /* XXX ??? */ 570 if (r) 571 goto fail0; 572 573 /* Load it up for DMA. */ 574 /* XXX errno NetBSD->Linux */ 575 r = -bus_dmamap_load_uio(adev->ddev->dmat, gtt->ttm.dma_address, &uio, 576 BUS_DMA_WAITOK); 577 if (r) 578 goto fail1; 579 580 /* Get each of the pages as ttm requests. */ 581 for (i = 0; i < ttm->num_pages; i++) { 582 vaddr_t va = (vaddr_t)gtt->userptr + (i << PAGE_SHIFT); 583 paddr_t pa; 584 struct vm_page *vmp; 585 586 if (!pmap_extract(gtt->usermm->vm_map.pmap, va, &pa)) { 587 r = -EFAULT; 588 goto fail2; 589 } 590 vmp = PHYS_TO_VM_PAGE(pa); 591 ttm->pages[i] = container_of(vmp, struct page, p_vmp); 592 } 593 594 /* Success! */ 595 return 0; 596 597 fail2: while (i --> 0) 598 ttm->pages[i] = NULL; /* paranoia */ 599 bus_dmamap_unload(adev->ddev->dmat, gtt->ttm.dma_address); 600 fail1: uvm_vsunlock(gtt->usermm, (void *)(vaddr_t)gtt->userptr, 601 ttm->num_pages << PAGE_SHIFT); 602 fail0: return r; 603 #else 604 do { 605 unsigned num_pages = ttm->num_pages - pinned; 606 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 607 struct page **pages = ttm->pages + pinned; 608 609 r = get_user_pages(current, current->mm, userptr, num_pages, 610 write, 0, pages, NULL); 611 if (r < 0) 612 goto release_pages; 613 614 pinned += r; 615 616 } while (pinned < ttm->num_pages); 617 618 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 619 ttm->num_pages << PAGE_SHIFT, 620 GFP_KERNEL); 621 if (r) 622 goto release_sg; 623 624 r = -ENOMEM; 625 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 626 if (nents != ttm->sg->nents) 627 goto release_sg; 628 629 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 630 gtt->ttm.dma_address, ttm->num_pages); 631 632 return 0; 633 634 release_sg: 635 kfree(ttm->sg); 636 637 release_pages: 638 release_pages(ttm->pages, pinned, 0); 639 return r; 640 #endif 641 } 642 643 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 644 { 645 #ifdef __NetBSD__ 646 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); 647 struct amdgpu_ttm_tt *gtt = container_of(ttm, struct amdgpu_ttm_tt, 648 ttm.ttm); 649 650 bus_dmamap_unload(adev->ddev->dmat, gtt->ttm.dma_address); 651 uvm_vsunlock(gtt->usermm, (void *)(vaddr_t)gtt->userptr, 652 ttm->num_pages << PAGE_SHIFT); 653 #else 654 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); 655 struct amdgpu_ttm_tt *gtt = (void *)ttm; 656 struct sg_page_iter sg_iter; 657 658 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 659 enum dma_data_direction direction = write ? 660 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 661 662 /* double check that we don't free the table twice */ 663 if (!ttm->sg->sgl) 664 return; 665 666 /* free the sg table and pages again */ 667 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 668 669 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { 670 struct page *page = sg_page_iter_page(&sg_iter); 671 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 672 set_page_dirty(page); 673 674 mark_page_accessed(page); 675 page_cache_release(page); 676 } 677 678 sg_free_table(ttm->sg); 679 #endif 680 } 681 682 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 683 struct ttm_mem_reg *bo_mem) 684 { 685 struct amdgpu_ttm_tt *gtt = (void*)ttm; 686 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 687 int r; 688 689 if (gtt->userptr) { 690 r = amdgpu_ttm_tt_pin_userptr(ttm); 691 if (r) { 692 DRM_ERROR("failed to pin userptr\n"); 693 return r; 694 } 695 } 696 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 697 if (!ttm->num_pages) { 698 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 699 ttm->num_pages, bo_mem, ttm); 700 } 701 702 if (bo_mem->mem_type == AMDGPU_PL_GDS || 703 bo_mem->mem_type == AMDGPU_PL_GWS || 704 bo_mem->mem_type == AMDGPU_PL_OA) 705 return -EINVAL; 706 707 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, 708 ttm->pages, gtt->ttm.dma_address, flags); 709 710 if (r) { 711 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 712 ttm->num_pages, (unsigned)gtt->offset); 713 return r; 714 } 715 return 0; 716 } 717 718 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 719 { 720 struct amdgpu_ttm_tt *gtt = (void *)ttm; 721 722 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 723 if (gtt->adev->gart.ready) 724 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); 725 726 if (gtt->userptr) 727 amdgpu_ttm_tt_unpin_userptr(ttm); 728 729 return 0; 730 } 731 732 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 733 { 734 struct amdgpu_ttm_tt *gtt = (void *)ttm; 735 736 ttm_dma_tt_fini(>t->ttm); 737 kfree(gtt); 738 } 739 740 static struct ttm_backend_func amdgpu_backend_func = { 741 .bind = &amdgpu_ttm_backend_bind, 742 .unbind = &amdgpu_ttm_backend_unbind, 743 .destroy = &amdgpu_ttm_backend_destroy, 744 }; 745 746 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, 747 unsigned long size, uint32_t page_flags, 748 struct page *dummy_read_page) 749 { 750 struct amdgpu_device *adev; 751 struct amdgpu_ttm_tt *gtt; 752 753 adev = amdgpu_get_adev(bdev); 754 755 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 756 if (gtt == NULL) { 757 return NULL; 758 } 759 gtt->ttm.ttm.func = &amdgpu_backend_func; 760 gtt->adev = adev; 761 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 762 kfree(gtt); 763 return NULL; 764 } 765 return >t->ttm.ttm; 766 } 767 768 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) 769 { 770 #ifndef __NetBSD__ 771 struct amdgpu_device *adev; 772 #endif 773 struct amdgpu_ttm_tt *gtt = (void *)ttm; 774 #ifndef __NetBSD__ 775 unsigned i; 776 #endif 777 int r; 778 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 779 780 if (ttm->state != tt_unpopulated) 781 return 0; 782 783 if (gtt && gtt->userptr) { 784 #ifdef __NetBSD__ 785 ttm->sg = NULL; 786 #else 787 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 788 if (!ttm->sg) 789 return -ENOMEM; 790 #endif 791 792 ttm->page_flags |= TTM_PAGE_FLAG_SG; 793 ttm->state = tt_unbound; 794 return 0; 795 } 796 797 if (slave && ttm->sg) { 798 #ifdef __NetBSD__ 799 r = drm_prime_bus_dmamap_load_sgt(ttm->bdev->dmat, 800 gtt->ttm.dma_address, ttm->sg); 801 if (r) 802 return r; 803 #else 804 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 805 gtt->ttm.dma_address, ttm->num_pages); 806 #endif 807 ttm->state = tt_unbound; 808 return 0; 809 } 810 811 #ifdef __NetBSD__ 812 /* XXX errno NetBSD->Linux */ 813 return ttm_bus_dma_populate(>t->ttm); 814 #else 815 816 adev = amdgpu_get_adev(ttm->bdev); 817 818 #ifdef CONFIG_SWIOTLB 819 if (swiotlb_nr_tbl()) { 820 return ttm_dma_populate(>t->ttm, adev->dev); 821 } 822 #endif 823 824 r = ttm_pool_populate(ttm); 825 if (r) { 826 return r; 827 } 828 829 for (i = 0; i < ttm->num_pages; i++) { 830 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], 831 0, PAGE_SIZE, 832 PCI_DMA_BIDIRECTIONAL); 833 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { 834 while (i--) { 835 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 836 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 837 gtt->ttm.dma_address[i] = 0; 838 } 839 ttm_pool_unpopulate(ttm); 840 return -EFAULT; 841 } 842 } 843 return 0; 844 #endif /* __NetBSD__ */ 845 } 846 847 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 848 { 849 #ifndef __NetBSD__ 850 struct amdgpu_device *adev; 851 #endif 852 struct amdgpu_ttm_tt *gtt = (void *)ttm; 853 #ifndef __NetBSD__ 854 unsigned i; 855 #endif 856 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 857 858 if (gtt && gtt->userptr) { 859 kfree(ttm->sg); 860 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 861 return; 862 } 863 864 if (slave) 865 return; 866 867 #ifdef __NetBSD__ 868 ttm_bus_dma_unpopulate(>t->ttm); 869 return; 870 #else 871 872 adev = amdgpu_get_adev(ttm->bdev); 873 874 #ifdef CONFIG_SWIOTLB 875 if (swiotlb_nr_tbl()) { 876 ttm_dma_unpopulate(>t->ttm, adev->dev); 877 return; 878 } 879 #endif 880 881 for (i = 0; i < ttm->num_pages; i++) { 882 if (gtt->ttm.dma_address[i]) { 883 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 884 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 885 } 886 } 887 888 ttm_pool_unpopulate(ttm); 889 #endif /* __NetBSD__ */ 890 } 891 892 #ifdef __NetBSD__ 893 static void amdgpu_ttm_tt_swapout(struct ttm_tt *ttm) 894 { 895 struct amdgpu_ttm_tt *gtt = container_of(ttm, struct amdgpu_ttm_tt, 896 ttm.ttm); 897 struct ttm_dma_tt *ttm_dma = >t->ttm; 898 899 ttm_bus_dma_swapout(ttm_dma); 900 } 901 902 static const struct uvm_pagerops amdgpu_uvm_ops = { 903 .pgo_reference = &ttm_bo_uvm_reference, 904 .pgo_detach = &ttm_bo_uvm_detach, 905 .pgo_fault = &ttm_bo_uvm_fault, 906 }; 907 #endif 908 909 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 910 uint32_t flags) 911 { 912 struct amdgpu_ttm_tt *gtt = (void *)ttm; 913 914 if (gtt == NULL) 915 return -EINVAL; 916 917 gtt->userptr = addr; 918 #ifdef __NetBSD__ 919 gtt->usermm = curproc->p_vmspace; 920 #else 921 gtt->usermm = current->mm; 922 #endif 923 gtt->userflags = flags; 924 return 0; 925 } 926 927 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm) 928 { 929 struct amdgpu_ttm_tt *gtt = (void *)ttm; 930 931 if (gtt == NULL) 932 return false; 933 934 return !!gtt->userptr; 935 } 936 937 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 938 unsigned long end) 939 { 940 struct amdgpu_ttm_tt *gtt = (void *)ttm; 941 unsigned long size; 942 943 if (gtt == NULL) 944 return false; 945 946 if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr) 947 return false; 948 949 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 950 if (gtt->userptr > end || gtt->userptr + size <= start) 951 return false; 952 953 return true; 954 } 955 956 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 957 { 958 struct amdgpu_ttm_tt *gtt = (void *)ttm; 959 960 if (gtt == NULL) 961 return false; 962 963 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 964 } 965 966 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 967 struct ttm_mem_reg *mem) 968 { 969 uint32_t flags = 0; 970 971 if (mem && mem->mem_type != TTM_PL_SYSTEM) 972 flags |= AMDGPU_PTE_VALID; 973 974 if (mem && mem->mem_type == TTM_PL_TT) { 975 flags |= AMDGPU_PTE_SYSTEM; 976 977 if (ttm->caching_state == tt_cached) 978 flags |= AMDGPU_PTE_SNOOPED; 979 } 980 981 if (adev->asic_type >= CHIP_TONGA) 982 flags |= AMDGPU_PTE_EXECUTABLE; 983 984 flags |= AMDGPU_PTE_READABLE; 985 986 if (!amdgpu_ttm_tt_is_readonly(ttm)) 987 flags |= AMDGPU_PTE_WRITEABLE; 988 989 return flags; 990 } 991 992 static struct ttm_bo_driver amdgpu_bo_driver = { 993 .ttm_tt_create = &amdgpu_ttm_tt_create, 994 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 995 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 996 #ifdef __NetBSD__ 997 .ttm_tt_swapout = &amdgpu_ttm_tt_swapout, 998 .ttm_uvm_ops = &amdgpu_uvm_ops, 999 #endif 1000 .invalidate_caches = &amdgpu_invalidate_caches, 1001 .init_mem_type = &amdgpu_init_mem_type, 1002 .evict_flags = &amdgpu_evict_flags, 1003 .move = &amdgpu_bo_move, 1004 .verify_access = &amdgpu_verify_access, 1005 .move_notify = &amdgpu_bo_move_notify, 1006 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1007 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1008 .io_mem_free = &amdgpu_ttm_io_mem_free, 1009 }; 1010 1011 int amdgpu_ttm_init(struct amdgpu_device *adev) 1012 { 1013 int r; 1014 1015 r = amdgpu_ttm_global_init(adev); 1016 if (r) { 1017 return r; 1018 } 1019 /* No others user of address space so set it to 0 */ 1020 r = ttm_bo_device_init(&adev->mman.bdev, 1021 adev->mman.bo_global_ref.ref.object, 1022 &amdgpu_bo_driver, 1023 #ifdef __NetBSD__ 1024 adev->ddev->bst, 1025 adev->ddev->dmat, 1026 #else 1027 adev->ddev->anon_inode->i_mapping, 1028 #endif 1029 DRM_FILE_PAGE_OFFSET, 1030 adev->need_dma32); 1031 if (r) { 1032 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1033 return r; 1034 } 1035 adev->mman.initialized = true; 1036 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1037 adev->mc.real_vram_size >> PAGE_SHIFT); 1038 if (r) { 1039 DRM_ERROR("Failed initializing VRAM heap.\n"); 1040 return r; 1041 } 1042 /* Change the size here instead of the init above so only lpfn is affected */ 1043 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 1044 1045 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, 1046 AMDGPU_GEM_DOMAIN_VRAM, 1047 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 1048 NULL, NULL, &adev->stollen_vga_memory); 1049 if (r) { 1050 return r; 1051 } 1052 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1053 if (r) 1054 return r; 1055 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); 1056 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1057 if (r) { 1058 amdgpu_bo_unref(&adev->stollen_vga_memory); 1059 return r; 1060 } 1061 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1062 (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); 1063 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, 1064 adev->mc.gtt_size >> PAGE_SHIFT); 1065 if (r) { 1066 DRM_ERROR("Failed initializing GTT heap.\n"); 1067 return r; 1068 } 1069 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1070 (unsigned)(adev->mc.gtt_size / (1024 * 1024))); 1071 1072 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; 1073 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; 1074 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; 1075 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; 1076 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; 1077 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; 1078 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; 1079 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; 1080 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; 1081 /* GDS Memory */ 1082 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 1083 adev->gds.mem.total_size >> PAGE_SHIFT); 1084 if (r) { 1085 DRM_ERROR("Failed initializing GDS heap.\n"); 1086 return r; 1087 } 1088 1089 /* GWS */ 1090 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 1091 adev->gds.gws.total_size >> PAGE_SHIFT); 1092 if (r) { 1093 DRM_ERROR("Failed initializing gws heap.\n"); 1094 return r; 1095 } 1096 1097 /* OA */ 1098 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 1099 adev->gds.oa.total_size >> PAGE_SHIFT); 1100 if (r) { 1101 DRM_ERROR("Failed initializing oa heap.\n"); 1102 return r; 1103 } 1104 1105 r = amdgpu_ttm_debugfs_init(adev); 1106 if (r) { 1107 DRM_ERROR("Failed to init debugfs\n"); 1108 return r; 1109 } 1110 return 0; 1111 } 1112 1113 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1114 { 1115 int r; 1116 1117 if (!adev->mman.initialized) 1118 return; 1119 amdgpu_ttm_debugfs_fini(adev); 1120 if (adev->stollen_vga_memory) { 1121 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1122 if (r == 0) { 1123 amdgpu_bo_unpin(adev->stollen_vga_memory); 1124 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1125 } 1126 amdgpu_bo_unref(&adev->stollen_vga_memory); 1127 } 1128 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 1129 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 1130 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 1131 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 1132 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 1133 ttm_bo_device_release(&adev->mman.bdev); 1134 amdgpu_gart_fini(adev); 1135 amdgpu_ttm_global_fini(adev); 1136 adev->mman.initialized = false; 1137 DRM_INFO("amdgpu: ttm finalized\n"); 1138 } 1139 1140 /* this should only be called at bootup or when userspace 1141 * isn't running */ 1142 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) 1143 { 1144 struct ttm_mem_type_manager *man; 1145 1146 if (!adev->mman.initialized) 1147 return; 1148 1149 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 1150 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1151 man->size = size >> PAGE_SHIFT; 1152 } 1153 1154 #ifdef __NetBSD__ 1155 1156 int 1157 amdgpu_mmap_object(struct drm_device *dev, off_t offset, size_t size, 1158 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp, 1159 struct file *file) 1160 { 1161 struct amdgpu_device *adev = dev->dev_private; 1162 1163 KASSERT(0 == (offset & (PAGE_SIZE - 1))); 1164 1165 if (__predict_false(adev == NULL)) /* XXX How?? */ 1166 return -EINVAL; 1167 1168 if (__predict_false((offset >> PAGE_SHIFT) < DRM_FILE_PAGE_OFFSET)) 1169 return -EINVAL; 1170 1171 return ttm_bo_mmap_object(&adev->mman.bdev, offset, size, prot, 1172 uobjp, uoffsetp, file); 1173 } 1174 1175 #else /* __NetBSD__ */ 1176 1177 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1178 { 1179 struct drm_file *file_priv; 1180 struct amdgpu_device *adev; 1181 1182 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 1183 return -EINVAL; 1184 1185 file_priv = filp->private_data; 1186 adev = file_priv->minor->dev->dev_private; 1187 if (adev == NULL) 1188 return -EINVAL; 1189 1190 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1191 } 1192 1193 #endif /* __NetBSD__ */ 1194 1195 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 1196 uint64_t src_offset, 1197 uint64_t dst_offset, 1198 uint32_t byte_count, 1199 struct reservation_object *resv, 1200 struct fence **fence) 1201 { 1202 struct amdgpu_device *adev = ring->adev; 1203 uint32_t max_bytes; 1204 unsigned num_loops, num_dw; 1205 struct amdgpu_ib *ib; 1206 unsigned i; 1207 int r; 1208 1209 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1210 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1211 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; 1212 1213 /* for IB padding */ 1214 while (num_dw & 0x7) 1215 num_dw++; 1216 1217 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); 1218 if (!ib) 1219 return -ENOMEM; 1220 1221 r = amdgpu_ib_get(ring, NULL, num_dw * 4, ib); 1222 if (r) { 1223 kfree(ib); 1224 return r; 1225 } 1226 1227 ib->length_dw = 0; 1228 1229 if (resv) { 1230 r = amdgpu_sync_resv(adev, &ib->sync, resv, 1231 AMDGPU_FENCE_OWNER_UNDEFINED); 1232 if (r) { 1233 DRM_ERROR("sync failed (%d).\n", r); 1234 goto error_free; 1235 } 1236 } 1237 1238 for (i = 0; i < num_loops; i++) { 1239 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1240 1241 amdgpu_emit_copy_buffer(adev, ib, src_offset, dst_offset, 1242 cur_size_in_bytes); 1243 1244 src_offset += cur_size_in_bytes; 1245 dst_offset += cur_size_in_bytes; 1246 byte_count -= cur_size_in_bytes; 1247 } 1248 1249 amdgpu_vm_pad_ib(adev, ib); 1250 WARN_ON(ib->length_dw > num_dw); 1251 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, 1252 &amdgpu_vm_free_job, 1253 AMDGPU_FENCE_OWNER_UNDEFINED, 1254 fence); 1255 if (r) 1256 goto error_free; 1257 1258 if (!amdgpu_enable_scheduler) { 1259 amdgpu_ib_free(adev, ib); 1260 kfree(ib); 1261 } 1262 return 0; 1263 error_free: 1264 amdgpu_ib_free(adev, ib); 1265 kfree(ib); 1266 return r; 1267 } 1268 1269 #if defined(CONFIG_DEBUG_FS) 1270 1271 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 1272 { 1273 struct drm_info_node *node = (struct drm_info_node *)m->private; 1274 unsigned ttm_pl = *(int *)node->info_ent->data; 1275 struct drm_device *dev = node->minor->dev; 1276 struct amdgpu_device *adev = dev->dev_private; 1277 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; 1278 int ret; 1279 struct ttm_bo_global *glob = adev->mman.bdev.glob; 1280 1281 spin_lock(&glob->lru_lock); 1282 ret = drm_mm_dump_table(m, mm); 1283 spin_unlock(&glob->lru_lock); 1284 if (ttm_pl == TTM_PL_VRAM) 1285 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", 1286 adev->mman.bdev.man[ttm_pl].size, 1287 (u64)atomic64_read(&adev->vram_usage) >> 20, 1288 (u64)atomic64_read(&adev->vram_vis_usage) >> 20); 1289 return ret; 1290 } 1291 1292 static int ttm_pl_vram = TTM_PL_VRAM; 1293 static int ttm_pl_tt = TTM_PL_TT; 1294 1295 static struct drm_info_list amdgpu_ttm_debugfs_list[] = { 1296 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, 1297 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, 1298 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 1299 #ifdef CONFIG_SWIOTLB 1300 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 1301 #endif 1302 }; 1303 1304 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 1305 size_t size, loff_t *pos) 1306 { 1307 struct amdgpu_device *adev = f->f_inode->i_private; 1308 ssize_t result = 0; 1309 int r; 1310 1311 if (size & 0x3 || *pos & 0x3) 1312 return -EINVAL; 1313 1314 if (*pos >= adev->mc.mc_vram_size) 1315 return -ENXIO; 1316 1317 while (size) { 1318 unsigned long flags; 1319 uint32_t value; 1320 1321 if (*pos >= adev->mc.mc_vram_size) 1322 return result; 1323 1324 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1325 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 1326 WREG32(mmMM_INDEX_HI, *pos >> 31); 1327 value = RREG32(mmMM_DATA); 1328 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1329 1330 r = put_user(value, (uint32_t *)buf); 1331 if (r) 1332 return r; 1333 1334 result += 4; 1335 buf += 4; 1336 *pos += 4; 1337 size -= 4; 1338 } 1339 1340 return result; 1341 } 1342 1343 static const struct file_operations amdgpu_ttm_vram_fops = { 1344 .owner = THIS_MODULE, 1345 .read = amdgpu_ttm_vram_read, 1346 .llseek = default_llseek 1347 }; 1348 1349 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 1350 size_t size, loff_t *pos) 1351 { 1352 struct amdgpu_device *adev = f->f_inode->i_private; 1353 ssize_t result = 0; 1354 int r; 1355 1356 while (size) { 1357 loff_t p = *pos / PAGE_SIZE; 1358 unsigned off = *pos & ~PAGE_MASK; 1359 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1360 struct page *page; 1361 void *ptr; 1362 1363 if (p >= adev->gart.num_cpu_pages) 1364 return result; 1365 1366 page = adev->gart.pages[p]; 1367 if (page) { 1368 ptr = kmap(page); 1369 ptr += off; 1370 1371 r = copy_to_user(buf, ptr, cur_size); 1372 kunmap(adev->gart.pages[p]); 1373 } else 1374 r = clear_user(buf, cur_size); 1375 1376 if (r) 1377 return -EFAULT; 1378 1379 result += cur_size; 1380 buf += cur_size; 1381 *pos += cur_size; 1382 size -= cur_size; 1383 } 1384 1385 return result; 1386 } 1387 1388 static const struct file_operations amdgpu_ttm_gtt_fops = { 1389 .owner = THIS_MODULE, 1390 .read = amdgpu_ttm_gtt_read, 1391 .llseek = default_llseek 1392 }; 1393 1394 #endif 1395 1396 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 1397 { 1398 #if defined(CONFIG_DEBUG_FS) 1399 unsigned count; 1400 1401 struct drm_minor *minor = adev->ddev->primary; 1402 struct dentry *ent, *root = minor->debugfs_root; 1403 1404 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, 1405 adev, &amdgpu_ttm_vram_fops); 1406 if (IS_ERR(ent)) 1407 return PTR_ERR(ent); 1408 i_size_write(ent->d_inode, adev->mc.mc_vram_size); 1409 adev->mman.vram = ent; 1410 1411 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, 1412 adev, &amdgpu_ttm_gtt_fops); 1413 if (IS_ERR(ent)) 1414 return PTR_ERR(ent); 1415 i_size_write(ent->d_inode, adev->mc.gtt_size); 1416 adev->mman.gtt = ent; 1417 1418 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 1419 1420 #ifdef CONFIG_SWIOTLB 1421 if (!swiotlb_nr_tbl()) 1422 --count; 1423 #endif 1424 1425 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 1426 #else 1427 1428 return 0; 1429 #endif 1430 } 1431 1432 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) 1433 { 1434 #if defined(CONFIG_DEBUG_FS) 1435 1436 debugfs_remove(adev->mman.vram); 1437 adev->mman.vram = NULL; 1438 1439 debugfs_remove(adev->mman.gtt); 1440 adev->mman.gtt = NULL; 1441 #endif 1442 } 1443