1 /* $NetBSD: amdgpu_pll.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_pll.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $"); 27 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #include "amdgpu.h" 31 #include "atom.h" 32 #include "atombios_encoders.h" 33 #include <asm/div64.h> 34 #include <linux/gcd.h> 35 36 #include "amdgpu_pll.h" 37 38 /** 39 * amdgpu_pll_reduce_ratio - fractional number reduction 40 * 41 * @nom: nominator 42 * @den: denominator 43 * @nom_min: minimum value for nominator 44 * @den_min: minimum value for denominator 45 * 46 * Find the greatest common divisor and apply it on both nominator and 47 * denominator, but make nominator and denominator are at least as large 48 * as their minimum values. 49 */ 50 static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den, 51 unsigned nom_min, unsigned den_min) 52 { 53 unsigned tmp; 54 55 /* reduce the numbers to a simpler ratio */ 56 tmp = gcd(*nom, *den); 57 *nom /= tmp; 58 *den /= tmp; 59 60 /* make sure nominator is large enough */ 61 if (*nom < nom_min) { 62 tmp = DIV_ROUND_UP(nom_min, *nom); 63 *nom *= tmp; 64 *den *= tmp; 65 } 66 67 /* make sure the denominator is large enough */ 68 if (*den < den_min) { 69 tmp = DIV_ROUND_UP(den_min, *den); 70 *nom *= tmp; 71 *den *= tmp; 72 } 73 } 74 75 /** 76 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation 77 * 78 * @nom: nominator 79 * @den: denominator 80 * @post_div: post divider 81 * @fb_div_max: feedback divider maximum 82 * @ref_div_max: reference divider maximum 83 * @fb_div: resulting feedback divider 84 * @ref_div: resulting reference divider 85 * 86 * Calculate feedback and reference divider for a given post divider. Makes 87 * sure we stay within the limits. 88 */ 89 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 90 unsigned fb_div_max, unsigned ref_div_max, 91 unsigned *fb_div, unsigned *ref_div) 92 { 93 /* limit reference * post divider to a maximum */ 94 ref_div_max = min(128 / post_div, ref_div_max); 95 96 /* get matching reference and feedback divider */ 97 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 99 100 /* limit fb divider to its maximum */ 101 if (*fb_div > fb_div_max) { 102 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 103 *fb_div = fb_div_max; 104 } 105 } 106 107 /** 108 * amdgpu_pll_compute - compute PLL paramaters 109 * 110 * @pll: information about the PLL 111 * @dot_clock_p: resulting pixel clock 112 * fb_div_p: resulting feedback divider 113 * frac_fb_div_p: fractional part of the feedback divider 114 * ref_div_p: resulting reference divider 115 * post_div_p: resulting reference divider 116 * 117 * Try to calculate the PLL parameters to generate the given frequency: 118 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 119 */ 120 void amdgpu_pll_compute(struct amdgpu_pll *pll, 121 u32 freq, 122 u32 *dot_clock_p, 123 u32 *fb_div_p, 124 u32 *frac_fb_div_p, 125 u32 *ref_div_p, 126 u32 *post_div_p) 127 { 128 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? 129 freq : freq / 10; 130 131 unsigned fb_div_min, fb_div_max, fb_div; 132 unsigned post_div_min, post_div_max, post_div; 133 unsigned ref_div_min, ref_div_max, ref_div; 134 unsigned post_div_best, diff_best; 135 unsigned nom, den; 136 137 /* determine allowed feedback divider range */ 138 fb_div_min = pll->min_feedback_div; 139 fb_div_max = pll->max_feedback_div; 140 141 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { 142 fb_div_min *= 10; 143 fb_div_max *= 10; 144 } 145 146 /* determine allowed ref divider range */ 147 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) 148 ref_div_min = pll->reference_div; 149 else 150 ref_div_min = pll->min_ref_div; 151 152 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && 153 pll->flags & AMDGPU_PLL_USE_REF_DIV) 154 ref_div_max = pll->reference_div; 155 else 156 ref_div_max = pll->max_ref_div; 157 158 /* determine allowed post divider range */ 159 if (pll->flags & AMDGPU_PLL_USE_POST_DIV) { 160 post_div_min = pll->post_div; 161 post_div_max = pll->post_div; 162 } else { 163 unsigned vco_min, vco_max; 164 165 if (pll->flags & AMDGPU_PLL_IS_LCD) { 166 vco_min = pll->lcd_pll_out_min; 167 vco_max = pll->lcd_pll_out_max; 168 } else { 169 vco_min = pll->pll_out_min; 170 vco_max = pll->pll_out_max; 171 } 172 173 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { 174 vco_min *= 10; 175 vco_max *= 10; 176 } 177 178 post_div_min = vco_min / target_clock; 179 if ((target_clock * post_div_min) < vco_min) 180 ++post_div_min; 181 if (post_div_min < pll->min_post_div) 182 post_div_min = pll->min_post_div; 183 184 post_div_max = vco_max / target_clock; 185 if ((target_clock * post_div_max) > vco_max) 186 --post_div_max; 187 if (post_div_max > pll->max_post_div) 188 post_div_max = pll->max_post_div; 189 } 190 191 /* represent the searched ratio as fractional number */ 192 nom = target_clock; 193 den = pll->reference_freq; 194 195 /* reduce the numbers to a simpler ratio */ 196 amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 197 198 /* now search for a post divider */ 199 if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP) 200 post_div_best = post_div_min; 201 else 202 post_div_best = post_div_max; 203 diff_best = ~0; 204 205 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 206 unsigned diff; 207 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, 208 ref_div_max, &fb_div, &ref_div); 209 diff = abs(target_clock - (pll->reference_freq * fb_div) / 210 (ref_div * post_div)); 211 212 if (diff < diff_best || (diff == diff_best && 213 !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) { 214 215 post_div_best = post_div; 216 diff_best = diff; 217 } 218 } 219 post_div = post_div_best; 220 221 /* get the feedback and reference divider for the optimal value */ 222 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 223 &fb_div, &ref_div); 224 225 /* reduce the numbers to a simpler ratio once more */ 226 /* this also makes sure that the reference divider is large enough */ 227 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 228 229 /* avoid high jitter with small fractional dividers */ 230 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 231 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60); 232 if (fb_div < fb_div_min) { 233 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 234 fb_div *= tmp; 235 ref_div *= tmp; 236 } 237 } 238 239 /* and finally save the result */ 240 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { 241 *fb_div_p = fb_div / 10; 242 *frac_fb_div_p = fb_div % 10; 243 } else { 244 *fb_div_p = fb_div; 245 *frac_fb_div_p = 0; 246 } 247 248 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 249 (pll->reference_freq * *frac_fb_div_p)) / 250 (ref_div * post_div * 10); 251 *ref_div_p = ref_div; 252 *post_div_p = post_div; 253 254 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 255 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 256 ref_div, post_div); 257 } 258 259 /** 260 * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use 261 * 262 * @crtc: drm crtc 263 * 264 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 265 */ 266 u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc) 267 { 268 struct drm_device *dev = crtc->dev; 269 struct drm_crtc *test_crtc; 270 struct amdgpu_crtc *test_amdgpu_crtc; 271 u32 pll_in_use = 0; 272 273 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 274 if (crtc == test_crtc) 275 continue; 276 277 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); 278 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) 279 pll_in_use |= (1 << test_amdgpu_crtc->pll_id); 280 } 281 return pll_in_use; 282 } 283 284 /** 285 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP 286 * 287 * @crtc: drm crtc 288 * 289 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 290 * also in DP mode. For DP, a single PPLL can be used for all DP 291 * crtcs/encoders. 292 */ 293 int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc) 294 { 295 struct drm_device *dev = crtc->dev; 296 struct drm_crtc *test_crtc; 297 struct amdgpu_crtc *test_amdgpu_crtc; 298 299 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 300 if (crtc == test_crtc) 301 continue; 302 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); 303 if (test_amdgpu_crtc->encoder && 304 ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) { 305 /* for DP use the same PLL for all */ 306 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) 307 return test_amdgpu_crtc->pll_id; 308 } 309 } 310 return ATOM_PPLL_INVALID; 311 } 312 313 /** 314 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 315 * 316 * @crtc: drm crtc 317 * @encoder: drm encoder 318 * 319 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 320 * be shared (i.e., same clock). 321 */ 322 int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc) 323 { 324 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 325 struct drm_device *dev = crtc->dev; 326 struct drm_crtc *test_crtc; 327 struct amdgpu_crtc *test_amdgpu_crtc; 328 u32 adjusted_clock, test_adjusted_clock; 329 330 adjusted_clock = amdgpu_crtc->adjusted_clock; 331 332 if (adjusted_clock == 0) 333 return ATOM_PPLL_INVALID; 334 335 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 336 if (crtc == test_crtc) 337 continue; 338 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); 339 if (test_amdgpu_crtc->encoder && 340 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) { 341 /* check if we are already driving this connector with another crtc */ 342 if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) { 343 /* if we are, return that pll */ 344 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) 345 return test_amdgpu_crtc->pll_id; 346 } 347 /* for non-DP check the clock */ 348 test_adjusted_clock = test_amdgpu_crtc->adjusted_clock; 349 if ((crtc->mode.clock == test_crtc->mode.clock) && 350 (adjusted_clock == test_adjusted_clock) && 351 (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) && 352 (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)) 353 return test_amdgpu_crtc->pll_id; 354 } 355 } 356 return ATOM_PPLL_INVALID; 357 } 358